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| author | Yue Du <daviddu@us.ibm.com> | 2017-01-11 23:37:55 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:07:15 -0500 |
| commit | db3fc618046c94c8df3dfc66ac883a3be8151eb4 (patch) | |
| tree | 7d623a4b440cc5f41b64d242eaa41d0643d366d1 | |
| parent | 3df424c99c4a9a7c7b9e1e02a5a799256f23a3b6 (diff) | |
| download | talos-hcode-db3fc618046c94c8df3dfc66ac883a3be8151eb4.tar.gz talos-hcode-db3fc618046c94c8df3dfc66ac883a3be8151eb4.zip | |
STOP: optimize size of stop images
1) optimize scom with no rc and directly inline asm(saved for 2K :D)
2) initialize all variables(doesnt really save size, just good guideline)
3) loop both cores when block is big and redundant(saved only 50B -_-)
(50b for 3 blocks, each block saves 17b, or 4 instructions)
4) improvement on history update(saved 500B more :))
5) functionalize the exit catchup routine which is identical twice
(this back fired and cost us 100B :()
6) functionalize the eval eimr override macro which is identical twice
(saved 130B :|)
7) finally the saving is about 2728B on CME
8) apply history update tech to sgpe, found bug in the tech, fixed
(but our saving is back to ~2500B)
9) clean up sgpe redundent ex branching code
(same as cme saved only about ~60B)
10) rebase
Change-Id: I3664d6a2dcab85f896a583852afde948e635bd02
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34777
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
31 files changed, 910 insertions, 1364 deletions
diff --git a/import/chips/p9/common/pmlib/include/cmehw_common.h b/import/chips/p9/common/pmlib/include/cmehw_common.h index 69598baa..51b0f4d4 100644 --- a/import/chips/p9/common/pmlib/include/cmehw_common.h +++ b/import/chips/p9/common/pmlib/include/cmehw_common.h @@ -59,18 +59,20 @@ enum CME_SCOM_CONTROLS CME_SCOM_QUEUED = 3 }; + + #define CME_SCOM_ADDR(addr, core, op) (addr | (core << 22) | (op << 20)) #if defined(USE_CME_QUEUED_SCOM) && defined(USE_PPE_IMPRECISE_MODE) #define CME_GETSCOM(addr, core, scom_op, data) \ - getscom(0, CME_SCOM_ADDR(addr, core, CME_SCOM_QUEUED), &data); + PPE_LVD(CME_SCOM_ADDR(addr, core, CME_SCOM_QUEUED), data); #define CME_PUTSCOM(addr, core, data) \ - putscom(0, CME_SCOM_ADDR(addr, core, CME_SCOM_QUEUED), data); + putscom_norc(CME_SCOM_ADDR(addr, core, CME_SCOM_QUEUED), data); #else #define CME_GETSCOM(addr, core, scom_op, data) \ - getscom(0, CME_SCOM_ADDR(addr, core, scom_op), &data); + PPE_LVD(CME_SCOM_ADDR(addr, core, scom_op), data); #define CME_PUTSCOM(addr, core, data) \ - putscom(0, CME_SCOM_ADDR(addr, core, CME_SCOM_NOP), data); + putscom_norc(CME_SCOM_ADDR(addr, core, CME_SCOM_NOP), data); #endif #endif /* __CMEHW_COMMON_H__ */ diff --git a/import/chips/p9/common/pmlib/include/gpehw_common.h b/import/chips/p9/common/pmlib/include/gpehw_common.h index 486fdb1e..b81aaef4 100644 --- a/import/chips/p9/common/pmlib/include/gpehw_common.h +++ b/import/chips/p9/common/pmlib/include/gpehw_common.h @@ -92,15 +92,15 @@ enum GPE_SCOM_ADDRESS_PARAMETERS #define GPE_SCOM_ADDR_CME(addr, quad, cme) \ GPE_SCOM_ADDR(addr, CME_ADDR_BASE, quad, cme) -#define GPE_GETSCOM(addr, data) getscom(0, addr, &data); +#define GPE_GETSCOM(addr, data) PPE_LVD(addr, data); -#define GPE_PUTSCOM(addr, data) putscom(0, addr, data); +#define GPE_PUTSCOM(addr, data) putscom_norc(addr, data); #define GPE_GETSCOM_VAR(addr, cplt_base, cq_offset, ex_select, data) \ - getscom(0,GPE_SCOM_ADDR(addr, cplt_base, cq_offset, ex_select),&data); + PPE_LVD(GPE_SCOM_ADDR(addr, cplt_base, cq_offset, ex_select), data); #define GPE_PUTSCOM_VAR(addr, cplt_base, cq_offset, ex_select, data) \ - putscom(0,GPE_SCOM_ADDR(addr, cplt_base, cq_offset, ex_select), data); + putscom_norc(GPE_SCOM_ADDR(addr, cplt_base, cq_offset, ex_select), data); /// GPE data buffer in SRAM(mostly for IPC) #define GPE_BUFFER(declaration) \ diff --git a/import/chips/p9/common/pmlib/include/p9_stop_common.h b/import/chips/p9/common/pmlib/include/p9_stop_common.h index 3838193d..0206360a 100644 --- a/import/chips/p9/common/pmlib/include/p9_stop_common.h +++ b/import/chips/p9/common/pmlib/include/p9_stop_common.h @@ -99,7 +99,7 @@ enum P9_STOP_LEVELS }; /// STOP History Ctrl and Status constants -enum P9_STOP_HISTORY_CTRL_STATUS +enum P9_STOP_STATE_HISTORY_CTRL_STATUS { STOP_CORE_READY_RUN = 0, STOP_CACHE_READY_RUN = 0, @@ -115,6 +115,22 @@ enum P9_STOP_HISTORY_CTRL_STATUS STOP_ACT_DISABLE = 0 }; +// stop_gated : 0 +// stop_transition : 2:3 (00 complete, 01 cme completed, 10 entry, 11 exit) +// req_stop_level : 4:7 +// act_stop_level : 8:11 +// req_write_enable : 12 +// act_write_enable : 13 +enum P9_STOP_STATE_HISTORY_BIT_MASK +{ + SSH_STOP_GATED = BIT32(0), + SSH_TRANS_SGPE = BIT32(3), + SSH_TRANS_ENTRY = BIT32(2), + SSH_TRANS_EXIT = BITS32(2, 2), + SSH_REQ_ENABLE = BIT32(12), + SSH_ACT_ENABLE = BIT32(13) +}; + /// Homer Layout enum P9_HOMER_REGION_CONSTANTS { diff --git a/import/chips/p9/common/pmlib/include/ppehw_common.h b/import/chips/p9/common/pmlib/include/ppehw_common.h index 7b8c96df..0a813c65 100644 --- a/import/chips/p9/common/pmlib/include/ppehw_common.h +++ b/import/chips/p9/common/pmlib/include/ppehw_common.h @@ -66,6 +66,10 @@ typedef union #define SHIFT16(b) (15-(b)) #define SHIFT8(b) (7-(b)) +/// Macro used for second word operation +#define BIT64SH(bit64) BIT32((bit64-32)) +#define BITS64SH(bit64, size) BITS32((bit64-32), size) +#define SHIFT64SH(bit64) SHIFT32((bit64-32)) /// Mark and Tag diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h index 64f1bb64..36e5aa1f 100755 --- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h +++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h @@ -146,6 +146,11 @@ extern inline uint32_t getscom(const uint32_t i_chiplet, const uint32_t i_addres return _getscom(i_chiplet, i_address, o_data); } +extern inline void putscom_norc(const uint32_t i_address, uint64_t i_data) +{ + PPE_STVD(i_address, i_data); +} + #ifdef __cplusplus } // extern C #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c index d9bb15cc..c9d0a024 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c @@ -34,7 +34,7 @@ CmePstateRecord G_cme_pstate_record; // CME Stop Header and Structure #include "p9_cme_stop.h" -CmeStopRecord G_cme_stop_record __attribute__((section (".dump_ptrs"))) = {0}; +CmeStopRecord G_cme_stop_record __attribute__((section (".dump_ptrs"))) = {{0}, {0}, 0}; #if TEST_ONLY_BCE_IRR #include "p9_cme_copy_scan_ring.h" diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h index 20bc55a1..d515f877 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h @@ -39,7 +39,7 @@ /// @todo RTC 161182 #if NIMBUS_DD_LEVEL == 1 - #define HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX 0 + #define HW386841_DD1_DSL_STOP1_FIX 0 #define MASK_MSR_SEM6 #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index 00a668b6..b9b7988d 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -127,67 +127,6 @@ #define PERV_CPLT_STAT0 0x20000100 -/// Macro to evaluate g_eimr_override -#if SPWU_AUTO -#define EVAL_EIMR_OVERRIDE(mask_irqs) \ - g_eimr_override &= ~(BITS64(12, 6) | BITS64(20, 2)); \ - mask_irqs.words.lower = 0; \ - mask_irqs.words.upper = \ - ((((~G_cme_stop_record.core_enabled) | \ - G_cme_stop_record.core_running | \ - G_cme_stop_record.core_stopgpe | \ - G_cme_stop_record.core_blockwu) & CME_MASK_BC) << SHIFT32(13)) | \ - ((((~G_cme_stop_record.core_enabled) | \ - G_cme_stop_record.core_running) & CME_MASK_BC) << SHIFT32(15)) | \ - ((((~G_cme_stop_record.core_enabled) | \ - G_cme_stop_record.core_running) & CME_MASK_BC) << SHIFT32(17)) | \ - (((~(G_cme_stop_record.core_enabled & \ - G_cme_stop_record.core_running)) & CME_MASK_BC) << SHIFT32(21)); \ - g_eimr_override |= mask_irqs.value; -#else -#define EVAL_EIMR_OVERRIDE(mask_irqs) \ - g_eimr_override &= ~(BITS64(12, 6) | BITS64(20, 2)); \ - mask_irqs.words.lower = 0; \ - mask_irqs.words.upper = \ - ((((~G_cme_stop_record.core_enabled) | \ - G_cme_stop_record.core_running | \ - G_cme_stop_record.core_stopgpe | \ - G_cme_stop_record.core_blockwu) & CME_MASK_BC) << SHIFT32(13)) | \ - ((((~G_cme_stop_record.core_enabled) | \ - G_cme_stop_record.core_running) & CME_MASK_BC) << SHIFT32(17)) | \ - (((~(G_cme_stop_record.core_enabled & \ - G_cme_stop_record.core_running)) & CME_MASK_BC) << SHIFT32(21)); \ - g_eimr_override |= mask_irqs.value; -#endif - -/// Macro to update STOP History -#define CME_STOP_UPDATE_HISTORY(core,gated,trans,req_l,act_l,req_e,act_e) \ - hist.value = 0; \ - hist.fields.stop_gated = gated; \ - hist.fields.stop_transition = trans; \ - hist.fields.req_stop_level = req_l; \ - hist.fields.act_stop_level = act_l; \ - hist.fields.req_write_enable = req_e; \ - hist.fields.act_write_enable = act_e; \ - CME_PUTSCOM(PPM_SSHSRC, core, hist.value); - -/// Macro to update PSSCR.PLS -#define CME_STOP_UPDATE_PLS_SRR1(pls, srr1_t0, srr1_t1, srr1_t2, srr1_t3) \ - ((((uint64_t)pls) << SHIFT64(36)) | (((uint64_t)srr1_t0) << SHIFT64(39)) | \ - (((uint64_t)pls) << SHIFT64(44)) | (((uint64_t)srr1_t1) << SHIFT64(47)) | \ - (((uint64_t)pls) << SHIFT64(52)) | (((uint64_t)srr1_t2) << SHIFT64(55)) | \ - (((uint64_t)pls) << SHIFT64(60)) | ((uint64_t)srr1_t3) | \ - (BIT64(32) | BIT64(40) | BIT64(48) | BIT64(56))) - -#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX -#define CME_STOP_UPDATE_DLS(dls, srr1) \ - ((((uint64_t)dls.threads.t0) << SHIFT64(36)) | (((uint64_t)srr1[0]) << SHIFT64(39)) | \ - (((uint64_t)dls.threads.t1) << SHIFT64(44)) | (((uint64_t)srr1[1]) << SHIFT64(47)) | \ - (((uint64_t)dls.threads.t2) << SHIFT64(52)) | (((uint64_t)srr1[2]) << SHIFT64(55)) | \ - (((uint64_t)dls.threads.t3) << SHIFT64(60)) | ((uint64_t)srr1[3]) | \ - (BIT64(32) | BIT64(40) | BIT64(48) | BIT64(56))) -#endif - /// CME STOP Return Codes enum CME_STOP_RETURN_CODE { @@ -197,18 +136,18 @@ enum CME_STOP_RETURN_CODE /// CME STOP IRQs with shorter names enum CME_STOP_IRQ_SHORT_NAME { - IRQ_DB1_C0 = CMEHW_IRQ_DOORBELL1_C0, - IRQ_DB1_C1 = CMEHW_IRQ_DOORBELL1_C1, - IRQ_DB2_C0 = CMEHW_IRQ_DOORBELL2_C0, - IRQ_DB2_C1 = CMEHW_IRQ_DOORBELL2_C1, - IRQ_STOP_C0 = CMEHW_IRQ_PC_PM_STATE_ACTIVE_C0, - IRQ_STOP_C1 = CMEHW_IRQ_PC_PM_STATE_ACTIVE_C1, - IRQ_PC_C0 = CMEHW_IRQ_PC_INTR_PENDING_C0, - IRQ_PC_C1 = CMEHW_IRQ_PC_INTR_PENDING_C1, - IRQ_RWU_C0 = CMEHW_IRQ_REG_WAKEUP_C0, - IRQ_RWU_C1 = CMEHW_IRQ_REG_WAKEUP_C1, - IRQ_SWU_C0 = CMEHW_IRQ_SPECIAL_WAKEUP_C0, - IRQ_SWU_C1 = CMEHW_IRQ_SPECIAL_WAKEUP_C1 + IRQ_DB1_C0 = CMEHW_IRQ_DOORBELL1_C0, + IRQ_DB1_C1 = CMEHW_IRQ_DOORBELL1_C1, + IRQ_DB2_C0 = CMEHW_IRQ_DOORBELL2_C0, + IRQ_DB2_C1 = CMEHW_IRQ_DOORBELL2_C1, + IRQ_STOP_C0 = CMEHW_IRQ_PC_PM_STATE_ACTIVE_C0, + IRQ_STOP_C1 = CMEHW_IRQ_PC_PM_STATE_ACTIVE_C1, + IRQ_PC_C0 = CMEHW_IRQ_PC_INTR_PENDING_C0, + IRQ_PC_C1 = CMEHW_IRQ_PC_INTR_PENDING_C1, + IRQ_RWU_C0 = CMEHW_IRQ_REG_WAKEUP_C0, + IRQ_RWU_C1 = CMEHW_IRQ_REG_WAKEUP_C1, + IRQ_SWU_C0 = CMEHW_IRQ_SPECIAL_WAKEUP_C0, + IRQ_SWU_C1 = CMEHW_IRQ_SPECIAL_WAKEUP_C1 }; enum CME_IRQ_VECTORS @@ -233,6 +172,22 @@ enum CME_IRQ_VECTORS IRQ_VEC_STOP_C1 = BIT64(21) }; +enum CME_STOP_STATE_HISTORY_VECTORS +{ + SSH_EXIT_COMPLETE = 0, + SSH_EXIT_IN_SESSION = (SSH_STOP_GATED | SSH_TRANS_EXIT), + SSH_REQ_LEVEL_UPDATE = (SSH_TRANS_ENTRY | SSH_REQ_ENABLE), + SSH_ACT_LEVEL_UPDATE = (SSH_STOP_GATED | SSH_ACT_ENABLE), + SSH_ACT_LV1_COMPLETE = (SSH_STOP_GATED | BIT32(7) | BITS32(11, 3)), + SSH_ACT_LV2_COMPLETE = (SSH_ACT_LEVEL_UPDATE | BIT32(10)), + SSH_ACT_LV2_CONTINUE = (SSH_ACT_LV2_COMPLETE | SSH_TRANS_ENTRY), + SSH_ACT_LV3_COMPLETE = (SSH_ACT_LEVEL_UPDATE | BITS32(10, 2)), + SSH_ACT_LV3_CONTINUE = (SSH_ACT_LV3_COMPLETE | SSH_TRANS_ENTRY), + SSH_ACT_LV4_COMPLETE = (SSH_ACT_LEVEL_UPDATE | BIT32(9)), + SSH_ACT_LV4_CONTINUE = (SSH_ACT_LV4_COMPLETE | SSH_TRANS_ENTRY), + SSH_ACT_LV5_COMPLETE = (SSH_ACT_LEVEL_UPDATE | BIT32(9) | BIT32(11) | SSH_TRANS_SGPE) +}; + enum CME_STOP_FLAGS { FLAG_STOP_READY = BIT32(0), @@ -277,20 +232,6 @@ enum CME_STOP_SRR1 NO_STATE_LOSS = 1 }; -#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX -typedef union -{ - uint16_t vector; - struct - { - uint8_t t0 : 4; - uint8_t t1 : 4; - uint8_t t2 : 4; - uint8_t t3 : 4; - } threads; -} CoreThreadsInfo; -#endif - #if TEST_ONLY_BCE_IRR typedef struct { @@ -319,12 +260,12 @@ typedef struct { // requested stop levels are read from pm_state, // need to be a global state for stop8 detection - uint8_t req_level_c0; - uint8_t req_level_c1; + uint8_t req_level[MAX_CORES_PER_CME]; // actual stop levels are changed through entry, // need to be a global state for aborting entry - uint8_t act_level_c0; - uint8_t act_level_c1; + uint8_t act_level[MAX_CORES_PER_CME]; + // uint8_t above is processed by stb/lbz in asm, no additional shifting + // target mask of enabled cores, used to filter 2bit core select in scom address uint32_t core_enabled; // whether core is in running state, @@ -345,8 +286,10 @@ typedef struct /// CME STOP Entry and Exit Prototypes void p9_cme_stop_enter_thread(void*); void p9_cme_stop_exit_thread(void*); +void p9_cme_stop_eval_eimr_override(); int p9_cme_stop_entry(); int p9_cme_stop_exit(); +int p9_cme_stop_exit_catchup(); void p9_cme_stop_enter_handler(void*, PkIrqId); void p9_cme_stop_exit_handler(void*, PkIrqId); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index a8eee74f..aa6f67a2 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -61,13 +61,14 @@ p9_cme_stop_entry() uint32_t core_aborted = 0; uint32_t core_catchup = 0; uint32_t core_stop1 = 0; + uint32_t core_index = 0; + uint32_t core_mask = 0; uint32_t core_raw = 0; - uint32_t core; - uint32_t pm_states; - uint32_t lclr_data; - uint64_t scom_data; - ppm_sshsrc_t hist; - ppm_pig_t pig; + uint32_t core = 0; + uint32_t pm_states = 0; + uint32_t lclr_data = 0; + data64_t scom_data = {0}; + ppm_pig_t pig = {0}; //-------------------------------------------------------------------------- PK_TRACE_INF("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); @@ -107,7 +108,7 @@ p9_cme_stop_entry() // bit1 is Recoverable Error // bit2 is Special Attention if (((core & CME_MASK_C0) && (in32(CME_LCL_SISR) & BITS32(13, 2))) || - ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS32(29, 2)))) + ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS64SH(61, 2)))) { PK_TRACE_INF("WARNING: Attn/Recov Present, Abort Entry and Return"); return CME_STOP_SUCCESS; @@ -140,84 +141,53 @@ p9_cme_stop_entry() // !pm_active AND running : req_level = 0 by exit, // not changing req_level // !pm_active AND !running : req_level = Current req_level - if (core & CME_MASK_C0) - { - G_cme_stop_record.req_level_c0 = - (pm_states & BITS32(4, 4)) >> SHIFT32(7); - - if (G_cme_stop_record.req_level_c0 == STOP_LEVEL_1) - { - G_cme_stop_record.act_level_c0 = STOP_LEVEL_1; - core_stop1 |= CME_MASK_C0; - } - - if ((G_cme_stop_record.header_flags & MAP_11_TO_8) && - (G_cme_stop_record.req_level_c0 == STOP_LEVEL_11)) - { - - G_cme_stop_record.req_level_c0 = STOP_LEVEL_8; - } - - if ((G_cme_stop_record.header_flags & MAP_8_TO_5) && - (G_cme_stop_record.req_level_c0 == STOP_LEVEL_8)) - { - G_cme_stop_record.req_level_c0 = STOP_LEVEL_5; - } - if ((G_cme_stop_record.header_flags & MAP_5_TO_4) && - (G_cme_stop_record.req_level_c0 == STOP_LEVEL_5)) + for (core_mask = 2; core_mask; core_mask--) + { + if (core & core_mask) { - G_cme_stop_record.req_level_c0 = STOP_LEVEL_4; - } + core_index = core_mask & 1; + G_cme_stop_record.req_level[core_index] = + (pm_states & BITS64SH(36, 4)) >> SHIFT64SH(39); - if ((G_cme_stop_record.header_flags & MAP_4_TO_2) && - (G_cme_stop_record.req_level_c0 == STOP_LEVEL_4)) - { - G_cme_stop_record.req_level_c0 = STOP_LEVEL_2; - } - } - - if (core & CME_MASK_C1) - { - G_cme_stop_record.req_level_c1 = - (pm_states & BITS32(8, 4)) >> SHIFT32(11); + if (G_cme_stop_record.req_level[core_index] == STOP_LEVEL_1) + { + G_cme_stop_record.act_level[core_index] = STOP_LEVEL_1; + core_stop1 |= core_mask; + } - if (G_cme_stop_record.req_level_c1 == STOP_LEVEL_1) - { - G_cme_stop_record.act_level_c1 = STOP_LEVEL_1; - core_stop1 |= CME_MASK_C1; - } + if ((G_cme_stop_record.header_flags & MAP_11_TO_8) && + (G_cme_stop_record.req_level[core_index] == STOP_LEVEL_11)) + { - if ((G_cme_stop_record.header_flags & MAP_11_TO_8) && - (G_cme_stop_record.req_level_c1 == STOP_LEVEL_11)) - { - G_cme_stop_record.req_level_c1 = STOP_LEVEL_8; - } + G_cme_stop_record.req_level[core_index] = STOP_LEVEL_8; + } - if ((G_cme_stop_record.header_flags & MAP_8_TO_5) && - (G_cme_stop_record.req_level_c1 == STOP_LEVEL_8)) - { - G_cme_stop_record.req_level_c1 = STOP_LEVEL_5; - } + if ((G_cme_stop_record.header_flags & MAP_8_TO_5) && + (G_cme_stop_record.req_level[core_index] == STOP_LEVEL_8)) + { + G_cme_stop_record.req_level[core_index] = STOP_LEVEL_5; + } - if ((G_cme_stop_record.header_flags & MAP_5_TO_4) && - (G_cme_stop_record.req_level_c1 == STOP_LEVEL_5)) - { - G_cme_stop_record.req_level_c1 = STOP_LEVEL_4; - } + if ((G_cme_stop_record.header_flags & MAP_5_TO_4) && + (G_cme_stop_record.req_level[core_index] == STOP_LEVEL_5)) + { + G_cme_stop_record.req_level[core_index] = STOP_LEVEL_4; + } - if ((G_cme_stop_record.header_flags & MAP_4_TO_2) && - (G_cme_stop_record.req_level_c1 == STOP_LEVEL_4)) - { - G_cme_stop_record.req_level_c1 = STOP_LEVEL_2; + if ((G_cme_stop_record.header_flags & MAP_4_TO_2) && + (G_cme_stop_record.req_level[core_index] == STOP_LEVEL_4)) + { + G_cme_stop_record.req_level[core_index] = STOP_LEVEL_2; + } } } PK_TRACE_DBG("Check: Stop Levels Request[%d %d] Actual[%d, %d]", - G_cme_stop_record.req_level_c0, - G_cme_stop_record.req_level_c1, - G_cme_stop_record.act_level_c0, - G_cme_stop_record.act_level_c1); + G_cme_stop_record.req_level[0], + G_cme_stop_record.req_level[1], + G_cme_stop_record.act_level[0], + G_cme_stop_record.act_level[1]); // Mark core as to be stopped G_cme_stop_record.core_running &= ~core; @@ -226,7 +196,7 @@ p9_cme_stop_entry() { PK_TRACE_DBG("Check: core[%d] core_stop1[%d]", core, core_stop1); -#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX +#if HW386841_DD1_DSL_STOP1_FIX //---------------------------------------------------------------------- PK_TRACE_INF("+++++ +++++ STOP LEVEL 1 ENTRY +++++ +++++"); @@ -237,13 +207,9 @@ p9_cme_stop_entry() out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1)); PK_TRACE("Update STOP history: in core stop level 1"); - CME_STOP_UPDATE_HISTORY(core_stop1, - STOP_CORE_IS_GATED, - STOP_TRANS_COMPLETE, - STOP_LEVEL_1, - STOP_LEVEL_1, - STOP_REQ_ENABLE, - STOP_ACT_ENABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ACT_LV1_COMPLETE; + CME_PUTSCOM(PPM_SSHSRC, core_stop1, scom_data.value); core = core & ~core_stop1; @@ -275,46 +241,38 @@ p9_cme_stop_entry() out32(CME_LCL_SICR_CLR, core << SHIFT32(1)); // set target_level from pm_state for both cores or just one core - target_level = (core == CME_MASK_C0) ? G_cme_stop_record.req_level_c0 : - G_cme_stop_record.req_level_c1; + target_level = (core == CME_MASK_C0) ? G_cme_stop_record.req_level[0] : + G_cme_stop_record.req_level[1]; // If both cores are going into STOP but targeting different levels, if ((core == CME_MASK_BC) && - (G_cme_stop_record.req_level_c0 != G_cme_stop_record.req_level_c1)) + (G_cme_stop_record.req_level[0] != G_cme_stop_record.req_level[1])) { // set target_level to the lighter level targeted by one core // set deeper_level to the deeper level targeted by deeper core - deeper_level = G_cme_stop_record.req_level_c0; + deeper_level = G_cme_stop_record.req_level[0]; deeper_core = CME_MASK_C0; - if (G_cme_stop_record.req_level_c0 < G_cme_stop_record.req_level_c1) + if (G_cme_stop_record.req_level[0] < G_cme_stop_record.req_level[1]) { - target_level = G_cme_stop_record.req_level_c0; - deeper_level = G_cme_stop_record.req_level_c1; + target_level = G_cme_stop_record.req_level[0]; + deeper_level = G_cme_stop_record.req_level[1]; deeper_core = CME_MASK_C1; } } PK_TRACE("Update STOP history: in transition of entry"); // Set req_level_level to target_level of either both or just one core - CME_STOP_UPDATE_HISTORY(core, - STOP_CORE_READY_RUN, - STOP_TRANS_ENTRY, - target_level, - STOP_LEVEL_0, - STOP_REQ_ENABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | (target_level << SHIFT32(7))); + CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // Set req_level_level to deeper_level for deeper core if (deeper_core) { - CME_STOP_UPDATE_HISTORY(deeper_core, - STOP_CORE_READY_RUN, - STOP_TRANS_ENTRY, - deeper_level, - STOP_LEVEL_0, - STOP_REQ_ENABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | (deeper_level << SHIFT32(7))); + CME_PUTSCOM(PPM_SSHSRC, deeper_core, scom_data.value); } PK_TRACE_DBG("Check: core[%d] target_lv[%d] deeper_lv[%d] deeper_core[%d]", @@ -373,14 +331,14 @@ p9_cme_stop_entry() do { - CME_GETSCOM(C_CPLT_STAT0, core, CME_SCOM_AND, scom_data); + CME_GETSCOM(C_CPLT_STAT0, core, CME_SCOM_AND, scom_data.value); } - while((~scom_data) & BIT64(8)); + while(!(scom_data.words.upper & BIT32(8))); PK_TRACE("Check core clock is stopped via CLOCK_STAT_SL[4-13]"); - CME_GETSCOM(C_CLOCK_STAT_SL, core, CME_SCOM_AND, scom_data); + CME_GETSCOM(C_CLOCK_STAT_SL, core, CME_SCOM_AND, scom_data.value); - if (((~scom_data) & CLK_REGION_ALL_BUT_PLL) != 0) + if (((~scom_data.value) & CLK_REGION_ALL_BUT_PLL) != 0) { PK_TRACE_INF("ERROR: Core Clock Stop Failed. HALT CME!"); pk_halt(); @@ -402,9 +360,9 @@ p9_cme_stop_entry() do { - CME_GETSCOM(CPPM_CACSR, core, CME_SCOM_OR, scom_data); + CME_GETSCOM(CPPM_CACSR, core, CME_SCOM_OR, scom_data.value); } - while(scom_data & BIT64(13)); + while(scom_data.words.upper & BIT32(13)); PK_TRACE("Switch glsmux to refclk to save clock grid power via CGCR[3]"); CME_PUTSCOM(C_PPM_CGCR, core, 0); @@ -429,16 +387,16 @@ p9_cme_stop_entry() if (core & CME_MASK_C0) { - scom_data = in64(CME_LCL_PECESR0); - CME_PUTSCOM(CPPM_PECES, core, scom_data); - G_cme_stop_record.act_level_c0 = STOP_LEVEL_2; + scom_data.value = in64(CME_LCL_PECESR0); + CME_PUTSCOM(CPPM_PECES, CME_MASK_C0, scom_data.value); + G_cme_stop_record.act_level[0] = STOP_LEVEL_2; } if (core & CME_MASK_C1) { - scom_data = in64(CME_LCL_PECESR1); - CME_PUTSCOM(CPPM_PECES, core, scom_data); - G_cme_stop_record.act_level_c1 = STOP_LEVEL_2; + scom_data.value = in64(CME_LCL_PECESR1); + CME_PUTSCOM(CPPM_PECES, CME_MASK_C1, scom_data.value); + G_cme_stop_record.act_level[1] = STOP_LEVEL_2; } PK_TRACE_INF("SE2.D: Clock Sync Dropped"); @@ -453,26 +411,19 @@ p9_cme_stop_entry() target_level == STOP_LEVEL_2 ? STOP_TRANS_COMPLETE : STOP_TRANS_ENTRY; - CME_STOP_UPDATE_HISTORY(core, - STOP_CORE_IS_GATED, - entry_ongoing, - target_level, - STOP_LEVEL_2, - STOP_REQ_DISABLE, - STOP_ACT_ENABLE); + scom_data.words.lower = 0; + scom_data.words.upper = (SSH_ACT_LV2_COMPLETE | (entry_ongoing << SHIFT32(3))); + CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // If both cores targeting different levels // deeper core should have at least deeper stop level than 2 // but only need to modify deeper core history if another one was done if (deeper_core && !entry_ongoing) { - CME_STOP_UPDATE_HISTORY(deeper_core, - STOP_CORE_IS_GATED, - STOP_TRANS_ENTRY, - deeper_level, - STOP_LEVEL_2, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ACT_LV2_CONTINUE; + CME_PUTSCOM(PPM_SSHSRC, deeper_core, scom_data.value); + // from now on, proceed with only deeper core core = deeper_core; target_level = deeper_level; @@ -620,12 +571,12 @@ p9_cme_stop_entry() // Drop to Vmin if(core & CME_MASK_C0) { - G_cme_stop_record.act_level_c0 = STOP_LEVEL_3; + G_cme_stop_record.act_level[0] = STOP_LEVEL_3; } if(core & CME_MASK_C1) { - G_cme_stop_record.act_level_c1 = STOP_LEVEL_3; + G_cme_stop_record.act_level[1] = STOP_LEVEL_3; } //=========================== @@ -634,14 +585,9 @@ p9_cme_stop_entry() PK_TRACE("SE3.c"); // Update Stop History: In Core Stop Level 3 - - CME_STOP_UPDATE_HISTORY(core, - STOP_CORE_IS_GATED, - STOP_TRANS_COMPLETE, - target_level, - STOP_LEVEL_3, - STOP_REQ_DISABLE, - STOP_ACT_ENABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ACT_LV3_COMPLETE; + CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); */ // If both cores targeting different levels // deeper core should have at least deeper stop level than 3 @@ -649,13 +595,9 @@ p9_cme_stop_entry() if (deeper_core) { /* - CME_STOP_UPDATE_HISTORY(deeper_core, - STOP_CORE_IS_GATED, - STOP_TRANS_ENTRY, - deeper_level, - STOP_LEVEL_2, - STOP_REQ_DISABLE, - STOP_ACT_ENABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ACT_LV3_CONTINUE; + CME_PUTSCOM(PPM_SSHSRC, deeper_core, scom_data.value); */ // from now on, proceed with only deeper core core = deeper_core; @@ -702,7 +644,7 @@ p9_cme_stop_entry() // bit2 is Special Attention // bit3 is Core Checkstop if (((core & CME_MASK_C0) && (in32(CME_LCL_SISR) & BITS32(12, 4))) || - ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS32(28, 4)))) + ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS64SH(60, 4)))) { PK_TRACE_INF("WARNING: Xstop/Attn/Recov Present, Skip Core Power Off"); } @@ -721,9 +663,9 @@ p9_cme_stop_entry() do { - CME_GETSCOM(PPM_PFSNS, core, CME_SCOM_AND, scom_data); + CME_GETSCOM(PPM_PFSNS, core, CME_SCOM_AND, scom_data.value); } - while(!(scom_data & BIT64(1))); + while(!(scom_data.words.upper & BIT32(1))); PK_TRACE("Turn off force voff via PFCS[0-1]"); // vdd_pfet_force_state = 00 (Nop) @@ -736,12 +678,12 @@ p9_cme_stop_entry() if (core & CME_MASK_C0) { - G_cme_stop_record.act_level_c0 = STOP_LEVEL_4; + G_cme_stop_record.act_level[0] = STOP_LEVEL_4; } if (core & CME_MASK_C1) { - G_cme_stop_record.act_level_c1 = STOP_LEVEL_4; + G_cme_stop_record.act_level[1] = STOP_LEVEL_4; } //=========================== @@ -753,26 +695,20 @@ p9_cme_stop_entry() entry_ongoing = target_level == STOP_LEVEL_4 ? STOP_TRANS_COMPLETE : STOP_TRANS_ENTRY; - CME_STOP_UPDATE_HISTORY(core, - STOP_CORE_IS_GATED, - entry_ongoing, - target_level, - STOP_LEVEL_4, - STOP_REQ_DISABLE, - STOP_ACT_ENABLE); + + scom_data.words.lower = 0; + scom_data.words.upper = (SSH_ACT_LV4_COMPLETE | (entry_ongoing << SHIFT32(3))); + CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // If both cores targeting different levels // deeper core should have at least deeper stop level than 4 // only need to modify deeper core history if another one was done if (deeper_core && !entry_ongoing) { - CME_STOP_UPDATE_HISTORY(deeper_core, - STOP_CORE_IS_GATED, - STOP_TRANS_ENTRY, - deeper_level, - STOP_LEVEL_4, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ACT_LV4_CONTINUE; + CME_PUTSCOM(PPM_SSHSRC, deeper_core, scom_data.value); + // from now on, proceed with only deeper core core = deeper_core; target_level = deeper_level; @@ -833,8 +769,8 @@ p9_cme_stop_entry() PK_TRACE_INF("+++++ +++++ STOP LEVEL 5-7 ENTRY +++++ +++++"); //---------------------------------------------------------------------- - if ((G_cme_stop_record.req_level_c0 >= STOP_LEVEL_8) && - (G_cme_stop_record.req_level_c1 >= STOP_LEVEL_8)) + if ((G_cme_stop_record.req_level[0] >= STOP_LEVEL_8) && + (G_cme_stop_record.req_level[1] >= STOP_LEVEL_8)) { //================================ @@ -911,52 +847,34 @@ p9_cme_stop_entry() //============================= PK_TRACE("Update STOP history: in core stop level 5"); - CME_STOP_UPDATE_HISTORY(core, - STOP_CORE_IS_GATED, - STOP_TRANS_CORE_PORTION, - target_level, - STOP_LEVEL_5, - STOP_REQ_DISABLE, - STOP_ACT_ENABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ACT_LV5_COMPLETE; + CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); PK_TRACE("Send PCB interrupt per core via PIG, select irq type via CPMMR[10]"); - if (core & CME_MASK_C0) + for (core_mask = 2; core_mask; core_mask--) { - if (G_cme_stop_record.req_level_c0 < STOP_LEVEL_11) - { - CME_PUTSCOM(CPPM_CPMMR_OR, CME_MASK_C0, BIT64(10)); - pig.fields.req_intr_type = PIG_TYPE3; - } - else + if (core & core_mask) { - CME_PUTSCOM(CPPM_CPMMR_CLR, CME_MASK_C0, BIT64(10)); - pig.fields.req_intr_type = PIG_TYPE2; - } + core_index = core_mask & 1; - pig.fields.req_intr_payload = G_cme_stop_record.req_level_c0; - CME_PUTSCOM(PPM_PIG, CME_MASK_C0, pig.value); - G_cme_stop_record.core_stopgpe |= core; - G_cme_stop_record.act_level_c0 = STOP_LEVEL_5; - } + if (G_cme_stop_record.req_level[core_index] < STOP_LEVEL_11) + { + CME_PUTSCOM(CPPM_CPMMR_OR, core_mask, BIT64(10)); + pig.fields.req_intr_type = PIG_TYPE3; + } + else + { + CME_PUTSCOM(CPPM_CPMMR_CLR, core_mask, BIT64(10)); + pig.fields.req_intr_type = PIG_TYPE2; + } - if (core & CME_MASK_C1) - { - if (G_cme_stop_record.req_level_c1 < STOP_LEVEL_11) - { - CME_PUTSCOM(CPPM_CPMMR_OR, CME_MASK_C1, BIT64(10)); - pig.fields.req_intr_type = PIG_TYPE3; + pig.fields.req_intr_payload = G_cme_stop_record.req_level[core_index]; + CME_PUTSCOM(PPM_PIG, core_mask, pig.value); + G_cme_stop_record.core_stopgpe |= core; + G_cme_stop_record.act_level[core_index] = STOP_LEVEL_5; } - else - { - CME_PUTSCOM(CPPM_CPMMR_CLR, CME_MASK_C1, BIT64(10)); - pig.fields.req_intr_type = PIG_TYPE2; - } - - pig.fields.req_intr_payload = G_cme_stop_record.req_level_c1; - CME_PUTSCOM(PPM_PIG, CME_MASK_C1, pig.value); - G_cme_stop_record.core_stopgpe |= core; - G_cme_stop_record.act_level_c1 = STOP_LEVEL_5; } PK_TRACE("Switch PPM wakeup to STOP-GPE via CPMMR[13]"); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index e8673dcc..2b4a549c 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -30,9 +30,89 @@ extern CmeStopRecord G_cme_stop_record; -#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX +#if HW386841_DD1_DSL_STOP1_FIX -CoreThreadsInfo G_dsl[MAX_CORES_PER_CME] = {{0}, {0}}; +uint8_t G_dsl[MAX_CORES_PER_CME][MAX_THREADS_PER_CORE] = {{0, 0, 0, 0}, {0, 0, 0, 0}}; + +#endif + +#if !SKIP_EXIT_CATCHUP + +int +p9_cme_stop_exit_catchup(uint32_t* core, uint32_t* deeper_core, + int* d2u4_flag, uint32_t* spwu_stop) +{ + int rc = 0; + uint8_t catchup_level = 0; + uint32_t core_catchup = 0; + uint32_t wakeup = 0; + data64_t scom_data = {0}; + + wakeup = (in32(CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; + core_catchup = (~(*core)) & + ((wakeup >> 4) | (wakeup >> 2) | wakeup); + core_catchup = core_catchup & G_cme_stop_record.core_enabled & + (~G_cme_stop_record.core_running); + + if (core_catchup & CME_MASK_C0) + { + CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data.value); + + if (scom_data.words.upper & BIT32(13)) + { + core_catchup = core_catchup - CME_MASK_C0; + } + } + + if (core_catchup & CME_MASK_C1) + { + CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data.value); + + if (scom_data.words.upper & BIT32(13)) + { + core_catchup = core_catchup - CME_MASK_C1; + } + } + + if (core_catchup) + { + // pcbmux grant + out32(CME_LCL_SICR_OR, (core_catchup << SHIFT32(11))); + // chtm purge done + out32(CME_LCL_EISR_CLR, (core_catchup << SHIFT32(25))); + + scom_data.words.lower = 0; + scom_data.words.upper = SSH_EXIT_IN_SESSION; + CME_PUTSCOM(PPM_SSHSRC, core_catchup, scom_data.value); + + catchup_level = (core_catchup & CME_MASK_C0) ? + G_cme_stop_record.act_level[0] : + G_cme_stop_record.act_level[1] ; + + *spwu_stop |= (core_catchup) & (wakeup >> 2); + + PK_TRACE_DBG("Catch: core[%d] running[%d] \ + core_catchup[%d] catchup_level[%d]", + *core, G_cme_stop_record.core_running, + core_catchup, catchup_level); + + while((core_catchup & (in32(CME_LCL_SISR) >> + SHIFT32(11))) != core_catchup); + + if (catchup_level < STOP_LEVEL_4) + { + *deeper_core = *core; + *d2u4_flag = 1; + } + else + { + *core = core_catchup; + rc = 1; + } + } + + return rc; +} #endif @@ -42,32 +122,28 @@ p9_cme_stop_exit() int d2u4_flag = 0; int catchup_ongoing_a = 0; int catchup_ongoing_b = 0; - uint8_t target_level; + uint8_t target_level = 0; uint8_t deeper_level = 0; uint32_t deeper_core = 0; - uint32_t wakeup; - uint32_t core; + uint32_t wakeup = 0; + uint32_t core = 0; + uint32_t core_mask = 0; + uint32_t act_stop_level = 0; + data64_t scom_data = {0}; #if !SPWU_AUTO - uint32_t spwu_stop; - uint32_t spwu_wake; -#endif -#if !STOP_PRIME -#if !SKIP_EXIT_CATCHUP - uint8_t catchup_level; - uint32_t core_catchup; -#endif + uint32_t spwu_stop = 0; + uint32_t spwu_wake = 0; #endif -#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX - uint8_t dsl; - uint8_t thread; - uint8_t G_srr1[MAX_CORES_PER_CME][MAX_THREADS_PER_CORE] = {{0, 0, 0, 0}, {0, 0, 0, 0}}; - uint32_t temp0 = 0; - uint32_t temp1 = 0; +#if HW386841_DD1_DSL_STOP1_FIX + uint8_t srr1[MAX_THREADS_PER_CORE] = {0, 0, 0, 0}; + uint32_t pscrs = 0; + uint32_t bitloc = 0; + uint32_t thread = 0; + uint32_t temp_dsl = 0; + uint32_t temp_srr1 = 0; + uint32_t core_index = 0; uint32_t core_stop1 = 0; - cme_scom_pscrs00_t pscrs; #endif - ppm_sshsrc_t hist; - data64_t scom_data; //-------------------------------------------------------------------------- PK_TRACE_INF("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++"); @@ -78,23 +154,16 @@ p9_cme_stop_exit() core = ((wakeup >> 4) | (wakeup >> 2) | wakeup) & CME_MASK_BC; // ignore wakeup when it suppose to be handled by sgpe - if (core & CME_MASK_C0) + for (core_mask = 2; core_mask; core_mask--) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data.value); - - if (scom_data.words.upper & BIT32(13)) + if (core & core_mask) { - core = core - CME_MASK_C0; - } - } - - if (core & CME_MASK_C1) - { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data.value); + CME_GETSCOM(CPPM_CPMMR, core_mask, CME_SCOM_AND, scom_data.value); - if (scom_data.words.upper & BIT32(13)) - { - core = core - CME_MASK_C1; + if (scom_data.words.upper & BIT32(13)) + { + core = core - core_mask; + } } } @@ -104,8 +173,8 @@ p9_cme_stop_exit() PK_TRACE_DBG("Check: Core Select[%d] Wakeup[%x] Actual Stop Levels[%d %d]", core, wakeup, - G_cme_stop_record.act_level_c0, - G_cme_stop_record.act_level_c1); + G_cme_stop_record.act_level[0], + G_cme_stop_record.act_level[1]); @@ -149,17 +218,16 @@ p9_cme_stop_exit() MARK_TAG(BEGINSCOPE_STOP_EXIT, core) //================================== -#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX +#if HW386841_DD1_DSL_STOP1_FIX // figure out who needs stop1 exit - if ((core & CME_MASK_C0) && G_cme_stop_record.act_level_c0 == STOP_LEVEL_1) + for (core_mask = 2; core_mask; core_mask--) { - core_stop1 |= CME_MASK_C0; - } - - if ((core & CME_MASK_C1) && G_cme_stop_record.act_level_c1 == STOP_LEVEL_1) - { - core_stop1 |= CME_MASK_C1; + if((core & core_mask) && + G_cme_stop_record.act_level[core_mask & 1] == STOP_LEVEL_1) + { + core_stop1 |= core_mask; + } } PK_TRACE_DBG("SX0.B: Core[%d] Requested Stop1 Exit", core_stop1); @@ -178,23 +246,23 @@ p9_cme_stop_exit() // set target_level to STOP level for c0 // unless c1(also or only) wants to wakeup target_level = deeper_level = - (core == CME_MASK_C0) ? G_cme_stop_record.act_level_c0 : - G_cme_stop_record.act_level_c1; + (core == CME_MASK_C0) ? G_cme_stop_record.act_level[0] : + G_cme_stop_record.act_level[1]; // If both cores want to wakeup but are in different STOP levels, // set deeper_level to the deeper level targeted by deeper core if ((core == CME_MASK_BC) && - (G_cme_stop_record.act_level_c0 != G_cme_stop_record.act_level_c1)) + (G_cme_stop_record.act_level[0] != G_cme_stop_record.act_level[1])) { // Assume C0 is deeper, target_level is already set to C1 - deeper_level = G_cme_stop_record.act_level_c0; + deeper_level = G_cme_stop_record.act_level[0]; deeper_core = CME_MASK_C0; // Otherwise correct assumption on which one is in lighter level - if (G_cme_stop_record.act_level_c0 < G_cme_stop_record.act_level_c1) + if (G_cme_stop_record.act_level[0] < G_cme_stop_record.act_level[1]) { - target_level = G_cme_stop_record.act_level_c0; - deeper_level = G_cme_stop_record.act_level_c1; + target_level = G_cme_stop_record.act_level[0]; + deeper_level = G_cme_stop_record.act_level[1]; deeper_core = CME_MASK_C1; } } @@ -213,13 +281,9 @@ p9_cme_stop_exit() out32(CME_LCL_EISR_CLR, (core << SHIFT32(25))); PK_TRACE("Update STOP history: in transition of exit"); - CME_STOP_UPDATE_HISTORY(core, - STOP_CORE_IS_GATED, - STOP_TRANS_EXIT, - STOP_LEVEL_0, - STOP_LEVEL_0, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_EXIT_IN_SESSION; + CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); PK_TRACE("Check for PCB mux granted via SISR[10/11]"); @@ -279,76 +343,13 @@ p9_cme_stop_exit() } else if ((core != CME_MASK_BC) && (!deeper_core) && (!catchup_ongoing_b)) { - wakeup = (in32(CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; - core_catchup = (~core) & - ((wakeup >> 4) | (wakeup >> 2) | wakeup); - core_catchup = core_catchup & G_cme_stop_record.core_enabled & - (~G_cme_stop_record.core_running); - - if (core_catchup & CME_MASK_C0) + if (p9_cme_stop_exit_catchup(&core, &deeper_core, &d2u4_flag, &spwu_stop)) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data.value); - - if (scom_data.words.upper & BIT32(13)) - { - core_catchup = core_catchup - CME_MASK_C0; - } - } - - if (core_catchup & CME_MASK_C1) - { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data.value); - - if (scom_data.words.upper & BIT32(13)) - { - core_catchup = core_catchup - CME_MASK_C1; - } - } - - if (core_catchup) - { - //================================== - MARK_TAG(SX_CATCHUP_B, core_catchup) - //================================== - - // pcbmux grant - out32(CME_LCL_SICR_OR, (core_catchup << SHIFT32(11))); - // chtm purge done - out32(CME_LCL_EISR_CLR, (core_catchup << SHIFT32(25))); - - CME_STOP_UPDATE_HISTORY(core_catchup, - STOP_CORE_IS_GATED, - STOP_TRANS_EXIT, - STOP_LEVEL_0, - STOP_LEVEL_0, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); - - catchup_level = (core_catchup & CME_MASK_C0) ? - G_cme_stop_record.act_level_c0 : - G_cme_stop_record.act_level_c1 ; - - spwu_stop |= (core_catchup) & (wakeup >> 2); - - PK_TRACE_DBG("Catch: core[%d] running[%d] \ - core_catchup[%d] catchup_level[%d]", - core, G_cme_stop_record.core_running, - core_catchup, catchup_level); - - while((core_catchup & (in32(CME_LCL_SISR) >> - SHIFT32(11))) != core_catchup); - - if (catchup_level < STOP_LEVEL_4) - { - deeper_core = core; - d2u4_flag = 1; - } - else - { - core = core_catchup; - catchup_ongoing_a = 1; - continue; - } + //========================== + MARK_TAG(SX_CATCHUP_A, core) + //========================== + catchup_ongoing_a = 1; + continue; } } @@ -384,76 +385,13 @@ p9_cme_stop_exit() } else if ((core != CME_MASK_BC) && (!deeper_core)) { - wakeup = (in32(CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; - core_catchup = (~core) & - ((wakeup >> 4) | (wakeup >> 2) | wakeup); - core_catchup = core_catchup & G_cme_stop_record.core_enabled & - (~G_cme_stop_record.core_running); - - if (core_catchup & CME_MASK_C0) - { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data.value); - - if (scom_data.words.upper & BIT32(13)) - { - core_catchup = core_catchup - CME_MASK_C0; - } - } - - if (core_catchup & CME_MASK_C1) + if (p9_cme_stop_exit_catchup(&core, &deeper_core, &d2u4_flag, &spwu_stop)) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data.value); - - if (scom_data.words.upper & BIT32(13)) - { - core_catchup = core_catchup - CME_MASK_C1; - } - } - - if (core_catchup) - { - //================================== - MARK_TAG(SX_CATCHUP_B, core_catchup) - //================================== - - // pcbmux grant - out32(CME_LCL_SICR_OR, (core_catchup << SHIFT32(11))); - // chtm purge done - out32(CME_LCL_EISR_CLR, (core_catchup << SHIFT32(25))); - - CME_STOP_UPDATE_HISTORY(core_catchup, - STOP_CORE_IS_GATED, - STOP_TRANS_EXIT, - STOP_LEVEL_0, - STOP_LEVEL_0, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); - - catchup_level = (core_catchup & CME_MASK_C0) ? - G_cme_stop_record.act_level_c0 : - G_cme_stop_record.act_level_c1 ; - - spwu_stop |= (core_catchup) & (wakeup >> 2); - - PK_TRACE_DBG("Catch: core[%d] running[%d] \ - core_catchup[%d] catchup_level[%d]", - core, G_cme_stop_record.core_running, - core_catchup, catchup_level); - - while((core_catchup & (in32(CME_LCL_SISR) >> - SHIFT32(11))) != core_catchup); - - if (catchup_level < STOP_LEVEL_4) - { - deeper_core = core; - d2u4_flag = 1; - } - else - { - core = core_catchup; - catchup_ongoing_b = 1; - continue; - } + //========================== + MARK_TAG(SX_CATCHUP_B, core) + //========================== + catchup_ongoing_b = 1; + continue; } } @@ -638,42 +576,25 @@ p9_cme_stop_exit() PK_TRACE("Set SPR mode to LT0-7 via SPR_MODE[20-27]"); CME_PUTSCOM(SPR_MODE, core, BITS64(20, 8)); - if (core & CME_MASK_C0) - { - PK_TRACE("Set SPRC to scratch0 for core0 via SCOM_SPRC"); - CME_PUTSCOM(SCOM_SPRC, CME_MASK_C0, 0); - - PK_TRACE("Load SCRACTH0 with HOMER+2MB"); - -#if EPM_P9_TUNING - - CME_PUTSCOM(SCRACTH0, CME_MASK_C0, 0x200000); - -#else - - CME_PUTSCOM(SCRACTH0, CME_MASK_C0, scom_data.value); - -#endif - - } - - if (core & CME_MASK_C1) + for (core_mask = 2; core_mask; core_mask--) { - PK_TRACE("Set SPRC to scratch1 for core1 via SCOM_SPRC"); - CME_PUTSCOM(SCOM_SPRC, CME_MASK_C1, BIT64(60)); + if (core & core_mask) + { + PK_TRACE_DBG("Set SPRC to scratch for core[%d] via SCOM_SPRC", core_mask); + CME_PUTSCOM(SCOM_SPRC, core_mask, ((core_mask & 1) ? BIT64(60) : 0)); - PK_TRACE("Load SCRACTH1 with HOMER+2MB"); + PK_TRACE_DBG("Load SCRACTH with HOMER+2MB for core[%d]", core_mask); #if EPM_P9_TUNING - CME_PUTSCOM(SCRACTH1, CME_MASK_C1, 0x200000); + CME_PUTSCOM((SCRACTH0 + (core_mask & 1)), core_mask, 0x200000); #else - CME_PUTSCOM(SCRACTH1, CME_MASK_C1, scom_data.value); + CME_PUTSCOM((SCRACTH0 + (core_mask & 1)), core_mask, scom_data.value); #endif - + } } PK_TRACE("RAM: mfspr sprd , gpr0 via RAM_CTRL"); @@ -739,7 +660,7 @@ p9_cme_stop_exit() while((~(in32(CME_LCL_EINR))) & (core << SHIFT32(21))) { - if (in32_sh(CME_LCL_SISR) & (core << SHIFT32(1))) + if (in32_sh(CME_LCL_SISR) & (core << SHIFT64SH(33))) { PK_TRACE("ERROR: Core Special Attention Detected. HALT CME!"); pk_halt(); @@ -773,7 +694,7 @@ p9_cme_stop_exit() PK_TRACE_INF("+++++ +++++ END OF STOP EXIT +++++ +++++"); //-------------------------------------------------------------------------- -#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX +#if HW386841_DD1_DSL_STOP1_FIX STOP1_EXIT: @@ -781,161 +702,127 @@ STOP1_EXIT: PK_TRACE_INF("SX0.D: Restore PSSCR.PLS+SRR1 back to actual level"); - if (core & CME_MASK_C0) + for (core_mask = 2; core_mask; core_mask--) { - CME_GETSCOM(PPM_SSHSRC, CME_MASK_C0, CME_SCOM_AND, hist.value); - - for (thread = 0; thread < MAX_THREADS_PER_CORE; thread++) + if (core & core_mask) { - pscrs.value = in32((CME_LCL_PSCRS00 + (thread << 5))); - dsl = (G_dsl[0].vector & BITS16((thread << 2), 4)) >> - SHIFT16((thread << 2) + 3); - PK_TRACE("C0: PSCRS1%d %x, old dsl %d", thread, pscrs.value, dsl); - - temp0 = pscrs.fields.esl_a_n ? pscrs.fields.rl_a_n : 0 ; - temp1 = hist.fields.act_stop_level; + PK_TRACE_DBG("Set PLS+SRR1 for Core[%d]", core_mask); + CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value); - dsl = MIN(temp0, MAX(temp1, dsl)); - G_dsl[0].vector = ((G_dsl[0].vector & ~BITS16((thread << 2), 4)) | - (dsl << SHIFT16((thread << 2) + 3))); - PK_TRACE("C0: new dsl %d", dsl); + act_stop_level = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11); + scom_data.words.upper = (BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56)); + core_index = core_mask & 1; - if (dsl >= STOP_LEVEL_8) + for (thread = 0, bitloc = 36; + thread < MAX_THREADS_PER_CORE; + thread++, bitloc += 8) { - G_srr1[0][thread] = MOST_STATE_LOSS; - } - else if (dsl >= STOP_LEVEL_4) - { - G_srr1[0][thread] = SOME_STATE_LOSS_BUT_NOT_TIMEBASE; - } - else - G_srr1[0][thread] = - pscrs.fields.esl_a_n ? SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS; - } + // address are 0x20 apart between threads and 0x80 apart between cores + pscrs = in32((CME_LCL_PSCRS00 + (core_index << 7) + (thread << 5))); - CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C0, CME_STOP_UPDATE_DLS(G_dsl[0], G_srr1[0])); - PK_TRACE("C0 DLS : %x %x %x %x", - G_dsl[0].threads.t0, G_dsl[0].threads.t1, - G_dsl[0].threads.t2, G_dsl[0].threads.t3); - PK_TRACE("C0 SRR1 : %x %x %x %x", - G_srr1[0][0], G_srr1[0][1], G_srr1[0][2], G_srr1[0][3]); - } + PK_TRACE_DBG("Old dsl%d of Core%d Thread%d, current PSCRS%x", + G_dsl[core_index][thread], core_index, thread, pscrs); - if (core & CME_MASK_C1) - { - CME_GETSCOM(PPM_SSHSRC, CME_MASK_C1, CME_SCOM_AND, hist.value); + // Calculate new DSL + if (pscrs & BIT32(2)) + { + temp_dsl = ((pscrs & BITS32(20, 4)) >> SHIFT32(23)); + temp_srr1 = SOME_STATE_LOSS_BUT_NOT_TIMEBASE; + } + else + { + temp_dsl = 0; + temp_srr1 = NO_STATE_LOSS; + } - for (thread = 0; thread < MAX_THREADS_PER_CORE; thread++) - { - pscrs.value = in32((CME_LCL_PSCRS01 + (thread << 5))); - dsl = (G_dsl[1].vector & BITS16((thread << 2), 4)) >> - SHIFT16((thread << 2) + 3); - PK_TRACE("C1 PSCRS1%d %x, old dsl %d", thread, pscrs.value, dsl); + G_dsl[core_index][thread] = + MIN(temp_dsl, MAX(act_stop_level, G_dsl[core_index][thread])); - temp0 = pscrs.fields.esl_a_n ? pscrs.fields.rl_a_n : 0 ; - temp1 = hist.fields.act_stop_level; + PK_TRACE_DBG("New dsl%d", G_dsl[core_index][thread]); + + // Calculate new SRR1 + if (G_dsl[core_index][thread] >= STOP_LEVEL_8) + { + srr1[thread] = MOST_STATE_LOSS; + } + else if (G_dsl[core_index][thread] >= STOP_LEVEL_4) + { + srr1[thread] = SOME_STATE_LOSS_BUT_NOT_TIMEBASE; + } + else + { + srr1[thread] = temp_srr1; + } - dsl = MIN(temp0, MAX(temp1, dsl)); - G_dsl[1].vector = ((G_dsl[1].vector & ~BITS16((thread << 2), 4)) | - (dsl << SHIFT16((thread << 2) + 3))); - PK_TRACE("C1 new dsl %d", dsl); + PK_TRACE_DBG("Srr1%d", srr1[thread]); - if (dsl >= STOP_LEVEL_8) - { - G_srr1[1][thread] = MOST_STATE_LOSS; - } - else if (dsl >= STOP_LEVEL_4) - { - G_srr1[1][thread] = SOME_STATE_LOSS_BUT_NOT_TIMEBASE; + // 36-39|44-47|52-55|60-63 + scom_data.words.lower |= + ((((uint32_t)G_dsl[core_index][thread]) << SHIFT64SH(bitloc)) | + (((uint32_t)srr1[thread]) << SHIFT64SH((bitloc + 3)))); } - else - G_srr1[1][thread] = - pscrs.fields.esl_a_n ? SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS; - } - CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C1, CME_STOP_UPDATE_DLS(G_dsl[1], G_srr1[1])); - PK_TRACE("C1 DLS : %x %x %x %x", - G_dsl[1].threads.t0, G_dsl[1].threads.t1, - G_dsl[1].threads.t2, G_dsl[1].threads.t3); - PK_TRACE("C1 SRR1 : %x %x %x %x", - G_srr1[1][0], G_srr1[1][1], G_srr1[1][2], G_srr1[1][3]); + // Report PLS+SRR1 + CME_PUTSCOM(DIRECT_CONTROLS, core_mask, scom_data.value); + } } #else PK_TRACE_INF("SX0.E: Restore PSSCR.PLS+SRR1 back to actual level"); - if (core & CME_MASK_C0) + for (core_mask = 2; core_mask; core_mask--) { - CME_GETSCOM(PPM_SSHSRC, CME_MASK_C0, CME_SCOM_AND, hist.value); - - PK_TRACE("Set PLS+SRR1 for Core0"); - - if (hist.fields.act_stop_level >= STOP_LEVEL_8) - { - CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C0, CME_STOP_UPDATE_PLS_SRR1( - hist.fields.act_stop_level, - MOST_STATE_LOSS, MOST_STATE_LOSS, - MOST_STATE_LOSS, MOST_STATE_LOSS)); - } - else if (hist.fields.act_stop_level >= STOP_LEVEL_4) + if (core & core_mask) { - CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C0, CME_STOP_UPDATE_PLS_SRR1( - hist.fields.act_stop_level, - SOME_STATE_LOSS_BUT_NOT_TIMEBASE, - SOME_STATE_LOSS_BUT_NOT_TIMEBASE, - SOME_STATE_LOSS_BUT_NOT_TIMEBASE, - SOME_STATE_LOSS_BUT_NOT_TIMEBASE)); - } - else - { - CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C0, CME_STOP_UPDATE_PLS_SRR1( - hist.fields.act_stop_level, - ((in32(CME_LCL_PSCRS00) & BIT32(2)) ? - SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS), - ((in32(CME_LCL_PSCRS10) & BIT32(2)) ? - SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS), - ((in32(CME_LCL_PSCRS20) & BIT32(2)) ? - SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS), - ((in32(CME_LCL_PSCRS30) & BIT32(2)) ? - SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS))); - } - } + PK_TRACE_DBG("Set PLS+SRR1 for Core[%d]", core_mask); + CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value); - if (core & CME_MASK_C1) - { - CME_GETSCOM(PPM_SSHSRC, CME_MASK_C1, CME_SCOM_AND, hist.value); + act_stop_level = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11); + scom_data.words.upper = 0; - PK_TRACE("Set PLS+SRR1 for Core1"); + if (act_stop_level >= STOP_LEVEL_8) + { + // MOST_STATE_LOSS(3) + b32/40/48/56 + scom_data.words.lower = + ((BIT64SH(32) | BITS64SH(38, 3) | BITS64SH(46, 3) | + BITS64SH(54, 3) | BITS64SH(62, 2)) | + (act_stop_level << SHIFT64SH(36)) | + (act_stop_level << SHIFT64SH(44)) | + (act_stop_level << SHIFT64SH(52)) | + (act_stop_level << SHIFT64SH(60))); + } + else if (act_stop_level >= STOP_LEVEL_4) + { + // SOME_STATE_LOSS_BUT_NOT_TIMEBASE(2) + scom_data.words.lower = + ((BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56)) | + (BIT64SH(38) | BIT64SH(46) | BIT64SH(54) | BIT64SH(62)) | + (act_stop_level << SHIFT64SH(36)) | + (act_stop_level << SHIFT64SH(44)) | + (act_stop_level << SHIFT64SH(52)) | + (act_stop_level << SHIFT64SH(60))); + } + else + { + // SOME_STATE_LOSS_BUT_NOT_TIMEBASE(2) vs NO_STATE_LOSS(1) + scom_data.words.lower = + ((BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56)) | + (act_stop_level << SHIFT64SH(36)) | + (act_stop_level << SHIFT64SH(44)) | + (act_stop_level << SHIFT64SH(52)) | + (act_stop_level << SHIFT64SH(60)) | + (((in32(CME_LCL_PSCRS00) & BIT32(2)) ? + SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(39)) | + (((in32(CME_LCL_PSCRS10) & BIT32(2)) ? + SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(47)) | + (((in32(CME_LCL_PSCRS20) & BIT32(2)) ? + SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(55)) | + (((in32(CME_LCL_PSCRS30) & BIT32(2)) ? + SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS))); + } - if (hist.fields.act_stop_level >= STOP_LEVEL_8) - { - CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C1, CME_STOP_UPDATE_PLS_SRR1( - hist.fields.act_stop_level, - MOST_STATE_LOSS, MOST_STATE_LOSS, - MOST_STATE_LOSS, MOST_STATE_LOSS)); - } - else if(hist.fields.act_stop_level >= STOP_LEVEL_4) - { - CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C1, CME_STOP_UPDATE_PLS_SRR1( - hist.fields.act_stop_level, - SOME_STATE_LOSS_BUT_NOT_TIMEBASE, - SOME_STATE_LOSS_BUT_NOT_TIMEBASE, - SOME_STATE_LOSS_BUT_NOT_TIMEBASE, - SOME_STATE_LOSS_BUT_NOT_TIMEBASE)); - } - else - { - CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C1, CME_STOP_UPDATE_PLS_SRR1( - hist.fields.act_stop_level, - ((in32(CME_LCL_PSCRS01) & BIT32(2)) ? - SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS), - ((in32(CME_LCL_PSCRS11) & BIT32(2)) ? - SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS), - ((in32(CME_LCL_PSCRS21) & BIT32(2)) ? - SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS), - ((in32(CME_LCL_PSCRS31) & BIT32(2)) ? - SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS))); + CME_PUTSCOM(DIRECT_CONTROLS, core_mask, scom_data.value); } } @@ -956,24 +843,17 @@ STOP1_EXIT: while((core & ~(in32(CME_LCL_SISR) >> SHIFT32(11))) != core); PK_TRACE("Update STOP history: STOP exit completed, core ready"); - CME_STOP_UPDATE_HISTORY(core, - STOP_CORE_READY_RUN, - STOP_TRANS_COMPLETE, - STOP_LEVEL_0, - STOP_LEVEL_0, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE) - - if (core & CME_MASK_C0) - { - G_cme_stop_record.req_level_c0 = 0; - G_cme_stop_record.act_level_c0 = 0; - } + scom_data.words.lower = 0; + scom_data.words.upper = SSH_EXIT_COMPLETE; + CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); - if (core & CME_MASK_C1) + for (core_mask = 2; core_mask; core_mask--) { - G_cme_stop_record.req_level_c1 = 0; - G_cme_stop_record.act_level_c1 = 0; + if (core & core_mask) + { + G_cme_stop_record.req_level[core_mask & 1] = 0; + G_cme_stop_record.act_level[core_mask & 1] = 0; + } } G_cme_stop_record.core_running |= core; diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index 9c9c7294..e8345e92 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -47,7 +47,7 @@ p9_cme_stop_spwu_handler(void* arg, PkIrqId irq) PkMachineContext ctx; int sem_post = 0; uint32_t raw_spwu = (in32(CME_LCL_EISR) & BITS32(14, 2)) >> SHIFT32(15); - uint64_t scom_data; + uint64_t scom_data = 0; if (raw_spwu & CME_MASK_C0) { @@ -190,7 +190,8 @@ void p9_cme_stop_db2_handler(void* arg, PkIrqId irq) { PkMachineContext ctx; - cppm_cmedb2_t db2c0, db2c1; + cppm_cmedb2_t db2c0 = {0}; + cppm_cmedb2_t db2c1 = {0}; MARK_TRAP(STOP_DB2_HANDLER) PK_TRACE_INF("DB2 Handler"); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c index cae31546..7b9e1f90 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c @@ -30,7 +30,7 @@ int p9_hcd_core_arrayinit(uint32_t core) { int rc = CME_STOP_SUCCESS; - uint64_t scom_data; + uint64_t scom_data = 0; PK_TRACE("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); CME_PUTSCOM(C_CPLT_CONF0_OR, core, BIT64(34)); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c index 0a1f7f61..677c1310 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c @@ -49,8 +49,8 @@ enum P9_HCD_CORE_CHIPLET_RESET_CONSTANTS int p9_hcd_core_chiplet_reset(uint32_t core) { - int rc = CME_STOP_SUCCESS; - data64_t scom_data; + int rc = CME_STOP_SUCCESS; + data64_t scom_data = {0}; PK_TRACE("Init NET_CTRL0[1,3-5,11-14,16,18,22,25,26],step needed for hotplug"); CME_PUTSCOM(CPPM_NC0INDIR_OR, core, C_NET_CTRL0_INIT_VECTOR); @@ -90,7 +90,7 @@ p9_hcd_core_chiplet_reset(uint32_t core) // to get the core to scan at 4:1, need to put a scan ratio of 2:1 if run at pll speed. PK_TRACE("Set scan ratio to 2:1 in non-bypass mode via OPCG_ALIGN[47-51]"); CME_GETSCOM(C_OPCG_ALIGN, core, CME_SCOM_AND, scom_data.value); - scom_data.words.lower &= ~BITS32(15, 5); + scom_data.words.lower &= ~BITS64SH(47, 5); #if !EPM_P9_TUNING scom_data.words.lower |= BIT32(19); #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c index 90b5e68c..38a60669 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c @@ -32,7 +32,6 @@ int p9_hcd_core_gptr_time_initf(uint32_t core) { int rc = CME_STOP_SUCCESS; - // Markers needed for gptr time initf PK_TRACE_DBG("Scan ec_gptr ring core value %d", core); putRing(core, CME_SCOM_EQ, ec_gptr); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c index c3d3016d..a544cc76 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c @@ -39,6 +39,5 @@ p9_hcd_core_initf(uint32_t core) PK_TRACE("Scan ec_mode ring core value %d", core); putRing(core, CME_SCOM_EQ, ec_mode); - // Markers needed for core ininf return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c index 25c6d7a9..2f2e37ce 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c @@ -29,7 +29,7 @@ int p9_hcd_core_pcb_arb(uint32_t core, uint8_t req_rel) { - uint32_t sisr; + uint32_t sisr = 0; out32(req_rel ? CME_LCL_SICR_OR : CME_LCL_SICR_CLR, core << SHIFT32(11)); do diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c index 17551f50..626c87eb 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c @@ -47,7 +47,7 @@ p9_hcd_core_poweron(uint32_t core) CME_PUTSCOM(C_PPM_CGCR, core, BIT64(0)); #if !STOP_PRIME - uint64_t scom_data; + uint64_t scom_data = 0; // vdd_pfet_val/sel_override = 0 (disbaled) // vdd_pfet_regulation_finger_en = 0 (controled by FSM) diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c index e734b603..bd3c39e8 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c @@ -48,7 +48,7 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type) // OPCG GO, LBIST mode CME_PUTSCOM(PERV_OPCG_REG0, core, BIT64(1)); #else - uint64_t scom_data; + uint64_t scom_data = 0; PK_TRACE("raise Vital clock region fence"); CME_PUTSCOM(PERV_CPLT_CTRL1_OR, core, BIT64(3)); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c index 6fb65c4a..3ef16035 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c @@ -30,9 +30,9 @@ int p9_hcd_core_startclocks(uint32_t core) { - int rc = CME_STOP_SUCCESS; - uint32_t id_vector; - data64_t scom_data; + int rc = CME_STOP_SUCCESS; + uint32_t id_vector = 0; + data64_t scom_data = {0}; cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_BASE + CME_HEADER_IMAGE_OFFSET); id_vector = pCmeImgHdr->g_cme_location_id; @@ -73,7 +73,7 @@ p9_hcd_core_startclocks(uint32_t core) PK_TRACE("Set fabric chiplet ID values via EQ_CPLT_CONF0[48-51,52-54,56-60]"); CME_GETSCOM(C_CPLT_CONF0, core, CME_SCOM_AND, scom_data.value); - scom_data.words.lower &= ~(BITS32(16, 7) | BITS32(24, 5)); + scom_data.words.lower &= ~(BITS64SH(48, 7) | BITS64SH(56, 5)); scom_data.words.lower |= id_vector; CME_PUTSCOM(C_CPLT_CONF0, core, scom_data.value); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c index 32957704..2d394c66 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c @@ -29,8 +29,8 @@ int p9_hcd_cache_arrayinit(uint32_t quad, uint32_t ex) { - int rc = SGPE_STOP_SUCCESS; - uint64_t scom_data; + int rc = SGPE_STOP_SUCCESS; + uint64_t scom_data = 0; PK_TRACE("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CONF0_OR, quad), BIT64(34)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c index 6893cab9..9dd1fcc1 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c @@ -51,9 +51,10 @@ enum P9_HCD_CACHE_CHIPLET_RESET_CONSTANTS int p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex) { - int rc = SGPE_STOP_SUCCESS; - uint64_t scom_data; - uint32_t core, cbit; + int rc = SGPE_STOP_SUCCESS; + uint64_t scom_data = 0; + uint32_t core = 0; + uint32_t cbit = 0; for(core = 0, cbit = BIT32((quad << 2)); core < CORES_PER_QUAD; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c index babd87e1..424f117e 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c @@ -29,8 +29,8 @@ int p9_hcd_cache_dpll_setup(uint32_t quad) { - int rc = SGPE_STOP_SUCCESS; - uint64_t scom_data; + int rc = SGPE_STOP_SUCCESS; + uint64_t scom_data = 0; // This is necessary to ensure that the DPLL is in Mode 1. // If not, the lock times will go from ~30us to 3-5ms diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c index 7b40a426..6be9285c 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c @@ -31,8 +31,8 @@ extern SgpeStopRecord G_sgpe_stop_record; int p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg) { - int rc = SGPE_STOP_SUCCESS; - uint64_t scom_data; + int rc = SGPE_STOP_SUCCESS; + uint64_t scom_data = 0; PK_TRACE("Drop L2 Regional Fences via CPLT_CTRL1[8/9]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_CLEAR, quad), @@ -151,27 +151,17 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg) GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_RING_FENCE_MASK_LATCH, quad), scom_data); - PK_TRACE("Drop TLBIE Quiesce"); + PK_TRACE("Drop TLBIE Quiesce and L2 Snoop disable"); if (ex & FST_EX_IN_QUAD) { GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SICR_CLR, quad, 0), BIT64(21)); - } - - if (ex & SND_EX_IN_QUAD) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SICR_CLR, quad, 1), BIT64(21)); - } - - PK_TRACE("Drop L2 Snoop Disable"); - - if (ex & FST_EX_IN_QUAD) - { GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_L2_RCMD_DIS_REG, quad, 0), 0); } if (ex & SND_EX_IN_QUAD) { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SICR_CLR, quad, 1), BIT64(21)); GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_L2_RCMD_DIS_REG, quad, 1), 0); } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c index 2bb2e2da..84777f05 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c @@ -48,7 +48,7 @@ p9_hcd_cache_scan0(uint32_t quad, uint64_t regions, uint64_t scan_type) // OPCG GO, LBIST mode GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_OPCG_REG0, quad), BIT64(1)); #else - uint64_t scom_data; + uint64_t scom_data = 0; PK_TRACE("raise Vital clock region fence"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_CPLT_CTRL1_OR, quad), BIT64(3)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c index bcb3f7f9..2b03714e 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c @@ -30,11 +30,12 @@ int p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_ex, int is_stop8) { - int rc = SGPE_STOP_SUCCESS; + + int rc = SGPE_STOP_SUCCESS; #if !SKIP_HOMER_ACCESS - int i; + int i = 0; uint32_t qoffset = 0; uint32_t qaddr = 0; uint64_t qdata = 0; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c index 6c473425..1cc0ff55 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c @@ -32,13 +32,15 @@ extern SgpeStopRecord G_sgpe_stop_record; int p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8) { - int rc = SGPE_STOP_SUCCESS; - int attr_proc_fabric_addr_bar_mode_small_system = 0; // default large - int attr_proc_fabric_pump_mode_chip_is_node = 0; // default group - int exloop = 0; - int excount = 0; - data64_t scom_data = {0}; - ocb_qcsr_t qcsr = {0}; + uint32_t rc = SGPE_STOP_SUCCESS; + uint32_t attr_proc_fabric_addr_bar_mode_small_system = 0; // default large + uint32_t attr_proc_fabric_pump_mode_chip_is_node = 0; // default group + uint32_t ex_loop = 0; + uint32_t ex_count = 0; + uint32_t ex_mask = 0; + uint32_t ex_index = 0; + data64_t scom_data = {0}; + ocb_qcsr_t qcsr = {0}; sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET); if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(16)) @@ -69,202 +71,131 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8) } while (qcsr.fields.change_in_progress); - for (exloop = 0; exloop < 12; exloop++) + for (ex_loop = 0; ex_loop < 12; ex_loop++) { - if (qcsr.value & BIT32(exloop)) + if (qcsr.value & BIT32(ex_loop)) { - excount++; + ex_count++; } } - PK_TRACE_DBG("Reading QCSR: %x, excount: %x", qcsr.value, excount); + PK_TRACE_DBG("Reading QCSR: %x, ex_count: %x", qcsr.value, ex_count); - if (m_ex & FST_EX_IN_QUAD) + for (ex_mask = 2; ex_mask; ex_mask--) { - // p9_l3_scom - - PK_TRACE("Setup L3_LCO_TARGET_ID/VICTIMS on ex0 via EX_L3_MODE_REG1[2-5,6-21]"); - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, 0), scom_data.value); - scom_data.words.upper &= ~BITS32(2, 20); - scom_data.words.upper |= (quad << SHIFT32((5 - 1))); - scom_data.words.upper |= ((qcsr.value & BITS32(0, 12)) >> 6); - - if (excount > 1) - { - PK_TRACE("Assert L3_LCO_ENABLE_CFG on ex0 via EX_L3_MODE_REG1[0]"); - scom_data.words.upper |= BIT32(0); - } - else - { - PK_TRACE("Drop L3_LCO_ENABLE_CFG on ex0 via EX_L3_MODE_REG1[0]"); - scom_data.words.upper &= ~BIT32(0); - } - - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, 0), scom_data.value); - - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 0), scom_data.value); - scom_data.words.upper &= ~(BIT32(1) | BITS32(14, 8) | BIT32(22)); - scom_data.words.upper |= (BIT32(2) | BIT32(17) | BIT32(19)); // set b11 with L2 - - if (attr_proc_fabric_addr_bar_mode_small_system) - { - scom_data.words.upper |= BIT32(22); - } - - if (excount == 2) - { - PK_TRACE("Assert L3_DYN_LCO_BLK_DIS_CFG on ex0 via EX_L3_MODE_REG0[9]"); - scom_data.words.upper |= BIT32(9); - } - else - { - PK_TRACE("Drop L3_DYN_LCO_BLK_DIS_CFG on ex0 via EX_L3_MODE_REG0[9]"); + if (m_ex & ex_mask) + { + ex_index = ex_mask & 1; + PK_TRACE_DBG("Stop11: Working on EX%d", ex_index); + + // p9_l3_scom: EX_L3_MODE_REG0 + + PK_TRACE("Setup L3_LCO_TARGET_ID/VICTIMS via EX_L3_MODE_REG1[2-5,6-21]"); + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, ex_index), scom_data.value); + scom_data.words.upper &= ~BITS32(2, 20); + scom_data.words.upper |= (quad << SHIFT32((5 - 1))); + scom_data.words.upper |= ((qcsr.value & BITS32(0, 12)) >> 6); + + if (ex_count > 1) + { + PK_TRACE("Assert L3_LCO_ENABLE_CFG via EX_L3_MODE_REG1[0]"); + scom_data.words.upper |= BIT32(0); + } + else + { + PK_TRACE("Drop L3_LCO_ENABLE_CFG via EX_L3_MODE_REG1[0]"); + scom_data.words.upper &= ~BIT32(0); + } + + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, ex_index), scom_data.value); + + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, ex_index), + scom_data.value); + scom_data.words.upper &= ~(BIT32(1) | BITS32(14, 8) | BIT32(22)); + scom_data.words.upper |= (BIT32(2) | BIT32(11) | BIT32(17) | BIT32(19)); + + if (attr_proc_fabric_addr_bar_mode_small_system) + { + scom_data.words.upper |= BIT32(22); + } + + if (ex_count == 2) + { + PK_TRACE("Assert L3_DYN_LCO_BLK_DIS_CFG via EX_L3_MODE_REG0[9]"); + scom_data.words.upper |= BIT32(9); + } + else + { + PK_TRACE("Drop L3_DYN_LCO_BLK_DIS_CFG via EX_L3_MODE_REG0[9]"); + scom_data.words.upper &= ~BIT32(9); + } + + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, ex_index), + scom_data.value); + + // p9_ncu_scom: EX_NCU_MODE_REG + + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG, quad, ex_index), + scom_data.value); scom_data.words.upper &= ~BIT32(9); - } - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 0), scom_data.value); + if (attr_proc_fabric_addr_bar_mode_small_system) + { + scom_data.words.upper |= BIT32(9); + } - // p9_ncu_scom + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG, quad, ex_index), + scom_data.value); - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG, quad, 0), scom_data.value); - scom_data.words.upper &= ~BIT32(9); + // p9_ncu_scom: EX_NCU_MODE_REG2 - if (attr_proc_fabric_addr_bar_mode_small_system) - { - scom_data.words.upper |= BIT32(9); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG2, quad, ex_index), + 0x1402220100000000); } - - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG, quad, 0), scom_data.value); - - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG2, quad, 0), 0x1402220100000000); - } - - if (m_ex & SND_EX_IN_QUAD) - { - // p9_l3_scom - - PK_TRACE("Setup L3_LCO_TARGET_ID/VICTIMS on ex1 via EX_L3_MODE_REG1[2-5,6-21]"); - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, 1), scom_data.value); - scom_data.words.upper &= ~BITS32(2, 20); - scom_data.words.upper |= ((quad << SHIFT32((5 - 1))) | BIT32(5)); - scom_data.words.upper |= ((qcsr.value & BITS32(0, 12)) >> 6); - - if (excount > 1) - { - PK_TRACE("Assert L3_LCO_ENABLE_CFG on ex1 via EX_L3_MODE_REG1[0]"); - scom_data.words.upper |= BIT32(0); - } - else - { - PK_TRACE("Drop L3_LCO_ENABLE_CFG on ex1 via EX_L3_MODE_REG1[0]"); - scom_data.words.upper &= ~BIT32(0); - } - - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, 1), scom_data.value); - - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 1), scom_data.value); - scom_data.words.upper &= ~(BIT32(1) | BITS32(14, 8) | BIT32(22)); - scom_data.words.upper |= (BIT32(2) | BIT32(17) | BIT32(19)); // set b11 with L2 - - if (attr_proc_fabric_addr_bar_mode_small_system) - { - scom_data.words.upper |= BIT32(22); - } - - if (excount == 2) - { - PK_TRACE("Assert L3_DYN_LCO_BLK_DIS_CFG on ex1 via EX_L3_MODE_REG0[9]"); - scom_data.words.upper |= BIT32(9); - } - else - { - PK_TRACE("Drop L3_DYN_LCO_BLK_DIS_CFG on ex1 via EX_L3_MODE_REG0[9]"); - scom_data.words.upper &= ~BIT32(9); - } - - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 1), scom_data.value); - - // p9_ncu_scom - - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG, quad, 1), scom_data.value); - scom_data.words.upper &= ~BIT32(9); - - if (attr_proc_fabric_addr_bar_mode_small_system) - { - scom_data.words.upper |= BIT32(9); - } - - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG, quad, 1), scom_data.value); - - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG2, quad, 1), 0x1402220100000000); } } else { - if (m_ex & FST_EX_IN_QUAD) + for (ex_mask = 2; ex_mask; ex_mask--) { - // L3_MODE0[11] L3_ADDR_HASH_EN_CFG must be set along with - // L2_MODE0[21] CFG_HASH_L3_ADDR_EN - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 0), scom_data.value); - scom_data.words.upper |= BIT32(11); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 0), scom_data.value); - - // p9_l2_scom - - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, 0), scom_data.value); - scom_data.words.lower |= BIT32(6); // bit38 - scom_data.words.upper |= BIT32(21); - scom_data.words.upper &= ~BIT32(23); - - if (attr_proc_fabric_addr_bar_mode_small_system) + if (m_ex & ex_mask) { - scom_data.words.upper |= BIT32(23); - } + ex_index = ex_mask & 1; + PK_TRACE_DBG("Stop8: Working on EX%d", ex_index); - if (attr_proc_fabric_pump_mode_chip_is_node) - { - scom_data.words.lower &= ~BIT32(6); - } + // p9_l2_scom: EX_L2_MODE_REG0 + // L3_MODE0[11] L3_ADDR_HASH_EN_CFG must be set along with + // L2_MODE0[21] CFG_HASH_L3_ADDR_EN before drop cache chiplet fence + // if that L2 region is clocked and L2 snoop disable is dropped - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, 0), scom_data.value); + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, ex_index), + scom_data.value); + scom_data.words.lower |= BIT64SH(38); + scom_data.words.upper |= BIT32(21); + scom_data.words.upper &= ~BIT32(23); - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, 0), scom_data.value); - scom_data.words.upper &= BITS32(4, 8); - scom_data.words.upper |= (BIT32(7) | BIT32(9)); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, 0), scom_data.value); - } + if (attr_proc_fabric_addr_bar_mode_small_system) + { + scom_data.words.upper |= BIT32(23); + } - if (m_ex & SND_EX_IN_QUAD) - { - // L3_MODE0[11] L3_ADDR_HASH_EN_CFG must be set along with - // L2_MODE0[21] CFG_HASH_L3_ADDR_EN - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 1), scom_data.value); - scom_data.words.upper |= BIT32(11); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 1), scom_data.value); + if (attr_proc_fabric_pump_mode_chip_is_node) + { + scom_data.words.lower &= ~BIT64SH(38); + } - // p9_l2_scom + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, ex_index), + scom_data.value); - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, 1), scom_data.value); - scom_data.words.lower |= BIT32(6); // bit38 - scom_data.words.upper |= BIT32(21); - scom_data.words.upper &= ~BIT32(23); + // p9_l2_scom: EX_L2_MODE_REG1 - if (attr_proc_fabric_addr_bar_mode_small_system) - { - scom_data.words.upper |= BIT32(23); + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, ex_index), + scom_data.value); + scom_data.words.upper &= BITS32(4, 8); + scom_data.words.upper |= (BIT32(7) | BIT32(9)); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, ex_index), + scom_data.value); } - - if (attr_proc_fabric_pump_mode_chip_is_node) - { - scom_data.words.lower &= ~BIT32(6); - } - - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, 1), scom_data.value); - - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, 1), scom_data.value); - scom_data.words.upper &= BITS32(4, 8); - scom_data.words.upper |= (BIT32(7) | BIT32(9)); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, 1), scom_data.value); } } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c index 406dad22..d688425e 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c @@ -30,9 +30,11 @@ int p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) { - int rc = SGPE_STOP_SUCCESS; - uint32_t id_vector; - data64_t scom_data; + uint32_t rc = SGPE_STOP_SUCCESS; + uint32_t id_vector = 0; + uint32_t ex_mask = 0; + uint32_t bitloc = 0; + data64_t scom_data = {0}; sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET); id_vector = pSgpeImgHdr->g_sgpe_location_id; @@ -49,44 +51,29 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) // QCCR[3/7] EDRAM_VPP_ENABLE_DC // 0x0 -> 0x8 -> 0xC -> 0xE -> 0xF to turn on edram // stagger EDRAM turn-on per EX (not both at same time) - if (ex & FST_EX_IN_QUAD) + for (ex_mask = 2; ex_mask; ex_mask--) { - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(0)); -#if !EPM_P9_TUNING - PPE_WAIT_CORE_CYCLES(48000); -#endif - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(1)); -#if !EPM_P9_TUNING - PPE_WAIT_CORE_CYCLES(4000); -#endif - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(2)); -#if !EPM_P9_TUNING - PPE_WAIT_CORE_CYCLES(16000); -#endif - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(3)); -#if !EPM_P9_TUNING - PPE_WAIT_CORE_CYCLES(4000); -#endif - } + if (ex & ex_mask) + { + bitloc = (ex_mask & 1) << 2; - if (ex & SND_EX_IN_QUAD) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(4)); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(bitloc)); #if !EPM_P9_TUNING - PPE_WAIT_CORE_CYCLES(48000); + PPE_WAIT_CORE_CYCLES(48000); #endif - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(5)); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64((bitloc + 1))); #if !EPM_P9_TUNING - PPE_WAIT_CORE_CYCLES(4000); + PPE_WAIT_CORE_CYCLES(4000); #endif - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(6)); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64((bitloc + 2))); #if !EPM_P9_TUNING - PPE_WAIT_CORE_CYCLES(16000); + PPE_WAIT_CORE_CYCLES(16000); #endif - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(7)); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64((bitloc + 3))); #if !EPM_P9_TUNING - PPE_WAIT_CORE_CYCLES(4000); + PPE_WAIT_CORE_CYCLES(4000); #endif + } } PK_TRACE("Assert cache EX1 ID bit2"); @@ -112,7 +99,7 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) PK_TRACE("Set fabric chiplet ID values via EQ_CPLT_CONF0[48-51,52-54,56-60]"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CONF0, quad), scom_data.value); - scom_data.words.lower &= ~(BITS32(16, 7) | BITS32(24, 5)); + scom_data.words.lower &= ~(BITS64SH(48, 7) | BITS64SH(56, 5)); scom_data.words.lower |= id_vector; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CONF0, quad), scom_data.value); @@ -184,8 +171,6 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) PK_TRACE("Cache clocks running now"); - /// @todo deskew_init() - // ------------------------------- // Cleaning up // ------------------------------- @@ -214,13 +199,14 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_RING_FENCE_MASK_LATCH, quad), scom_data.value); - PK_TRACE("Drop refresh quiesce"); + PK_TRACE("Drop refresh quiesce and LCO Disable"); if (ex & FST_EX_IN_QUAD) { GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, quad, 0), scom_data.value); scom_data.words.upper &= ~BIT32(7); GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, quad, 0), scom_data.value); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, quad, 0), 0); } if (ex & SND_EX_IN_QUAD) @@ -228,17 +214,6 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, quad, 1), scom_data.value); scom_data.words.upper &= ~BIT32(7); GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, quad, 1), scom_data.value); - } - - PK_TRACE("Drop LCO Disable"); - - if (ex & FST_EX_IN_QUAD) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, quad, 0), 0); - } - - if (ex & SND_EX_IN_QUAD) - { GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, quad, 1), 0); } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index 302d5436..ba4d7df6 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -149,17 +149,6 @@ extern "C" { #define PERV_CPLT_STAT0 0x10000100 #define PERV_NET_CTRL1_WAND 0x000F0045 -/// Macro to update STOP History -#define SGPE_STOP_UPDATE_HISTORY(id,base,gated,trans,req_l,act_l,req_e,act_e) \ - hist.value = 0; \ - hist.fields.stop_gated = gated; \ - hist.fields.stop_transition = trans; \ - hist.fields.req_stop_level = req_l; \ - hist.fields.act_stop_level = act_l; \ - hist.fields.req_write_enable = req_e; \ - hist.fields.act_write_enable = act_e; \ - GPE_PUTSCOM_VAR(PPM_SSHSRC, base, id, 0, hist.value); - enum SGPE_IPC_CONSTANTS { ENABLE_CORE_STOP_UPDATES = 1, @@ -196,6 +185,17 @@ enum SGPE_STOP_IRQ_PAYLOAD_MASKS TYPE6_PAYLOAD_EXIT_EVENT = 0xF }; +enum SGPE_STOP_STATE_HISTORY_VECTORS +{ + SSH_EXIT_COMPLETE = 0, + SSH_EXIT_IN_SESSION = (SSH_STOP_GATED | SSH_TRANS_EXIT), + SSH_ENTRY_IN_SESSION = (SSH_STOP_GATED | SSH_TRANS_ENTRY), + SSH_REQ_LEVEL_UPDATE = (SSH_STOP_GATED | SSH_TRANS_ENTRY | SSH_REQ_ENABLE), + SSH_ACT_LEVEL_UPDATE = (SSH_STOP_GATED | SSH_ACT_ENABLE), + SSH_ACT_LV8_COMPLETE = (SSH_ACT_LEVEL_UPDATE | BIT32(8)), + SSH_ACT_LV11_COMPLETE = (SSH_ACT_LEVEL_UPDATE | BIT32(8) | BITS32(10, 2)) +}; + enum SGPE_STOP_EVENT_LEVELS { LEVEL_EX_BASE = 8, @@ -204,21 +204,21 @@ enum SGPE_STOP_EVENT_LEVELS enum SGPE_STOP_CME_FLAGS { - CME_EX1_INDICATOR = BIT64(26), - CME_SIBLING_FUNCTIONAL = BIT64(27), - CME_CORE0_ENTRY_FIRST = BIT64(28), - CME_CORE1_ENTRY_FIRST = BIT64(29), - CME_CORE0_ENABLE = BIT64(30), - CME_CORE1_ENABLE = BIT64(31) + CME_EX1_INDICATOR = BIT32(26), + CME_SIBLING_FUNCTIONAL = BIT32(27), + CME_CORE0_ENTRY_FIRST = BIT32(28), + CME_CORE1_ENTRY_FIRST = BIT32(29), + CME_CORE0_ENABLE = BIT32(30), + CME_CORE1_ENABLE = BIT32(31) }; enum SGPE_STOP_PSCOM_MASK { - PSCOM_MASK_ALL_L2 = BITS64(2, 2) | BITS64(10, 2), - PSCOM_MASK_EX0_L2 = BIT64(2) | BIT64(10), - PSCOM_MASK_EX1_L2 = BIT64(3) | BIT64(11), - PSCOM_MASK_EX0_L3 = BIT64(4) | BIT64(6) | BIT64(8), - PSCOM_MASK_EX1_L3 = BIT64(5) | BIT64(7) | BIT64(9) + PSCOM_MASK_ALL_L2 = BITS32(2, 2) | BITS32(10, 2), + PSCOM_MASK_EX0_L2 = BIT32(2) | BIT32(10), + PSCOM_MASK_EX1_L2 = BIT32(3) | BIT32(11), + PSCOM_MASK_EX0_L3 = BIT32(4) | BIT32(6) | BIT32(8), + PSCOM_MASK_EX1_L3 = BIT32(5) | BIT32(7) | BIT32(9) }; enum SGPE_FUNCTION_STATUS diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index 3e86f930..9e304718 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -71,22 +71,23 @@ p9_sgpe_stop_entry() { int entry_ongoing[2] = {0, 0}; int l3_purge_aborted = 0; - uint32_t ex = 0; - uint32_t qloop; - uint32_t cloop; - uint32_t climit; - uint32_t xentry; - uint32_t qentry; - uint64_t scom_data; - uint64_t temp_data; - uint64_t host_attn; - uint64_t local_xstop; - ppm_sshsrc_t hist; + uint32_t ex = 0; + uint32_t ex_mask = 0; + uint32_t bitloc = 0; + uint32_t qloop = 0; + uint32_t cloop = 0; + uint32_t climit = 0; + uint32_t xentry = 0; + uint32_t qentry = 0; + uint64_t host_attn = 0; + uint64_t local_xstop = 0; + data64_t scom_data = {0}; + data64_t temp_data = {0}; #if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX - int spin; + uint32_t spin = 0; #endif #if !SKIP_IPC - int rc; + uint32_t rc = 0; #endif //-------------------------------------------------------------------------- @@ -339,14 +340,10 @@ p9_sgpe_stop_entry() PK_TRACE("Update STOP history on core[%d]: in transition of entry", ((qloop << 2) + cloop)); - SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), - CORE_ADDR_BASE, - STOP_CORE_IS_GATED, - STOP_TRANS_ENTRY, - STOP_LEVEL_8, - STOP_LEVEL_8, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ENTRY_IN_SESSION; + GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, ((qloop << 2) + cloop), 0, + scom_data.value); } //==================================================== @@ -366,29 +363,29 @@ p9_sgpe_stop_entry() PPE_WAIT_CORE_CYCLES(256) PK_TRACE("Assert partial bad L2/L3 and stopping/stoped l2 pscom masks via RING_FENCE_MASK_LATCH"); - scom_data = 0; + scom_data.words.lower = 0; if (!(G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop))) { - scom_data |= (PSCOM_MASK_EX0_L2 | PSCOM_MASK_EX0_L3); + scom_data.words.upper |= (PSCOM_MASK_EX0_L2 | PSCOM_MASK_EX0_L3); } else if ((ex & FST_EX_IN_QUAD) || (G_sgpe_stop_record.state[qloop].act_state_x0 >= LEVEL_EX_BASE)) { - scom_data |= PSCOM_MASK_EX0_L2; + scom_data.words.upper |= PSCOM_MASK_EX0_L2; } if (!(G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG] & BIT32(qloop))) { - scom_data |= (PSCOM_MASK_EX1_L2 | PSCOM_MASK_EX1_L3); + scom_data.words.upper |= (PSCOM_MASK_EX1_L2 | PSCOM_MASK_EX1_L3); } else if ((ex & SND_EX_IN_QUAD) || (G_sgpe_stop_record.state[qloop].act_state_x1 >= LEVEL_EX_BASE)) { - scom_data |= PSCOM_MASK_EX1_L2; + scom_data.words.upper |= PSCOM_MASK_EX1_L2; } - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_RING_FENCE_MASK_LATCH, qloop), scom_data); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_RING_FENCE_MASK_LATCH, qloop), scom_data.value); @@ -404,14 +401,14 @@ p9_sgpe_stop_entry() do { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_STAT0, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_STAT0, qloop), scom_data.value); } - while((~scom_data) & BIT64(8)); + while(!(scom_data.words.upper & BIT32(8))); PK_TRACE("Check L2 clock is stopped via CLOCK_STAT_SL[4-13]"); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data.value); - if (((~scom_data) & ((uint64_t)ex << SHIFT64(9))) != 0) + if (((~(scom_data.words.upper)) & (ex << SHIFT32(9))) != 0) { PK_TRACE("ERROR: L2 clock stop failed. HALT SGPE!"); pk_halt(); @@ -434,9 +431,9 @@ p9_sgpe_stop_entry() do { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QACSR, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QACSR, qloop), scom_data.value); } - while(((~scom_data >> SHIFT64(37)) & ex) != ex); + while((((~(scom_data.words.lower)) >> SHIFT64SH(37)) & ex) != ex); PK_TRACE("Switch glsmux to refclk to save clock grid power via EXCGCR[34/35]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_CLR, qloop), @@ -481,14 +478,11 @@ p9_sgpe_stop_entry() // shift by 2 == times 4, which is cores per quad PK_TRACE("Update STOP history on core[%d]: in stop level 8", ((qloop << 2) + cloop)); - SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), - CORE_ADDR_BASE, - STOP_CORE_IS_GATED, - entry_ongoing[cloop >> 1], - STOP_LEVEL_8, - STOP_LEVEL_8, - STOP_REQ_DISABLE, - STOP_ACT_ENABLE); + scom_data.words.lower = 0; + scom_data.words.upper = (SSH_ACT_LV8_COMPLETE | + ((entry_ongoing[cloop >> 1]) << SHIFT32(3))); + GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, ((qloop << 2) + cloop), 0, + scom_data.value); } PK_TRACE("Update QSSR: l2_stopped, drop stop_entry_ongoing"); @@ -535,14 +529,10 @@ p9_sgpe_stop_entry() out32(OCB_QSSR_OR, BIT32(qloop + 20)); PK_TRACE("Update STOP history on quad[%d]: update request stop level", qloop); - SGPE_STOP_UPDATE_HISTORY(qloop, - QUAD_ADDR_BASE, - STOP_CACHE_IS_GATED, - STOP_TRANS_ENTRY, - G_sgpe_stop_record.state[qloop].req_state_q, - STOP_LEVEL_11, - STOP_REQ_ENABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | + (G_sgpe_stop_record.state[qloop].req_state_q << SHIFT32(7))); + GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); //================================== MARK_TAG(SE_PURGE_L3, (32 >> qloop)) @@ -646,9 +636,9 @@ p9_sgpe_stop_entry() do { GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, - qloop, 0), scom_data); + qloop, 0), scom_data.value); } - while(scom_data & (BIT64(0) | BIT64(2))); + while(scom_data.words.upper & (BIT32(0) | BIT32(2))); } if(ex & SND_EX_IN_QUAD) @@ -656,9 +646,9 @@ p9_sgpe_stop_entry() do { GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, - qloop, 1), scom_data); + qloop, 1), scom_data.value); } - while(scom_data & (BIT64(0) | BIT64(2))); + while(scom_data.words.upper & (BIT32(0) | BIT32(2))); } //============================================= @@ -678,22 +668,22 @@ p9_sgpe_stop_entry() } #endif - scom_data = 0; - temp_data = 0; + scom_data.value = 0; + temp_data.value = 0; if (ex & FST_EX_IN_QUAD) { GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 0), - scom_data); + scom_data.value); } if (ex & SND_EX_IN_QUAD) { GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 1), - temp_data); + temp_data.value); } } - while((scom_data | temp_data) & BIT64(0)); + while((scom_data.words.upper | temp_data.words.upper) & BIT32(0)); if (l3_purge_aborted) { @@ -718,9 +708,9 @@ p9_sgpe_stop_entry() do { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR, qloop), scom_data.value); } - while(!(scom_data & BIT64(31))); + while(!(scom_data.words.upper & BIT32(31))); PK_TRACE("Drop powerbus purge via QCCR[30]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(30)); @@ -754,9 +744,10 @@ p9_sgpe_stop_entry() { do { - GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIRAMDBG, qloop, 0), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIRAMDBG, qloop, 0), + scom_data.value); } - while(!(scom_data & BIT64(0))); + while(!(scom_data.words.upper & BIT32(0))); PK_TRACE("CME0 Halted"); } @@ -765,9 +756,10 @@ p9_sgpe_stop_entry() { do { - GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIRAMDBG, qloop, 1), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIRAMDBG, qloop, 1), + scom_data.value); } - while(!(scom_data & BIT64(0))); + while(!(scom_data.words.upper & BIT32(0))); PK_TRACE("CME1 Halted"); } @@ -778,16 +770,16 @@ p9_sgpe_stop_entry() // Edram quiesce is asserted by hardware when l3 thold is asserted in cc if (ex & FST_EX_IN_QUAD) { - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 0), scom_data); - scom_data |= BIT64(7); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 0), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 0), scom_data.value); + scom_data.words.upper |= BIT32(7); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 0), scom_data.value); } if (ex & SND_EX_IN_QUAD) { - GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 1), scom_data); - scom_data |= BIT64(7); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 1), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 1), scom_data.value); + scom_data.words.upper |= BIT32(7); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 1), scom_data.value); } PK_TRACE("Check NCU_SATUS_REG[0:3] for all zeros"); @@ -797,9 +789,9 @@ p9_sgpe_stop_entry() do { GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_STATUS_REG, qloop, 0), - scom_data); + scom_data.value); } - while((~scom_data & BITS64(0, 4)) != BITS64(0 , 4)); + while(((~(scom_data.words.upper)) & BITS32(0, 4)) != BITS32(0, 4)); } if (ex & SND_EX_IN_QUAD) @@ -807,9 +799,9 @@ p9_sgpe_stop_entry() do { GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_STATUS_REG, qloop, 1), - scom_data); + scom_data.value); } - while((~scom_data & BITS64(0, 4)) != BITS64(0 , 4)); + while(((~(scom_data.words.upper)) & BITS32(0, 4)) != BITS32(0, 4)); } PK_TRACE_INF("SE11.C: NCU Status Clean"); @@ -848,16 +840,16 @@ p9_sgpe_stop_entry() do { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_STAT0, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_STAT0, qloop), scom_data.value); } - while((~scom_data) & BIT64(8)); + while(!(scom_data.words.upper & BIT32(8))); PK_TRACE("Check core clock is stopped via CLOCK_STAT_SL[4-13]"); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data.value); - if (((~scom_data) & (CLK_REGION_ALL_BUT_EX | - ((uint64_t)ex << SHIFT64(7)) | - ((uint64_t)ex << SHIFT64(13)))) != 0) + if (((~scom_data.value) & (CLK_REGION_ALL_BUT_EX | + ((uint64_t)ex << SHIFT64(7)) | + ((uint64_t)ex << SHIFT64(13)))) != 0) { PK_TRACE("ERROR: Cache clock stop failed. HALT SGPE!"); pk_halt(); @@ -897,32 +889,33 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), BITS64(4, 2) | BIT64(11) | BIT64(59)); PK_TRACE("FCMS: checkword set"); - scom_data = 0xa5a5a5a5a5a5a5a5; - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); + scom_data.value = 0xa5a5a5a5a5a5a5a5; + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); for(spin = 1;; spin++) { PK_TRACE("FCMS: spin ring loop%d", spin); - scom_data = (G_ring_spin[spin][0] - G_ring_spin[spin - 1][0]) << 32; - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data); + scom_data.words.upper = (G_ring_spin[spin][0] - G_ring_spin[spin - 1][0]); + scom_data.words.lower = 0; + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data.value); PK_TRACE("FCMS: Poll OPCG done for ring spin"); do { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x10000100, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x10000100, qloop), scom_data.value); } - while(~scom_data & BIT64(8)); + while(!(scom_data.words.upper & BIT32(8))); if (spin == 9) { PK_TRACE("FCMS: checkword check"); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); - if (scom_data != 0xa5a5a5a5a5a5a5a5) + if (scom_data.value != 0xa5a5a5a5a5a5a5a5) { PK_TRACE("ERROR: checkword[%x%x] failed. HALT SGPE!", - UPPER32(scom_data), LOWER32(scom_data)); + scom_data.words.upper, scom_data.words.lower); pk_halt(); } @@ -930,14 +923,15 @@ p9_sgpe_stop_entry() } PK_TRACE("FCMS: save pbie read ptr"); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); - EXTRACT_RING_BITS(G_ring_spin[spin][1], scom_data, G_ring_save[qloop][spin - 1]); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); + EXTRACT_RING_BITS(G_ring_spin[spin][1], scom_data.value, + G_ring_save[qloop][spin - 1]); PK_TRACE("FCMS: mask: %8x %8x", UPPER32(G_ring_spin[spin][1]), LOWER32(G_ring_spin[spin][1])); PK_TRACE("FCMS: ring: %8x %8x", - UPPER32(scom_data), - LOWER32(scom_data)); + scom_data.words.upper, + scom_data.words.lower); PK_TRACE("FCMS: save: %8x %8x", UPPER32(G_ring_save[qloop][spin - 1]), LOWER32(G_ring_save[qloop][spin - 1])); @@ -960,33 +954,26 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(16)); PK_TRACE("Shutdown L3 EDRAM via QCCR[0-3/4-7]"); + // QCCR[0/4] EDRAM_ENABLE_DC // QCCR[1/5] EDRAM_VWL_ENABLE_DC // QCCR[2/6] L3_EX0/1_EDRAM_VROW_VBLH_ENABLE_DC // QCCR[3/7] EDRAM_VPP_ENABLE_DC - - if (ex & SND_EX_IN_QUAD) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), - BIT64(7)); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), - BIT64(6)); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), - BIT64(5)); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), - BIT64(4)); - } - - if (ex & FST_EX_IN_QUAD) + for (ex_mask = 2; ex_mask; ex_mask--) { - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), - BIT64(3)); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), - BIT64(2)); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), - BIT64(1)); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), - BIT64(0)); + if (ex & ex_mask) + { + bitloc = (ex_mask & 1) << 2; + + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), + BIT64((bitloc + 3))); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), + BIT64((bitloc + 2))); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), + BIT64((bitloc + 1))); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), + BIT64(bitloc)); + } } #if !STOP_PRIME @@ -1012,9 +999,9 @@ p9_sgpe_stop_entry() do { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, qloop), scom_data.value); } - while(!(scom_data & BIT64(3))); + while(!(scom_data.words.upper & BIT32(3))); PK_TRACE("Power off VDD via PFCS[0-1]"); // vdd_pfet_force_state = 01 (Force Voff) @@ -1024,9 +1011,9 @@ p9_sgpe_stop_entry() do { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, qloop), scom_data.value); } - while(!(scom_data & BIT64(1))); + while(!(scom_data.words.upper & BIT32(1))); PK_TRACE("Turn off force voff via PFCS[0-3]"); // vdd_pfet_force_state = 00 (Nop) @@ -1051,25 +1038,16 @@ p9_sgpe_stop_entry() PK_TRACE("Update STOP history on core[%d]: in stop level 11", ((qloop << 2) + cloop)); - SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), - CORE_ADDR_BASE, - STOP_CORE_IS_GATED, - STOP_TRANS_COMPLETE, - STOP_LEVEL_11, - STOP_LEVEL_11, - STOP_REQ_DISABLE, - STOP_ACT_ENABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ACT_LV11_COMPLETE ; + GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, ((qloop << 2) + cloop), 0, + scom_data.value); } PK_TRACE("Update STOP history on quad[%d]: in stop level 11", qloop); - SGPE_STOP_UPDATE_HISTORY(qloop, - QUAD_ADDR_BASE, - STOP_CACHE_IS_GATED, - STOP_TRANS_COMPLETE, - STOP_LEVEL_11, - STOP_LEVEL_11, - STOP_REQ_DISABLE, - STOP_ACT_ENABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_ACT_LV11_COMPLETE; + GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); PK_TRACE("Update QSSR: quad_stopped"); out32(OCB_QSSR_OR, BIT32(qloop + 14)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index 1c299d1a..dac878ad 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -54,8 +54,8 @@ uint32_t G_fcm_spin[4] = {0, 435, 1402, 2411}; void fused_core_mode_scan_fix(uint32_t qloop, int l2bit) { - int spin; - uint64_t scom_data; + uint32_t spin = 0; + uint64_t scom_data = 0; // bit8/9 = l2-0/1, bit49 = cfg PK_TRACE("FCMS: Setup scan register to select the ring"); @@ -110,28 +110,29 @@ fused_core_mode_scan_fix(uint32_t qloop, int l2bit) int p9_sgpe_stop_exit() { - uint32_t m_l2; - uint32_t m_pg; - uint32_t cloop; - uint32_t qloop; - uint32_t cexit; - uint32_t qspwu; - uint32_t core; - int cme; -#if NIMBUS_DD_LEVEL != 1 - int fused_core_mode = 0; -#endif - uint64_t scom_data = 0; - ppm_sshsrc_t hist; + uint32_t m_l2 = 0; + uint32_t m_pg = 0; + uint32_t cloop = 0; + uint32_t qloop = 0; + uint32_t cexit = 0; + uint32_t qspwu = 0; + uint32_t ex_mask = 0; + uint32_t ec_mask = 0; + uint32_t ex_index = 0; + uint32_t ec_index = 0; + data64_t scom_data = {0}; #if !STOP_PRIME - ocb_ccsr_t ccsr; - uint64_t cme_flags; + ocb_ccsr_t ccsr = {0}; + uint32_t cme_flags = 0; #if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX - int spin; + uint32_t spin = 0; +#endif #endif +#if NIMBUS_DD_LEVEL != 1 + uint32_t fused_core_mode = 0; #endif #if !SKIP_IPC - int rc; + uint32_t rc = 0; #endif //=============================== @@ -305,14 +306,10 @@ p9_sgpe_stop_exit() PK_TRACE("Update STOP history on core[%d]: in transition of exit", ((qloop << 2) + cloop)); - SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), - CORE_ADDR_BASE, - STOP_CORE_IS_GATED, - STOP_TRANS_EXIT, - STOP_LEVEL_0, - STOP_LEVEL_0, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_EXIT_IN_SESSION; + GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, ((qloop << 2) + cloop), 0, + scom_data.value); } @@ -329,14 +326,9 @@ p9_sgpe_stop_exit() PK_TRACE("Update STOP history on quad[%d]: in transition of exit", qloop); - SGPE_STOP_UPDATE_HISTORY(qloop, - QUAD_ADDR_BASE, - STOP_CACHE_IS_GATED, - STOP_TRANS_EXIT, - STOP_LEVEL_0, - STOP_LEVEL_0, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_EXIT_IN_SESSION; + GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); //================================= MARK_TAG(SX_POWERON, (32 >> qloop)) @@ -391,16 +383,17 @@ p9_sgpe_stop_exit() #endif // set 20, 22, 24 and 26 during Stop11 Exit after setting up the DPLL - scom_data = BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26); + scom_data.words.lower = 0; + scom_data.words.upper = BIT32(20) | BIT32(22) | BIT32(24) | BIT32(26); // set 21, 23, 25, and 27 if EX0 is bad (not partial good) if ((~m_pg) & FST_EX_IN_QUAD) { - scom_data |= BIT64(21) | BIT64(23) | BIT64(25) | BIT64(27); + scom_data.words.upper |= BIT32(21) | BIT32(23) | BIT32(25) | BIT32(27); } PK_TRACE("Assert inter-ppm settings via QPMMR[22,24,26,EX0PB:21,23,25]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_OR, qloop), scom_data); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_OR, qloop), scom_data.value); //======================================= MARK_TAG(SX_CHIPLET_INITS, (32 >> qloop)) @@ -483,32 +476,32 @@ p9_sgpe_stop_exit() GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), BITS64(4, 2) | BIT64(11) | BIT64(59)); PK_TRACE("PBRW: checkword set"); - scom_data = 0xa5a5a5a5a5a5a5a5; - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); + scom_data.value = 0xa5a5a5a5a5a5a5a5; + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); for(spin = 1;; spin++) { PK_TRACE("PBRW: spin ring loop%d", spin); - scom_data = (G_ring_spin[spin][0] - G_ring_spin[spin - 1][0]) << 32; - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data); + scom_data.value = (G_ring_spin[spin][0] - G_ring_spin[spin - 1][0]) << 32; + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data.value); PK_TRACE("PBRW: Poll OPCG done for ring spin"); do { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x10000100, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x10000100, qloop), scom_data.value); } - while(~scom_data & BIT64(8)); + while(!(scom_data.words.upper & BIT32(8))); if (spin == 9) { PK_TRACE("PBRW: checkword check"); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); - if (scom_data != 0xa5a5a5a5a5a5a5a5) + if (scom_data.value != 0xa5a5a5a5a5a5a5a5) { PK_TRACE_INF("ERROR: checkword[%x%x] failed. HALT SGPE!", - UPPER32(scom_data), LOWER32(scom_data)); + scom_data.words.upper, scom_data.words.lower); pk_halt(); } @@ -516,24 +509,25 @@ p9_sgpe_stop_exit() } PK_TRACE("PBRW: restore pbie read ptr"); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); PK_TRACE("PBRW: mask: %8x %8x", UPPER32(G_ring_spin[spin][1]), LOWER32(G_ring_spin[spin][1])); PK_TRACE("PBRW: ring: %8x %8x", - UPPER32(scom_data), - LOWER32(scom_data)); + scom_data.words.upper, + scom_data.words.lower); PK_TRACE("PBRW: save: %8x %8x", UPPER32(G_ring_save[qloop][spin - 1]), LOWER32(G_ring_save[qloop][spin - 1])); - RESTORE_RING_BITS(G_ring_spin[spin][1], scom_data, G_ring_save[qloop][spin - 1]); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); + RESTORE_RING_BITS(G_ring_spin[spin][1], scom_data.value, + G_ring_save[qloop][spin - 1]); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); PK_TRACE("PBRW: mask: %8x %8x", UPPER32(G_ring_spin[spin][1]), LOWER32(G_ring_spin[spin][1])); PK_TRACE("PBRW: ring: %8x %8x", - UPPER32(scom_data), - LOWER32(scom_data)); + scom_data.words.upper, + scom_data.words.lower); PK_TRACE("PBRW: save: %8x %8x", UPPER32(G_ring_save[qloop][spin - 1]), LOWER32(G_ring_save[qloop][spin - 1])); @@ -619,30 +613,29 @@ p9_sgpe_stop_exit() PK_TRACE_DBG("Check: quad[%d] m_l2[%d] m_pg[%d] Serviced by SX11SH", qloop, m_l2, m_pg); - for(cme = 0; cme < EXES_PER_QUAD; cme += 2) + for (ec_index = 0; ec_index < CORES_PER_QUAD; ec_index += 2) { - core = ((cexit & BITS32(cme, 2)) >> SHIFT32((cme + 1))); + ec_mask = ((cexit & BITS32(ec_index, 2)) >> SHIFT32((ec_index + 1))); - if(!core) + if(!ec_mask) { continue; } - PK_TRACE("Assert core[%d]-L2/CC quiesces via SICR[6/7,8/9]", core); - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SICR_OR, - qloop, (cme >> 1)), - ((uint64_t)core << SHIFT64(7) | - (uint64_t)core << SHIFT64(9))); + PK_TRACE("Assert core[%d]-L2/CC quiesces via SICR[6/7,8/9]", ec_mask); + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SICR_OR, qloop, (ec_index >> 1)), + ((uint64_t)ec_mask << SHIFT64(7) | + (uint64_t)ec_mask << SHIFT64(9))); - PK_TRACE("Poll for interface quiesced via CME[%d] SISR[30,31]", cme); + PK_TRACE("Poll for interface quiesced via CME[%d] SISR[30,31]", ec_index); do { - GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SISR, - qloop, (cme >> 1)), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SISR, qloop, (ec_index >> 1)), + scom_data.value); } - while(((scom_data >> 32) & core) != core); + while(((scom_data.words.upper) & ec_mask) != ec_mask); } #if !STOP_PRIME @@ -685,232 +678,147 @@ p9_sgpe_stop_exit() } while (ccsr.fields.change_in_progress); - if (m_pg & FST_EX_IN_QUAD) + for (ex_mask = 2; ex_mask; ex_mask--) { - cme_flags = 0; - - if (m_pg & SND_EX_IN_QUAD) - { - cme_flags |= CME_SIBLING_FUNCTIONAL; - } - -#if NIMBUS_DD_LEVEL != 1 - - GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SISR, qloop, 0), scom_data); - - if (scom_data & BIT64(9)) - { - fused_core_mode = 1; - } - else - { - fused_core_mode = 0; - } - -#endif - - if (ccsr.value & BIT32((qloop << 2))) - { - cme_flags |= CME_CORE0_ENABLE; - GPE_GETSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0, - ((qloop << 2))), scom_data); - - if (!(scom_data & BIT64(18))) - { - cme_flags |= CME_CORE0_ENTRY_FIRST; - } - -#if NIMBUS_DD_LEVEL != 1 - - if (fused_core_mode) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR_OR, - ((qloop << 2))), BIT64(9)); - } - -#endif - - } - - if (ccsr.value & BIT32((qloop << 2) + 1)) + if (m_pg & ex_mask) { - cme_flags |= CME_CORE1_ENABLE; - GPE_GETSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0, - ((qloop << 2) + 1)), scom_data); + cme_flags = 0; + ex_index = ex_mask & 1; + ec_index = ((qloop << 2) + (ex_index << 1)); - if (!(scom_data & BIT64(18))) + if (ex_index == 1) { - cme_flags |= CME_CORE1_ENTRY_FIRST; + cme_flags |= CME_EX1_INDICATOR; } -#if NIMBUS_DD_LEVEL != 1 - - if (fused_core_mode) + if (m_pg & (~ex_mask)) { - GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR_OR, - ((qloop << 2) + 1)), BIT64(9)); + cme_flags |= CME_SIBLING_FUNCTIONAL; } -#endif - - } - - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS_OR, qloop, 0), - cme_flags); - } - - if (m_pg & SND_EX_IN_QUAD) - { - cme_flags = CME_EX1_INDICATOR; - - if (m_pg & FST_EX_IN_QUAD) - { - cme_flags |= CME_SIBLING_FUNCTIONAL; - } - #if NIMBUS_DD_LEVEL != 1 - GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SISR, qloop, 1), scom_data); + GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SISR, qloop, ex_index), + scom_data.value); - if (scom_data & BIT64(9)) - { - fused_core_mode = 1; - } - else - { fused_core_mode = 0; - } - -#endif - - if (ccsr.value & BIT32(((qloop << 2) + 2))) - { - cme_flags |= CME_CORE0_ENABLE; - GPE_GETSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0, - ((qloop << 2) + 2)), scom_data); - - if (!(scom_data & BIT64(18))) - { - cme_flags |= CME_CORE0_ENTRY_FIRST; - } - -#if NIMBUS_DD_LEVEL != 1 - if (fused_core_mode) + if (scom_data.words.upper & BIT32(9)) { - GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR_OR, - ((qloop << 2) + 2)), BIT64(9)); + fused_core_mode = 1; } #endif - } - - if (ccsr.value & BIT32(((qloop << 2) + 3))) - { - cme_flags |= CME_CORE1_ENABLE; - GPE_GETSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0, - ((qloop << 2) + 3)), scom_data); - - if (!(scom_data & BIT64(18))) + for (cloop = 0; cloop < CORES_PER_EX; cloop++) { - cme_flags |= CME_CORE1_ENTRY_FIRST; - } + if (ccsr.value & BIT32((ec_index + cloop))) + { + cme_flags |= (CME_CORE0_ENABLE >> cloop); + GPE_GETSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0, + (ec_index + cloop)), scom_data.value); + + if (!(scom_data.words.upper & BIT32(18))) + { + cme_flags |= (CME_CORE0_ENTRY_FIRST >> cloop); + } #if NIMBUS_DD_LEVEL != 1 - if (fused_core_mode) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR_OR, - ((qloop << 2) + 3)), BIT64(9)); - } + if (fused_core_mode) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR_OR, + (ec_index + cloop)), BIT64(9)); + } #endif - } + } + } - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS_OR, qloop, 1), - cme_flags); + scom_data.words.lower = 0; + scom_data.words.upper = cme_flags; + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS_OR, qloop, ex_index), + scom_data.value); + } } // enable cme trace array + // + // Trace configuration + // CME_LCL_DBG + // 0: LCL_EN_DBG + // 4: LCL_EN_INTR_ADDR + // 5: LCL_EN_TRACE_EXTRA + // 6: LCL_EN_TRACE_STALL + // 7: LCL_EN_WAIT_CYCLES + // 8: LCL_EN_FULL_SPEED + // inst: 3D20C000 | addis r9, 0, 0xC000 | R9 = 0xC0000000 + // inst: 3C208F80 | addis r1, 0, 0x8F80 | R1 = 0x8F800000 + // inst: 90290120 | stw r1, 0x120(r9) | 0xC0000120 = R1 + // + // 1. The trace array has to be stopped to configure it + // 2. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRCTRL_CONFIG + // bit0: store_trig_mode_lt = 1 + // bit 11 enh_trace_mode = 1 + // bit 14:15 = trace_select_lt = 10 for CME0 + // 3. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_0 + // Set trace data compare mask to 0 (0:63) + // 4. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_1 + // Set trace data compare mask to 0 (64:87) + // 5. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_4 + // Clear MSKa, MSKb + // 6. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_5 + // Clear MSKc, MSKd + // 7. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_9 + // bit 0 = disable compression: + // bit 1 = error_bit_compresion_care_mask + // (default is zero so should be enabled) + // 32 msk_err_q <= error_mode_lt(0); + // 33 pat_err_q <= error_mode_lt(1); + // 34 trig0_err_msk <= error_mode_lt(2); + // 35 trig1_err_msk <= error_mode_lt(3); + // match_err <= (msk_err_q or not pat_err_q) + // xor error_stage_lt(0); + // mask = 0 and pattern = 1 and may be trigger 0 + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET); if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(4)) { - // Trace configuration - // CME_LCL_DBG - // 0: LCL_EN_DBG - // 4: LCL_EN_INTR_ADDR - // 5: LCL_EN_TRACE_EXTRA - // 6: LCL_EN_TRACE_STALL - // 7: LCL_EN_WAIT_CYCLES - // 8: LCL_EN_FULL_SPEED - // inst: 3D20C000 | addis r9, 0, 0xC000 | R9 = 0xC0000000 - // inst: 3C208F80 | addis r1, 0, 0x8F80 | R1 = 0x8F800000 - // inst: 90290120 | stw r1, 0x120(r9) | 0xC0000120 = R1 - - // 1. The trace array has to be stopped to configure it - // 2. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRCTRL_CONFIG - // bit0: store_trig_mode_lt = 1 - // bit 11 enh_trace_mode = 1 - // bit 14:15 = trace_select_lt = 10 for CME0 - // 3. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_0 - // Set trace data compare mask to 0 (0:63) - // 4. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_1 - // Set trace data compare mask to 0 (64:87) - // 5. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_4 - // Clear MSKa, MSKb - // 6. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_5 - // Clear MSKc, MSKd - // 7. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_9 - // bit 0 = disable compression: - // bit 1 = error_bit_compresion_care_mask - // (default is zero so should be enabled) - // 32 msk_err_q <= error_mode_lt(0); - // 33 pat_err_q <= error_mode_lt(1); - // 34 trig0_err_msk <= error_mode_lt(2); - // 35 trig1_err_msk <= error_mode_lt(3); - // match_err <= (msk_err_q or not pat_err_q) - // xor error_stage_lt(0); - // mask = 0 and pattern = 1 and may be trigger 0 - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, qloop), BIT64(1)); - if (m_pg & FST_EX_IN_QUAD) + for (ex_mask = 2; ex_mask; ex_mask--) { - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 0), 0x3D20C00000000000); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 0), 0x3C208F8000000000); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 0), 0x9029012000000000); - - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRCTRL_CONFIG, qloop), - (BIT64(0) | BIT64(11) | BIT64(14))); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_0, qloop), 0); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_1, qloop), 0); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_4, qloop), 0); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_5, qloop), 0); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_9, qloop), - BITS64(33, 2)); - } + if (m_pg & ex_mask) + { - if (m_pg & SND_EX_IN_QUAD) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 1), 0x3D20C00000000000); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 1), 0x3C208F8000000000); - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 1), 0x9029012000000000); - - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRCTRL_CONFIG | 0x80), - qloop), (BIT64(0) | BIT64(11) | BIT64(14))); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_0 | 0x80), - qloop), 0); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_1 | 0x80), - qloop), 0); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_4 | 0x80), - qloop), 0); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_5 | 0x80), - qloop), 0); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_9 | 0x80), - qloop), BITS64(33, 2)); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, ex_index), + 0x3D20C00000000000); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, ex_index), + 0x3C208F8000000000); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, ex_index), + 0x9029012000000000); + + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD( + (L3TRA_TRACE_TRCTRL_CONFIG | (ex_index << 7)), + qloop), (BIT64(0) | BIT64(11) | BIT64(14))); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD( + (L3TRA_TRACE_TRDATA_CONFIG_0 | (ex_index << 7)), + qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD( + (L3TRA_TRACE_TRDATA_CONFIG_1 | (ex_index << 7)), + qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD( + (L3TRA_TRACE_TRDATA_CONFIG_4 | (ex_index << 7)), + qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD( + (L3TRA_TRACE_TRDATA_CONFIG_5 | (ex_index << 7)), + qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD( + (L3TRA_TRACE_TRDATA_CONFIG_9 | (ex_index << 7)), + qloop), BITS64(33, 2)); + } } } @@ -949,14 +857,9 @@ p9_sgpe_stop_exit() PK_TRACE("Update STOP history on quad[%d]: \ STOP exit completed, cache ready", qloop); - SGPE_STOP_UPDATE_HISTORY(qloop, - QUAD_ADDR_BASE, - STOP_CACHE_READY_RUN, - STOP_TRANS_COMPLETE, - STOP_LEVEL_0, - STOP_LEVEL_0, - STOP_REQ_DISABLE, - STOP_ACT_DISABLE); + scom_data.words.lower = 0; + scom_data.words.upper = SSH_EXIT_COMPLETE; + GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); PK_TRACE("Update QSSR: drop quad_stopped"); out32(OCB_QSSR_CLR, BIT32(qloop + 14)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c index 6c0ae6a6..1384b7e3 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c @@ -86,15 +86,15 @@ void p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) { PkMachineContext ctx; - uint32_t cirq; - uint32_t qirq; - uint32_t cloop; - uint32_t qloop; + uint32_t cirq = 0; + uint32_t qirq = 0; + uint32_t cloop = 0; + uint32_t qloop = 0; uint32_t cpending_t2 = 0; uint32_t cpending_t3 = 0; uint32_t qpending_t6 = 0; uint32_t payload = 0; - uint64_t scom_data; + uint64_t scom_data = 0; //========================= MARK_TRAP(STOP_PIG_HANDLER) |
