CME Code Size Reduction ATTEMPT#3

  -- some IOTA kernel cleanup
  -- also add checking for IOTA execution stack overflow
  -- re-coded to eliminate some math library macro usage
  -- added native 16-bit multiply
  -- re-coded to remove redundancy from external interrupt handler
  -- removed dec handler (optional define) and other minor cleanup
  -- fixed Interrupt initialization code in std_init (all PPE images)
  -- always inline pstate_db0_clip_bcast & update_vdm_jump_values_in_dpll
  -- optimized pls calculation code
  -- optimized pstate init, db1 handler, core good handling
  -- optimized pmcr requests and pmsr updates (always write for both cores)

Key_Cronus_Test=PM_REGRESS

Change-Id: I759785cd28f6eda8c807a476c7173a8fb39bbc38
Original-Change-Id: If48fec5832bd5e46cb89f0d6a97d90a488e8ff7b
CQ: SW415503
RTC: 178789
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53381
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

1 files changed, 21 insertions, 26 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 559bcf9b..009be29f 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -705,6 +705,7 @@ p9_cme_stop_entry()
                 PK_TRACE("RAMMING Set SPR mode to LT0-7 via SPR_MODE[20-27]");
                 CME_PUTSCOM(SPR_MODE, core, BITS64(20, 8));
 
+
                 if (core & CME_MASK_C0)
                 {
                     PK_TRACE("RAMMING Set SPRC to scratch0 for core0 via SCOM_SPRC");
@@ -718,46 +719,39 @@ p9_cme_stop_entry()
                     CME_PUTSCOM(SCOM_SPRC, CME_MASK_C1, BIT64(60));
                     CME_GETSCOM(SCRATCH1, CME_MASK_C1, G_scratch[1]);
                 }
-            }
 
-            if ((core & CME_MASK_C0) && G_cme_stop_record.req_level[0] > STOP_LEVEL_3)
-            {
+                uint32_t pls_core = ((G_cme_stop_record.req_level[0] > STOP_LEVEL_3) ? (core & CME_MASK_C0) : 0)
+                                    | ((G_cme_stop_record.req_level[1] > STOP_LEVEL_3) ? (core & CME_MASK_C1) : 0);
+
                 for(thread = 0; thread < 4; thread++)
                 {
                     PK_TRACE("PSSCR RAM: mfspr psscr, gpr0 via RAM_CTRL");
-                    CME_PUTSCOM(RAM_CTRL, CME_MASK_C0, RAM_MFSPR_PSSCR_GPR0 | (((uint64_t) thread) << 62));
+                    CME_PUTSCOM(RAM_CTRL, pls_core, RAM_MFSPR_PSSCR_GPR0 | (((uint64_t) thread) << 62));
 
                     PK_TRACE("PSSCR RAM: mtspr sprd , gpr0 via RAM_CTRL");
-                    CME_PUTSCOM(RAM_CTRL, CME_MASK_C0, RAM_MTSPR_SPRD_GPR0 | (((uint64_t) thread) << 62));
-                    CME_GETSCOM(SCRATCH0, CME_MASK_C0, scom_data.value);
+                    CME_PUTSCOM(RAM_CTRL, pls_core, RAM_MTSPR_SPRD_GPR0 | (((uint64_t) thread) << 62));
+
+                    if (pls_core & CME_MASK_C0)
+                    {
+                        CME_GETSCOM(SCRATCH0, CME_MASK_C0, scom_data.value);
+                        G_pls[0][thread] = (scom_data.words.upper & BITS32(0, 4)) >> SHIFT32(3);
+                    }
 
-                    G_pls[0][thread] = (scom_data.words.upper & BITS32(0, 4)) >> SHIFT32(3);
 #ifdef PLS_DEBUG
                     PKTRACE("PSSCR %X %X c0thread %X", scom_data.words.upper, scom_data.words.lower, thread);
 #endif
-                }
-            }
 
-            if ((core & CME_MASK_C1) && G_cme_stop_record.req_level[1] > STOP_LEVEL_3)
-            {
-                for (thread = 0; thread < 4; thread++)
-                {
-                    PK_TRACE("PSSCR RAM: mfspr psscr, gpr0 via RAM_CTRL");
-                    CME_PUTSCOM(RAM_CTRL, CME_MASK_C1, RAM_MFSPR_PSSCR_GPR0 | (((uint64_t) thread) << 62));
-
-                    PK_TRACE("PSSCR RAM: mtspr sprd , gpr0 via RAM_CTRL");
-                    CME_PUTSCOM(RAM_CTRL, CME_MASK_C1, RAM_MTSPR_SPRD_GPR0 | (((uint64_t) thread) << 62));
-                    CME_GETSCOM(SCRATCH1, CME_MASK_C1, scom_data.value);
+                    if (pls_core & CME_MASK_C1)
+                    {
+                        CME_GETSCOM(SCRATCH1, CME_MASK_C1, scom_data.value);
+                        G_pls[1][thread] = (scom_data.words.upper & BITS32(0, 4)) >> SHIFT32(3);
+                    }
 
-                    G_pls[1][thread] = (scom_data.words.upper & BITS32(0, 4)) >> SHIFT32(3);
 #ifdef PLS_DEBUG
                     PKTRACE("PSSCR %X %X c1thread %X", scom_data.words.upper, scom_data.words.lower, thread);
 #endif
                 }
-            }
 
-            if (target_level > STOP_LEVEL_3 || deeper_level > STOP_LEVEL_3)
-            {
                 PK_TRACE("RAMMING Disable thread0-3 for RAM via THREAD_INFO");
                 CME_PUTSCOM(THREAD_INFO, core, 0);
 
@@ -786,9 +780,11 @@ p9_cme_stop_entry()
 
                 PK_TRACE("RAMMING Clear core maintenance mode via direct controls");
                 CME_PUTSCOM(DIRECT_CONTROLS, core, (BIT64(3) | BIT64(11) | BIT64(19) | BIT64(27)));
+
+                sync();
+
             }
 
-            sync();
 #endif
 
 
@@ -1372,7 +1368,7 @@ p9_cme_stop_entry()
 
                 CME_GETSCOM_OR( CPPM_CSAR, core, scom_data.value );
 
-                if( CME_STOP_HCODE_ERR_INJ_BIT & scom_data.words.upper )
+                if( BIT64(CPPM_CSAR_STOP_HCODE_ERROR_INJECT) & scom_data.value )
                 {
                     PK_TRACE_DBG("CME STOP ENTRY ERROR INJECT TRAP");
                     PK_PANIC(CME_STOP_ENTRY_TRAP_INJECT);
@@ -1622,7 +1618,6 @@ p9_cme_stop_entry()
             }
 
             sync();
-
             PK_TRACE("Clear special wakeup after wakeup_notify = 1 since it is edge triggered");
             out32(CME_LCL_EISR_CLR, core << SHIFT32(15));