IOTA

- implement iota panic ("dead") codes
- fix uih interrupt window condition leading to iota machine stack
  overflow and/or phantom interrupt detection
- fix iota static machine stack init value
- refactor UIH for both IOTA and PK to pull the priority table from a
  common source
- the entire INTERCME0 IRQ handler in PK is executed with EE=0, for IOTA
  this can only be emulated by masking all higher priorities in the UIH
  for that particular task/interrupt priority group

Change-Id: I8357518b02922d3328aff4d80003ac3030fdd5e7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44135
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

22 files changed, 583 insertions, 393 deletions

diff --git a/import/chips/p9/procedures/ppe/iota/iota.c b/import/chips/p9/procedures/ppe/iota/iota.c
index d4c098c0..d5ef2e4d 100644
--- a/import/chips/p9/procedures/ppe/iota/iota.c
+++ b/import/chips/p9/procedures/ppe/iota/iota.c
@@ -25,6 +25,7 @@
 #include "iota.h"
 #include "iota_uih.h"
 #include "iota_ppe42.h"
+#include "iota_panic_codes.h"
 
 // Force all kernel variables into .sdata
 // Order controlled by linker script
@@ -56,7 +57,7 @@ void _iota_evaluate_idle_tasks()
             if(g_iota_idle_task_list[idle_task_idx].function == IOTA_NO_TASK)
             {
                 // Tried to execute a NULLPTR task
-                iota_halt();
+                iota_dead(IOTA_NULLPTR_TASK);
             }
 
             g_iota_idle_task_list[idle_task_idx].function(idle_task_idx, 0);
@@ -137,29 +138,30 @@ void _iota_schedule(uint32_t schedule_reason)
     }
     else
     {
-        iota_halt();
+        iota_dead(IOTA_MACHINE_STATE_STACK_OVERFLOW);
     }
 
-    // call appropriate interrupt handler here
-    uint32_t task_idx;
-
+    // Call appropriate interrupt handler here
     switch(schedule_reason)
     {
         case _IOTA_SCHEDULE_REASON_EXT:
-
-            task_idx = iota_uih();
+            // Need semicolon since a label can only be followed by a statement
+            // and not a declaration
+            ;
+            uint32_t task_idx = iota_uih();
 
             if(g_iota_task_list[task_idx] != IOTA_NO_TASK)
             {
-                //uint32_t ctx = mfmsr();
                 uint32_t irq = cntlz64(g_ext_irq_vector);
                 mtmsr(IOTA_DEFAULT_MSR);
                 g_iota_task_list[task_idx](task_idx, irq);
-                //mtmsr(ctx);
+                // Interrupts are disabled once the task returns
+                wrteei(0);
+                iota_uih_restore();
             }
             else
             {
-                iota_halt();
+                iota_dead(IOTA_NULLPTR_TASK);
             }
 
             break;
@@ -173,17 +175,13 @@ void _iota_schedule(uint32_t schedule_reason)
             break;
     }
 
-    wrteei(0);
-
     // Check for idle tasks here
     // Rationale: if the g_iota_curr_machine_state_ptr ==
-    //            &g_iota_curr_machine_state_ptr[0],
+    //            g_iota_machine_state_stack,
     //            then all interrupt tasks must be completed since this is the
     //            last context about to be restored, which means enabled idle
     //            tasks can be executed
-    iotaMachineState* p = g_iota_curr_machine_state_ptr;
-
-    if(--p == g_iota_machine_state_stack)
+    if(g_iota_curr_machine_state_ptr - 1 == g_iota_machine_state_stack)
     {
         uint32_t ctx = mfmsr();
         wrteei(1);
@@ -198,7 +196,7 @@ void _iota_schedule(uint32_t schedule_reason)
     }
     else
     {
-        iota_halt();
+        iota_dead(IOTA_MACHINE_STATE_STACK_UNDERFLOW);
     }
 }
 
diff --git a/import/chips/p9/procedures/ppe/iota/iota.h b/import/chips/p9/procedures/ppe/iota/iota.h
index d68c0141..8d88c548 100644
--- a/import/chips/p9/procedures/ppe/iota/iota.h
+++ b/import/chips/p9/procedures/ppe/iota/iota.h
@@ -40,6 +40,7 @@
 void iota_run()  __attribute__((noreturn));
 
 #define iota_halt() __iota_halt()
+#define iota_dead(code) PK_PANIC((code))
 
 /**
  * Set the state of an idle task
@@ -141,6 +142,7 @@ void iota_set_idle_task_state(uint32_t state, uint32_t idle_task_idx);
         IOTA_32U_ARR_INIT, \
         IOTA_32U_ARR_INIT, \
         IOTA_32U_ARR_INIT, \
+        IOTA_32U_ARR_INIT, \
         IOTA_32U_ARR_INIT \
     }
 ///
@@ -191,7 +193,7 @@ void _iota_schedule(uint32_t schedule_reason);
 void _iota_evaluate_idle_tasks();
 
 extern void __iota_halt() __attribute__((noreturn));
-extern void iota_uih_irq_vec_restore();
+extern void iota_uih_restore();
 
 extern iotaTimerFuncPtr g_iota_dec_handler;
 extern iotaTimerFuncPtr g_iota_fit_handler;
diff --git a/import/chips/p9/procedures/ppe/iota/iota_panic_codes.h b/import/chips/p9/procedures/ppe/iota/iota_panic_codes.h
new file mode 100644
index 00000000..bf23b4b1
--- /dev/null
+++ b/import/chips/p9/procedures/ppe/iota/iota_panic_codes.h
@@ -0,0 +1,260 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/iota/iota_panic_codes.h $      */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2016,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __IOTA_PANIC_CODES_H__
+#define __IOTA_PANIC_CODES_H__
+
+// On PPE42, PANIC codes are stored as part of the trap word instruction.
+// tw 31, RA, RB  Where RA and RB would used to encode the trap code.
+// There are 16 valid gprs on PP42, so this gives 256 possible trap codes.
+// The trap code is defined as a two byte code defined as 0xYYZZ where YY
+// is encoded into the RA field and ZZ is incoded into the RB field
+// YY and ZZ are limited to the values:
+//   00,01,02,03,04,05,06,07,08,09,0a,0d,1c,1d,1e,1f (valid gpr ids)
+//
+// To add a new panic code, select an unused values and rename it.
+// This enum contains all the valid values that can be used. Using a
+// panic code not in this list will result in a compiler/assembler error.
+#ifndef __ASSEMBLER__
+
+typedef enum
+{
+    IOTA_UNUSED_0000 = 0x0000,
+    IOTA_NULLPTR_TASK = 0x0001,
+    IOTA_MACHINE_STATE_STACK_OVERFLOW = 0x0002,
+    IOTA_MACHINE_STATE_STACK_UNDERFLOW = 0x0003,
+    IOTA_UNUSED_0004 = 0x0004,
+    IOTA_UNUSED_0005 = 0x0005,
+    IOTA_UNUSED_0006 = 0x0006,
+    IOTA_UNUSED_0007 = 0x0007,
+    IOTA_UNUSED_0008 = 0x0008,
+    IOTA_UNUSED_0009 = 0x0009,
+    IOTA_UNUSED_000a = 0x000a,
+    IOTA_UNUSED_000d = 0x000d,
+    IOTA_UNUSED_001c = 0x001c,
+    IOTA_UNUSED_001d = 0x001d,
+    IOTA_UNUSED_001e = 0x001e,
+    IOTA_UNUSED_001f = 0x001f,
+
+
+    IOTA_UIH_DISABLED_FIRED = 0x0100,
+    IOTA_UIH_STACK_OVERFLOW = 0x0101,
+    IOTA_UIH_STACK_UNDERFLOW = 0x0102,
+    IOTA_UIH_PHANTOM_INTERRUPT = 0x0103,
+    IOTA_UNUSED_0104 = 0x0104,
+    IOTA_UNUSED_0105 = 0x0105,
+    IOTA_UNUSED_0106 = 0x0106,
+    IOTA_UNUSED_0107 = 0x0107,
+    IOTA_UNUSED_0108 = 0x0108,
+    IOTA_UNUSED_0109 = 0x0109,
+    IOTA_UNUSED_010a = 0x010a,
+    IOTA_UNUSED_010d = 0x010d,
+    IOTA_UNUSED_011c = 0x011c,
+    IOTA_UNUSED_011d = 0x011d,
+    IOTA_UNUSED_011e = 0x011e,
+    IOTA_UNUSED_011f = 0x011f,
+
+
+    IOTA_UNUSED_0200 = 0x0200,
+    IOTA_UNUSED_0201 = 0x0201,
+    IOTA_UNUSED_0202 = 0x0202,
+    IOTA_UNUSED_0203 = 0x0203,
+    IOTA_UNUSED_0204 = 0x0204,
+    IOTA_UNUSED_0205 = 0x0205,
+    IOTA_UNUSED_0206 = 0x0206,
+    IOTA_UNUSED_0207 = 0x0207,
+    IOTA_UNUSED_0208 = 0x0208,
+    IOTA_UNUSED_0209 = 0x0209,
+    IOTA_UNUSED_020a = 0x020a,
+    IOTA_UNUSED_020d = 0x020d,
+    IOTA_UNUSED_021c = 0x021c,
+    IOTA_UNUSED_021d = 0x021d,
+    IOTA_UNUSED_021e = 0x021e,
+    IOTA_UNUSED_021f = 0x021f,
+
+
+    IOTA_UNUSED_0300 = 0x0300,
+    IOTA_UNUSED_0301 = 0x0301,
+    IOTA_UNUSED_0302 = 0x0302,
+    IOTA_UNUSED_0303 = 0x0303,
+    IOTA_UNUSED_0304 = 0x0304,
+    IOTA_UNUSED_0305 = 0x0305,
+    IOTA_UNUSED_0306 = 0x0306,
+    IOTA_UNUSED_0307 = 0x0307,
+    IOTA_UNUSED_0308 = 0x0308,
+    IOTA_UNUSED_0309 = 0x0309,
+    IOTA_UNUSED_030a = 0x030a,
+    IOTA_UNUSED_030d = 0x030d,
+    IOTA_UNUSED_031c = 0x031c,
+    IOTA_UNUSED_031d = 0x031d,
+    IOTA_UNUSED_031e = 0x031e,
+    IOTA_UNUSED_031f = 0x031f,
+
+
+    IOTA_UNUSED_0400 = 0x0400,
+    IOTA_UNUSED_0401 = 0x0401,
+    IOTA_UNUSED_0402 = 0x0402,
+    IOTA_UNUSED_0403 = 0x0403,
+    IOTA_UNUSED_0404 = 0x0404,
+    IOTA_UNUSED_0405 = 0x0405,
+    IOTA_UNUSED_0406 = 0x0406,
+    IOTA_UNUSED_0407 = 0x0407,
+    IOTA_UNUSED_0408 = 0x0408,
+    IOTA_UNUSED_0409 = 0x0409,
+    IOTA_UNUSED_040a = 0x040a,
+    IOTA_UNUSED_040d = 0x040d,
+    IOTA_UNUSED_041c = 0x041c,
+    IOTA_UNUSED_041d = 0x041d,
+    IOTA_UNUSED_041e = 0x041e,
+    IOTA_UNUSED_041f = 0x041f,
+
+
+    IOTA_UNUSED_0500 = 0x0500,
+    IOTA_UNUSED_0501 = 0x0501,
+    IOTA_UNUSED_0502 = 0x0502,
+    IOTA_UNUSED_0503 = 0x0503,
+    IOTA_UNUSED_0504 = 0x0504,
+    IOTA_UNUSED_0505 = 0x0505,
+    IOTA_UNUSED_0506 = 0x0506,
+    IOTA_UNUSED_0507 = 0x0507,
+    IOTA_UNUSED_0508 = 0x0508,
+    IOTA_UNUSED_0509 = 0x0509,
+    IOTA_UNUSED_050a = 0x050a,
+    IOTA_UNUSED_050d = 0x050d,
+    IOTA_UNUSED_051c = 0x051c,
+    IOTA_UNUSED_051d = 0x051d,
+    IOTA_UNUSED_051e = 0x051e,
+    IOTA_UNUSED_051f = 0x051f,
+
+
+    IOTA_UNUSED_0600 = 0x0600,
+    IOTA_UNUSED_0601 = 0x0601,
+    IOTA_UNUSED_0602 = 0x0602,
+    IOTA_UNUSED_0603 = 0x0603,
+    IOTA_UNUSED_0604 = 0x0604,
+    IOTA_UNUSED_0605 = 0x0605,
+    IOTA_UNUSED_0606 = 0x0606,
+    IOTA_UNUSED_0607 = 0x0607,
+    IOTA_UNUSED_0608 = 0x0608,
+    IOTA_UNUSED_0609 = 0x0609,
+    IOTA_UNUSED_060a = 0x060a,
+    IOTA_UNUSED_060d = 0x060d,
+    IOTA_UNUSED_061c = 0x061c,
+    IOTA_UNUSED_061d = 0x061d,
+    IOTA_UNUSED_061e = 0x061e,
+    IOTA_UNUSED_061f = 0x061f,
+
+
+    IOTA_UNUSED_0700 = 0x0700,
+    IOTA_UNUSED_0701 = 0x0701,
+    IOTA_UNUSED_0702 = 0x0702,
+    IOTA_UNUSED_0703 = 0x0703,
+    IOTA_UNUSED_0704 = 0x0704,
+    IOTA_UNUSED_0705 = 0x0705,
+    IOTA_UNUSED_0706 = 0x0706,
+    IOTA_UNUSED_0707 = 0x0707,
+    IOTA_UNUSED_0708 = 0x0708,
+    IOTA_UNUSED_0709 = 0x0709,
+    IOTA_UNUSED_070a = 0x070a,
+    IOTA_UNUSED_070d = 0x070d,
+    IOTA_UNUSED_071c = 0x071c,
+    IOTA_UNUSED_071d = 0x071d,
+    IOTA_UNUSED_071e = 0x071e,
+    IOTA_UNUSED_071f = 0x071f,
+
+
+    IOTA_UNUSED_0800 = 0x0800,
+    IOTA_UNUSED_0801 = 0x0801,
+    IOTA_UNUSED_0802 = 0x0802,
+    IOTA_UNUSED_0803 = 0x0803,
+    IOTA_UNUSED_0804 = 0x0804,
+    IOTA_UNUSED_0805 = 0x0805,
+    IOTA_UNUSED_0806 = 0x0806,
+    IOTA_UNUSED_0807 = 0x0807,
+    IOTA_UNUSED_0808 = 0x0808,
+    IOTA_UNUSED_0809 = 0x0809,
+    IOTA_UNUSED_080a = 0x080a,
+    IOTA_UNUSED_080d = 0x080d,
+    IOTA_UNUSED_081c = 0x081c,
+    IOTA_UNUSED_081d = 0x081d,
+    IOTA_UNUSED_081e = 0x081e,
+    IOTA_UNUSED_081f = 0x081f,
+
+
+    IOTA_UNUSED_0900 = 0x0900,
+    IOTA_UNUSED_0901 = 0x0901,
+    IOTA_UNUSED_0902 = 0x0902,
+    IOTA_UNUSED_0903 = 0x0903,
+    IOTA_UNUSED_0904 = 0x0904,
+    IOTA_UNUSED_0905 = 0x0905,
+    IOTA_UNUSED_0906 = 0x0906,
+    IOTA_UNUSED_0907 = 0x0907,
+    IOTA_UNUSED_0908 = 0x0908,
+    IOTA_UNUSED_0909 = 0x0909,
+    IOTA_UNUSED_090a = 0x090a,
+    IOTA_UNUSED_090d = 0x090d,
+    IOTA_UNUSED_091c = 0x091c,
+    IOTA_UNUSED_091d = 0x091d,
+    IOTA_UNUSED_091e = 0x091e,
+    IOTA_UNUSED_091f = 0x091f,
+
+
+    IOTA_UNUSED_0a00 = 0x0a00,
+    IOTA_UNUSED_0a01 = 0x0a01,
+    IOTA_UNUSED_0a02 = 0x0a02,
+    IOTA_UNUSED_0a03 = 0x0a03,
+    IOTA_UNUSED_0a04 = 0x0a04,
+    IOTA_UNUSED_0a05 = 0x0a05,
+    IOTA_UNUSED_0a06 = 0x0a06,
+    IOTA_UNUSED_0a07 = 0x0a07,
+    IOTA_UNUSED_0a08 = 0x0a08,
+    IOTA_UNUSED_0a09 = 0x0a09,
+    IOTA_UNUSED_0a0a = 0x0a0a,
+    IOTA_UNUSED_0a0d = 0x0a0d,
+    IOTA_UNUSED_0a1c = 0x0a1c,
+    IOTA_UNUSED_0a1d = 0x0a1d,
+    IOTA_UNUSED_0a1e = 0x0a1e,
+    IOTA_UNUSED_0a1f = 0x0a1f,
+
+
+    IOTA_UNUSED_0d00 = 0x0d00,
+    IOTA_UNUSED_0d01 = 0x0d01,
+    IOTA_UNUSED_0d02 = 0x0d02,
+    IOTA_UNUSED_0d03 = 0x0d03,
+    IOTA_UNUSED_0d04 = 0x0d04,
+    IOTA_UNUSED_0d05 = 0x0d05,
+    IOTA_UNUSED_0d06 = 0x0d06,
+    IOTA_UNUSED_0d07 = 0x0d07,
+    IOTA_UNUSED_0d08 = 0x0d08,
+    IOTA_UNUSED_0d09 = 0x0d09,
+    IOTA_UNUSED_0d0a = 0x0d0a,
+    IOTA_UNUSED_0d0d = 0x0d0d,
+    IOTA_UNUSED_0d1c = 0x0d1c,
+    IOTA_UNUSED_0d1d = 0x0d1d,
+    IOTA_UNUSED_0d1e = 0x0d1e,
+    IOTA_UNUSED_0d1f = 0x0d1f
+} iotaPanicCode_t;
+
+#endif  // __ASSEMBLER__
+#endif
diff --git a/import/chips/p9/procedures/ppe/iota/iota_ppe42.h b/import/chips/p9/procedures/ppe/iota/iota_ppe42.h
index 8dcbc787..2779962f 100644
--- a/import/chips/p9/procedures/ppe/iota/iota_ppe42.h
+++ b/import/chips/p9/procedures/ppe/iota/iota_ppe42.h
@@ -55,6 +55,7 @@
 #define _IOTA_SAVE_R3_OFFSET   64
 #define _IOTA_SAVE_R10_OFFSET  68
 #define _IOTA_SAVE_CTR_OFFSET  72
+#define _IOTA_SAVE_PADDING_OFFSET 76
 
 #define _IOTA_TEMPORARY_R3_STACK_OFFSET -4
 
diff --git a/import/chips/p9/procedures/ppe/iota/iota_uih.c b/import/chips/p9/procedures/ppe/iota/iota_uih.c
index 62afce93..546def67 100644
--- a/import/chips/p9/procedures/ppe/iota/iota_uih.c
+++ b/import/chips/p9/procedures/ppe/iota/iota_uih.c
@@ -24,151 +24,7 @@
 /* IBM_PROLOG_END_TAG                                                     */
 #include "iota.h"
 #include "iota_uih.h"
-
-// Notes:
-//   The following two lists,
-//     ext_irq_vectors_cme[][] and IDX_PRTY_LVL_<task_abbr>, must match.
-//   IDX_PRTY_LVL_<task_abbr> is the tasks priority level and serves
-//   as the index into the ext_irq_vectors_cme[][] table.
-
-const uint64_t ext_irq_vectors_cme[IOTA_NUM_EXT_IRQ_PRIORITIES][2] =
-{
-    /* 0: IDX_PRTY_VEC    1: IDX_MASK_VEC */
-    {
-        IRQ_VEC_PRTY0_CME, /* 0: IDX_PRTY_LVL_HIPRTY */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME |
-        IRQ_VEC_PRTY7_CME |
-        IRQ_VEC_PRTY6_CME |
-        IRQ_VEC_PRTY5_CME |
-        IRQ_VEC_PRTY4_CME |
-        IRQ_VEC_PRTY3_CME |
-        IRQ_VEC_PRTY2_CME |
-        IRQ_VEC_PRTY1_CME |
-        IRQ_VEC_PRTY0_CME
-    },
-    {
-        IRQ_VEC_PRTY1_CME, /* 1: IDX_PRTY_LVL_DB3 */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME |
-        IRQ_VEC_PRTY7_CME |
-        IRQ_VEC_PRTY6_CME |
-        IRQ_VEC_PRTY5_CME |
-        IRQ_VEC_PRTY4_CME |
-        IRQ_VEC_PRTY3_CME |
-        IRQ_VEC_PRTY2_CME |
-        IRQ_VEC_PRTY1_CME
-    },
-    {
-        IRQ_VEC_PRTY2_CME, /* 2: IDX_PRTY_LVL_DB2 */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME |
-        IRQ_VEC_PRTY7_CME |
-        IRQ_VEC_PRTY6_CME |
-        IRQ_VEC_PRTY5_CME |
-        IRQ_VEC_PRTY4_CME |
-        IRQ_VEC_PRTY3_CME |
-        IRQ_VEC_PRTY2_CME
-    },
-    {
-        IRQ_VEC_PRTY3_CME, /* 3: IDX_PRTY_LVL_SPWU */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME |
-        IRQ_VEC_PRTY7_CME |
-        IRQ_VEC_PRTY6_CME |
-        IRQ_VEC_PRTY5_CME |
-        IRQ_VEC_PRTY4_CME |
-        IRQ_VEC_PRTY3_CME
-    },
-    {
-        IRQ_VEC_PRTY4_CME, /* 4: IDX_PRTY_LVL_WAKE */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME |
-        IRQ_VEC_PRTY7_CME |
-        IRQ_VEC_PRTY6_CME |
-        IRQ_VEC_PRTY5_CME |
-        IRQ_VEC_PRTY4_CME
-    },
-    {
-        IRQ_VEC_PRTY5_CME, /* 5: IDX_PRTY_LVL_STOP */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME |
-        IRQ_VEC_PRTY7_CME |
-        IRQ_VEC_PRTY6_CME |
-        IRQ_VEC_PRTY5_CME
-    },
-    {
-        IRQ_VEC_PRTY6_CME, /* 6: IDX_PRTY_LVL_DB1 */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME |
-        IRQ_VEC_PRTY7_CME |
-        IRQ_VEC_PRTY6_CME
-    },
-
-    {
-        IRQ_VEC_PRTY7_CME, /* 7: IDX_PRTY_LVL_DB0 */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME |
-        IRQ_VEC_PRTY7_CME
-    },
-
-    {
-        IRQ_VEC_PRTY8_CME, /* 8: IDX_PRTY_LVL_INTERCME_IN0 */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME |
-        IRQ_VEC_PRTY8_CME
-    },
-    {
-        IRQ_VEC_PRTY9_CME, /* 9: IDX_PRTY_LVL_PMCR */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY9_CME
-    },
-    {
-        IRQ_VEC_PRTY10_CME, /* 10: IDX_PRTY_LVL_DISABLED */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY10_CME
-    },
-    {
-        IRQ_VEC_PRTY11_CME, /* 11: IDX_PRTY_LVL_COMM_RECVD */
-        IRQ_VEC_PRTY12_CME |
-        IRQ_VEC_PRTY11_CME
-    },
-    {
-        IRQ_VEC_PRTY12_CME, /* 12: IDX_PRTY_LVL_DISABLED */
-        IRQ_VEC_PRTY12_CME
-    }
-
-
-};
+#include "iota_panic_codes.h"
 
 uint32_t g_current_prty_level = IOTA_NUM_EXT_IRQ_PRIORITIES - 1;
 uint8_t  g_eimr_stack[IOTA_NUM_EXT_IRQ_PRIORITIES];
@@ -188,6 +44,11 @@ uint32_t iota_uih(void)
     // 1. Identify the priority level of the interrupt.
     g_ext_irq_vector = in64(CME_LCL_EISTR);
 
+    if(g_ext_irq_vector == 0)
+    {
+        iota_dead(IOTA_UIH_PHANTOM_INTERRUPT);
+    }
+
     do
     {
         if(ext_irq_vectors_cme[iPrtyLvl][IDX_PRTY_VEC] & g_ext_irq_vector)
@@ -217,8 +78,7 @@ uint32_t iota_uih(void)
         }
         else
         {
-            asm volatile("mtspr 0x110, %0" : : "r" (0xdead));
-            iota_halt();
+            iota_dead(IOTA_UIH_STACK_OVERFLOW);
         }
 
         // 3. Write the new mask for this priority level.
@@ -228,20 +88,16 @@ uint32_t iota_uih(void)
     }
     else
     {
-        asm volatile("mtspr 0x110, %0" : : "r" (0xbeef));
         // Disabled IRQ fired
-        iota_halt();
+        iota_dead(IOTA_UIH_DISABLED_FIRED);
     }
 
     // Return the priority level
     return iPrtyLvl;
 }
 
-void iota_uih_irq_vec_restore()
+void iota_uih_restore()
 {
-    uint32_t ctx = mfmsr();
-    wrteei(0);
-
     if (g_eimr_stack_ctr >= 0)
     {
         out64(CME_LCL_EIMR,
@@ -256,8 +112,6 @@ void iota_uih_irq_vec_restore()
     }
     else
     {
-        iota_halt();
+        iota_dead(IOTA_UIH_STACK_UNDERFLOW);
     }
-
-    mtmsr(ctx);
 }
diff --git a/import/chips/p9/procedures/ppe/iota/iota_uih.h b/import/chips/p9/procedures/ppe/iota/iota_uih.h
index 5fe86457..309c8b99 100644
--- a/import/chips/p9/procedures/ppe/iota/iota_uih.h
+++ b/import/chips/p9/procedures/ppe/iota/iota_uih.h
@@ -46,6 +46,7 @@ extern uint32_t iota_uih(void);
 extern void __hwmacro_setup(void);
 
 extern uint64_t g_ext_irq_vector;
+extern const uint64_t ext_irq_vectors_cme[IOTA_NUM_EXT_IRQ_PRIORITIES][2];
 
 // Needed by ppehw_common.h
 #define PK_IRQ_POLARITY_ACTIVE_LOW  0
@@ -107,11 +108,10 @@ extern const uint64_t ext_irq_vectors_cme[IOTA_NUM_EXT_IRQ_PRIORITIES][2];
                               IRQ_VEC_PRTY8_CME | \
                               IRQ_VEC_PRTY9_CME | \
                               IRQ_VEC_PRTY10_CME )
-
+#endif
 extern uint32_t g_current_prty_level;
 extern uint8_t  g_eimr_stack[IOTA_NUM_EXT_IRQ_PRIORITIES] SECTION_SBSS;
 extern int      g_eimr_stack_ctr;
 extern uint64_t g_eimr_override_stack[IOTA_NUM_EXT_IRQ_PRIORITIES]SECTION_SBSS;
 extern uint64_t g_eimr_override;
-#endif
 #endif //__IOTA_UIH_H__
diff --git a/import/chips/p9/procedures/ppe/iota/pk.h b/import/chips/p9/procedures/ppe/iota/pk.h
index 296813f1..3e0741a4 100644
--- a/import/chips/p9/procedures/ppe/iota/pk.h
+++ b/import/chips/p9/procedures/ppe/iota/pk.h
@@ -48,7 +48,7 @@ typedef uint64_t PkTimebase;
 extern uint64_t pk_timebase_get();
 
 #define pk_halt() iota_halt()
-#define pk_irq_vec_restore(...) iota_uih_irq_vec_restore()
+#define pk_irq_vec_restore(...)
 
 // This sets the SPRG0 in pk.
 static inline void ppe42_app_ctx_set(uint16_t app_ctx)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_common.mk b/import/chips/p9/procedures/ppe_closed/cme/cme_common.mk
index 5eb1624b..e29a5954 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_common.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_common.mk
@@ -54,6 +54,7 @@ CME_OBJS += ppe42_gcc.o
 CME_OBJS += ppe42_string.o
 CME_OBJS += p9_cme_iota_main.o
 CME_OBJS += std_init.o
+CME_OBJS += p9_cme_irq_priority_table.o
 
 # Add source code directories for the above objects
 $(call ADD_PPEIMAGE_SRCDIR,$(IMAGE),$(IOTA_SRCDIR))
@@ -175,60 +176,60 @@ CME_COMMONFLAGS:=
 ifeq "__PK__" "$($(IMAGE)_KERNEL)"
 # Options for PK_TRACE
 #CME_COMMONFLAGS+= -DPK_TRACE_LEVEL=0
-CME_COMMONFLAGS+= -DPK_TRACE_TIMER_OUTPUT=0
-CME_COMMONFLAGS+= -DDEV_DEBUG=0
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_TIMER_OUTPUT=0
+$(IMAGE)_COMMONFLAGS+= -DDEV_DEBUG=0
 
 # Options for Kernel configuration
 
 # Force CME tasks to use the unified interrupt handler
-CME_COMMONFLAGS+= -DUNIFIED_IRQ_HANDLER_CME
+$(IMAGE)_COMMONFLAGS+= -DUNIFIED_IRQ_HANDLER_CME
 
 # This application will statically initialize
 # it's external interrupt table using
 # the table defined in p9_cme_main.c
-CME_COMMONFLAGS+= -DSTATIC_IRQ_TABLE
+$(IMAGE)_COMMONFLAGS+= -DSTATIC_IRQ_TABLE
 
 # This application will use the external timebase register
 # (comment this line out to use the decrementer as timebase)
-CME_COMMONFLAGS+= -DAPPCFG_USE_EXT_TIMEBASE
+$(IMAGE)_COMMONFLAGS+= -DAPPCFG_USE_EXT_TIMEBASE
 
-CME_COMMONFLAGS+= -DPK_TIMER_SUPPORT=1
-CME_COMMONFLAGS+= -DPK_THREAD_SUPPORT=1
-CME_COMMONFLAGS+= -DPK_TRACE_SUPPORT=1
-CME_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
-CME_COMMONFLAGS+= -D__PK__=1
+$(IMAGE)_COMMONFLAGS+= -DPK_TIMER_SUPPORT=1
+$(IMAGE)_COMMONFLAGS+= -DPK_THREAD_SUPPORT=1
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SUPPORT=1
+$(IMAGE)_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
+$(IMAGE)_COMMONFLAGS+= -D__PK__=1
 else
 #__IOTA__
-CME_COMMONFLAGS+= -DPK_TRACE_SUPPORT=1
-CME_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
-CME_COMMONFLAGS+= -DPK_TIMER_SUPPORT=0
-CME_COMMONFLAGS+= -D__IOTA__
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SUPPORT=1
+$(IMAGE)_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
+$(IMAGE)_COMMONFLAGS+= -DPK_TIMER_SUPPORT=0
+$(IMAGE)_COMMONFLAGS+= -D__IOTA__
 #__IOTA__
 endif
 
 ## Common to both __PK__ and __IOTA__
-CME_COMMONFLAGS+= -D__PPE_PLAT
-CME_COMMONFLAGS+= -D__PPE_CME
+$(IMAGE)_COMMONFLAGS+= -D__PPE_PLAT
+$(IMAGE)_COMMONFLAGS+= -D__PPE_CME
 # Options for Functions being skipped
 
-CME_COMMONFLAGS+= -DSPWU_AUTO=0
-CME_COMMONFLAGS+= -DSTOP_PRIME=0
+$(IMAGE)_COMMONFLAGS+= -DSPWU_AUTO=0
+$(IMAGE)_COMMONFLAGS+= -DSTOP_PRIME=0
 
-CME_COMMONFLAGS+= -DSKIP_ABORT=0
-CME_COMMONFLAGS+= -DSKIP_L2_PURGE_ABORT=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_ABORT=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_L2_PURGE_ABORT=0
 
-CME_COMMONFLAGS+= -DSKIP_ENTRY_CATCHUP=0
-CME_COMMONFLAGS+= -DSKIP_EXIT_CATCHUP=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_ENTRY_CATCHUP=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_EXIT_CATCHUP=0
 
-CME_COMMONFLAGS+= -DSKIP_ARRAYINIT=0
-CME_COMMONFLAGS+= -DSKIP_SCAN0=0
-CME_COMMONFLAGS+= -DSKIP_INITF=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_ARRAYINIT=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_SCAN0=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_INITF=0
 
-CME_COMMONFLAGS+= -DSKIP_SELF_RESTORE=0
-CME_COMMONFLAGS+= -DSKIP_RAM_HRMOR=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_SELF_RESTORE=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_RAM_HRMOR=0
 
-CME_COMMONFLAGS+= -DSKIP_BCE_SCAN_RING=0
-CME_COMMONFLAGS+= -DSKIP_BCE_SCOM_RESTORE=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_BCE_SCAN_RING=0
+$(IMAGE)_COMMONFLAGS+= -DSKIP_BCE_SCOM_RESTORE=0
 
 ## end ifdef IMAGE
 endif
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_p9c10.mk b/import/chips/p9/procedures/ppe_closed/cme/cme_p9c10.mk
index 93ef1892..7a17a462 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_p9c10.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_p9c10.mk
@@ -27,14 +27,15 @@ CME_TARGET := cme_p9c10
 IMAGE := $(CME_TARGET)
 
 #Select KERNEL
-#$(IMAGE)_KERNEL:=__IOTA__
-$(IMAGE)_KERNEL:=__PK__
+$(IMAGE)_KERNEL:=__IOTA__
+#$(IMAGE)_KERNEL:=__PK__
 
 # Options for Platforms specific
-$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=0
 $(IMAGE)_COMMONFLAGS = -DNIMBUS_DD_LEVEL=0
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=10
 
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=0
+
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_BROADSIDE_SCAN0=0
@@ -43,7 +44,6 @@ $(IMAGE)_COMMONFLAGS+= -DSIMICS_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DUSE_SIMICS_IO=0
 
 include $(CME_SRCDIR)/cme_common.mk
-$(IMAGE)_COMMONFLAGS+=$(CME_COMMONFLAGS)
 OBJS := $(CME_OBJS)
 
 $(call BUILD_PPEIMAGE)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n10.mk b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n10.mk
index 2e5bbb84..d0486f98 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n10.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n10.mk
@@ -27,16 +27,15 @@ CME_TARGET := cme_p9n10
 IMAGE:=$(CME_TARGET)
 
 #Select KERNEL
-#$(IMAGE)_KERNEL:=__IOTA__
-$(IMAGE)_KERNEL:=__PK__
+$(IMAGE)_KERNEL:=__IOTA__
+#(IMAGE)_KERNEL:=__PK__
 
 # Options for Platforms specific DD lvl
-
-$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=0
-
 $(IMAGE)_COMMONFLAGS = -DNIMBUS_DD_LEVEL=10
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=0
+
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_BROADSIDE_SCAN0=0
@@ -45,7 +44,6 @@ $(IMAGE)_COMMONFLAGS+= -DSIMICS_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DUSE_SIMICS_IO=0
 
 include $(CME_SRCDIR)/cme_common.mk
-$(IMAGE)_COMMONFLAGS+=$(CME_COMMONFLAGS)
 OBJS := $(CME_OBJS)
 
 $(call BUILD_PPEIMAGE)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n20.mk b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n20.mk
index 1d39bf24..2b067530 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n20.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n20.mk
@@ -27,24 +27,23 @@ CME_IMAGE:=cme_p9n20
 IMAGE:=$(CME_IMAGE)
 
 #Select KERNEL
-#$(IMAGE)_KERNEL:=__IOTA__
-$(IMAGE)_KERNEL:=__PK__
+$(IMAGE)_KERNEL:=__IOTA__
+#$(IMAGE)_KERNEL:=__PK__
 
 # Options for Platforms specific tuning
-
-$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=0
-
-$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=20
+$(IMAGE)_COMMONFLAGS = -DNIMBUS_DD_LEVEL=20
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=2
+
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_BROADSIDE_SCAN0=0
+
 $(IMAGE)_COMMONFLAGS+= -DSIMICS_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DUSE_SIMICS_IO=0
 
 include $(CME_SRCDIR)/cme_common.mk
-$(IMAGE)_COMMONFLAGS+=$(CME_COMMONFLAGS)
 OBJS := $(CME_OBJS)
 
 $(call BUILD_PPEIMAGE)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n21.mk b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n21.mk
index a339063e..0109aac8 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n21.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n21.mk
@@ -28,24 +28,25 @@ IMAGE:=$(CME_IMAGE)
 IMAGE_EDITOR:=cmeImgEdit.exe
 
 #Select KERNEL
-#$(IMAGE)_KERNEL:=__IOTA__
-$(IMAGE)_KERNEL:=__PK__
+$(IMAGE)_KERNEL:=__IOTA__
+#$(IMAGE)_KERNEL:=__PK__
 
 # Options for Platforms specific tuning
 
-$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=2
 
-$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=21
+$(IMAGE)_COMMONFLAGS = -DNIMBUS_DD_LEVEL=21
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=2
+
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_BROADSIDE_SCAN0=0
+
 $(IMAGE)_COMMONFLAGS+= -DSIMICS_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DUSE_SIMICS_IO=0
 
 include $(CME_SRCDIR)/cme_common.mk
-$(IMAGE)_COMMONFLAGS+=$(CME_COMMONFLAGS)
 OBJS := $(CME_OBJS)
 
 $(call BUILD_PPEIMAGE)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/iota_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/iota_app_cfg.h
index ddb26a07..d7bab97c 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/iota_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/iota_app_cfg.h
@@ -46,7 +46,7 @@
 #endif
 
 // Maximum number of expected nested interrupts
-#define IOTA_MAX_NESTED_INTERRUPTS    4
+#define IOTA_MAX_NESTED_INTERRUPTS    12
 
 //An "idle" task is one that only runs when the ppe42 engine would otherwise
 //be idle and thus has the lowest priority and can be interrupted by anything.
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c
index c22c07b3..dcc02b25 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c
@@ -42,148 +42,6 @@
 //            DO NOT modify this file unless you're the owner        //
 //-------------------------------------------------------------------//
 
-// Notes:
-//   The following two lists,
-//     ext_irq_vectors_cme[][] and IDX_PRTY_LVL_<task_abbr>, must match.
-//   IDX_PRTY_LVL_<task_abbr> is the tasks priority level and serves
-//   as the index into the ext_irq_vectors_cme[][] table.
-
-const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2] =
-{
-    /* 0: IDX_PRTY_VEC    1: IDX_MASK_VEC */
-    {
-        IRQ_VEC_PRTY0_CME, /* 0: IDX_PRTY_LVL_HIPRTY */
-        IRQ_VEC_PRTY0_CME  |
-        IRQ_VEC_PRTY1_CME  |
-        IRQ_VEC_PRTY2_CME  |
-        IRQ_VEC_PRTY3_CME  |
-        IRQ_VEC_PRTY4_CME  |
-        IRQ_VEC_PRTY5_CME  |
-        IRQ_VEC_PRTY6_CME  |
-        IRQ_VEC_PRTY7_CME  |
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY1_CME, /* 1: IDX_PRTY_LVL_DB3 */
-        IRQ_VEC_PRTY1_CME  |
-        IRQ_VEC_PRTY2_CME  |
-        IRQ_VEC_PRTY3_CME  |
-        IRQ_VEC_PRTY4_CME  |
-        IRQ_VEC_PRTY5_CME  |
-        IRQ_VEC_PRTY6_CME  |
-        IRQ_VEC_PRTY7_CME  |
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY2_CME, /* 2: IDX_PRTY_LVL_DB2 */
-        IRQ_VEC_PRTY2_CME  |
-        IRQ_VEC_PRTY3_CME  |
-        IRQ_VEC_PRTY4_CME  |
-        IRQ_VEC_PRTY5_CME  |
-        IRQ_VEC_PRTY6_CME  |
-        IRQ_VEC_PRTY7_CME  |
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY3_CME, /* 3: IDX_PRTY_LVL_SPWU */
-        IRQ_VEC_PRTY3_CME  |
-        IRQ_VEC_PRTY4_CME  |
-        IRQ_VEC_PRTY5_CME  |
-        IRQ_VEC_PRTY6_CME  |
-        IRQ_VEC_PRTY7_CME  |
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY4_CME, /* 4: IDX_PRTY_LVL_RGWU */
-        IRQ_VEC_PRTY4_CME  |
-        IRQ_VEC_PRTY5_CME  |
-        IRQ_VEC_PRTY6_CME  |
-        IRQ_VEC_PRTY7_CME  |
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY5_CME, /* 5: IDX_PRTY_LVL_PCWU */
-        IRQ_VEC_PRTY5_CME  |
-        IRQ_VEC_PRTY6_CME  |
-        IRQ_VEC_PRTY7_CME  |
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY6_CME, /* 6: IDX_PRTY_LVL_PM_ACTIVE */
-        IRQ_VEC_PRTY6_CME  |
-        IRQ_VEC_PRTY7_CME  |
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY7_CME, /* 7: IDX_PRTY_LVL_DB1 */
-        IRQ_VEC_PRTY7_CME  |
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY8_CME, /* 8: IDX_PRTY_LVL_DB0 */
-        IRQ_VEC_PRTY8_CME  |
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY9_CME, /* 9: IDX_PRTY_LVL_INTERCME_IN0 */
-        IRQ_VEC_PRTY9_CME  |
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY10_CME, /* 10: IDX_PRTY_LVL_PMCR */
-        IRQ_VEC_PRTY10_CME |
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY11_CME, /* 11: IDX_PRTY_LVL_COMM_RECVD */
-        IRQ_VEC_PRTY11_CME |
-        IRQ_VEC_PRTY12_CME
-    },
-    {
-        IRQ_VEC_PRTY12_CME, /* 12: IDX_PRTY_LVL_DISABLED */
-        IRQ_VEC_PRTY12_CME
-    }
-
-};
-
 uint32_t      g_current_prty_level = NUM_EXT_IRQ_PRTY_LEVELS - 1;
 uint8_t       g_eimr_stack[NUM_EXT_IRQ_PRTY_LEVELS];
 int           g_eimr_stack_ctr = -1;
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h
index 45e88596..74fdbbe2 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h
@@ -47,6 +47,9 @@
 //   definitions in cme_irq_common.c
 
 #include <stdint.h>
+#if !defined(__IOTA__)
+    #include "pk.h"
+#endif
 
 // Priority Levels
 #define IDX_PRTY_LVL_HIPRTY         0
@@ -65,7 +68,6 @@
 #define IDX_PRTY_VEC                0
 #define IDX_MASK_VEC                1
 #define NUM_EXT_IRQ_PRTY_LEVELS     13
-extern const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2];
 
 // Group0: Non-task hi-prty IRQs
 #define IRQ_VEC_PRTY0_CME   (uint64_t)(0xFE00000000000000)
@@ -108,7 +110,8 @@ extern const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2];
                               IRQ_VEC_PRTY10_CME | \
                               IRQ_VEC_PRTY11_CME | \
                               IRQ_VEC_PRTY12_CME )
-
+#if !defined(__IOTA__)
+extern const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2];
 extern uint32_t      g_current_prty_level;
 
 extern uint8_t
@@ -122,7 +125,6 @@ g_eimr_override_stack[NUM_EXT_IRQ_PRTY_LEVELS] __attribute__((section(".sbss")))
 extern uint64_t      g_eimr_override;
 
 /// Restore a vector of interrupts by overwriting EIMR.
-#if !defined(__IOTA__)
 UNLESS__PPE42_IRQ_CORE_C__(extern)
 inline void
 pk_irq_vec_restore(PkMachineContext* context)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c
new file mode 100644
index 00000000..f1824bd6
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c
@@ -0,0 +1,226 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2017                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// Notes:
+//   The following two lists,
+//     ext_irq_vectors_cme[][] and IDX_PRTY_LVL_<task_abbr>, must match.
+//   IDX_PRTY_LVL_<task_abbr> is the tasks priority level and serves
+//   as the index into the ext_irq_vectors_cme[][] table.
+
+#include "p9_cme_irq.h"
+
+#if defined(__IOTA__)
+    #include "iota_app_cfg.h"
+    const uint64_t ext_irq_vectors_cme[IOTA_NUM_EXT_IRQ_PRIORITIES][2] =
+#else
+    const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2] =
+#endif
+{
+    /* 0: IDX_PRTY_VEC    1: IDX_MASK_VEC */
+    {
+        IRQ_VEC_PRTY0_CME, /* 0: IDX_PRTY_LVL_HIPRTY */
+        IRQ_VEC_PRTY0_CME  |
+        IRQ_VEC_PRTY1_CME  |
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME
+    },
+    {
+        IRQ_VEC_PRTY1_CME, /* 1: IDX_PRTY_LVL_DB3 */
+        IRQ_VEC_PRTY1_CME  |
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME
+    },
+    {
+        IRQ_VEC_PRTY2_CME, /* 2: IDX_PRTY_LVL_DB2 */
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME |
+        // For Stop Entry/Exit related priority groups, mask every other SE/SX
+        // related priority group, even higher ones, since the actual procedures
+        // will open up EIMR at specific points in the SE/SX sequence.
+        IRQ_VEC_PRTY1_CME
+    },
+    {
+        IRQ_VEC_PRTY3_CME, /* 3: IDX_PRTY_LVL_SPWU */
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME |
+        // For Stop Entry/Exit related priority groups, mask every other SE/SX
+        // related priority group, even higher ones, since the actual procedures
+        // will open up EIMR at specific points in the SE/SX sequence.
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY1_CME
+    },
+    {
+        IRQ_VEC_PRTY4_CME, /* 4: IDX_PRTY_LVL_RGWU */
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME |
+        // For Stop Entry/Exit related priority groups, mask every other SE/SX
+        // related priority group, even higher ones, since the actual procedures
+        // will open up EIMR at specific points in the SE/SX sequence.
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY1_CME
+    },
+    {
+        IRQ_VEC_PRTY5_CME, /* 5: IDX_PRTY_LVL_PCWU */
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME |
+        // For Stop Entry/Exit related priority groups, mask every other SE/SX
+        // related priority group, even higher ones, since the actual procedures
+        // will open up EIMR at specific points in the SE/SX sequence.
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY1_CME
+    },
+    {
+        IRQ_VEC_PRTY6_CME, /* 6: IDX_PRTY_LVL_PM_ACTIVE */
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME |
+        // For Stop Entry/Exit related priority groups, mask every other SE/SX
+        // related priority group, even higher ones, since the actual procedures
+        // will open up EIMR at specific points in the SE/SX sequence.
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY1_CME
+    },
+    {
+        IRQ_VEC_PRTY7_CME, /* 7: IDX_PRTY_LVL_DB1 */
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME
+    },
+    {
+        IRQ_VEC_PRTY8_CME, /* 8: IDX_PRTY_LVL_DB0 */
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME
+    },
+    {
+        IRQ_VEC_PRTY9_CME, /* 9: IDX_PRTY_LVL_INTERCME_IN0 */
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME |
+        // The entirety of this handler is executed in EE=0 mode on PK, for IOTA
+        // this behavior can ony be emulated by masking all higher priority
+        // interrupts in the UIH
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY1_CME
+    },
+    {
+        IRQ_VEC_PRTY10_CME, /* 10: IDX_PRTY_LVL_PMCR */
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME
+    },
+    {
+        IRQ_VEC_PRTY11_CME, /* 11: IDX_PRTY_LVL_COMM_RECVD */
+        IRQ_VEC_PRTY11_CME |
+        IRQ_VEC_PRTY12_CME |
+        // The entirety of this handler is executed in EE=0 mode on PK, for IOTA
+        // this behavior can ony be emulated by masking all higher priority
+        // interrupts in the UIH
+        IRQ_VEC_PRTY10_CME |
+        IRQ_VEC_PRTY9_CME  |
+        IRQ_VEC_PRTY8_CME  |
+        IRQ_VEC_PRTY7_CME  |
+        IRQ_VEC_PRTY6_CME  |
+        IRQ_VEC_PRTY5_CME  |
+        IRQ_VEC_PRTY4_CME  |
+        IRQ_VEC_PRTY3_CME  |
+        IRQ_VEC_PRTY2_CME  |
+        IRQ_VEC_PRTY1_CME
+
+    },
+    {
+        IRQ_VEC_PRTY12_CME, /* 12: IDX_PRTY_LVL_DISABLED */
+        IRQ_VEC_PRTY12_CME
+    }
+};
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
index 22cec0ce..3467d98b 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
@@ -168,7 +168,7 @@ void p9_cme_pstate_intercme_msg_handler(void* arg, PkIrqId irq)
     intercme_msg_recv(&msg, IMT_LOCK_SIBLING);
 
     // Block on the intercme0 interrupt
-    while(!(in32(CME_LCL_EISR) & BIT32(8))) {}
+    while(!(in32(CME_LCL_EISR) & BIT32(7))) {}
 
     // Restore the mask, cede control to the intercme0 interrupt handler
     pk_irq_vec_restore(&ctx);
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
index dc496ad3..4c8f0b9a 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
@@ -82,11 +82,7 @@ void p9_cme_pstate_db_handler(void* arg, PkIrqId irq)
 {
     PK_TRACE_INF("DB_HDL: Entered\n");
 #if defined(__IOTA__)
-    wrteei(1);
-
     p9_cme_pstate_process_db0();
-
-    iota_uih_irq_vec_restore();
 #else
     pk_semaphore_post((PkSemaphore*)arg);
 #endif
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
index af42303f..aecc8739 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
@@ -53,8 +53,10 @@ uint32_t G_pmcr_cme_flags;
 
 void cme_pstate_pmcr_action()
 {
+    // In IOTA, any task function is executed with EE=1
+#if !defined(__IOTA__)
     wrteei(1);
-
+#endif
     PkMachineContext  ctx __attribute__((unused));
     uint64_t pmcr;
     ppm_pig_t ppmPigData;
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 8362fcbc..5ac2f79d 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -975,7 +975,9 @@ p9_cme_stop_entry()
                   (core << SHIFT32(15)) |
                   (core << SHIFT32(17)));
             sync();
+            wrteei(0);
             out32(CME_LCL_EIMR_OR,  (BITS32(12, 6) | BITS32(20, 2)));
+            wrteei(1);
 #endif
 
             //===================
@@ -1189,7 +1191,9 @@ p9_cme_stop_entry()
                   (core << SHIFT32(15)) |
                   (core << SHIFT32(17)));
             sync();
+            wrteei(0);
             out32(CME_LCL_EIMR_OR,  (BITS32(12, 6) | BITS32(20, 2)));
+            wrteei(1);
 #endif
 
             //===================
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
index b54bb458..c03a7537 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
@@ -79,12 +79,9 @@ p9_cme_stop_pcwu_handler(void* arg, PkIrqId irq)
     {
         out32(CME_LCL_EIMR_OR, BITS32(12, 10));
 #if defined(__IOTA__)
-        wrteei(1);
         p9_cme_stop_exit();
-
         // re-evaluate g_eimr_override then restore eimr
         p9_cme_stop_eval_eimr_override();
-        iota_uih_irq_vec_restore();
 #else
         pk_semaphore_post((PkSemaphore*)arg);
 #endif
@@ -179,12 +176,9 @@ p9_cme_stop_spwu_handler(void* arg, PkIrqId irq)
         out32(CME_LCL_EIMR_OR, BITS32(12, 10));
         PK_TRACE_INF("Launching exit thread");
 #if defined(__IOTA__)
-        wrteei(1);
         p9_cme_stop_exit();
-
         // re-evaluate g_eimr_override then restore eimr
         p9_cme_stop_eval_eimr_override();
-        iota_uih_irq_vec_restore();
 #else
         pk_semaphore_post((PkSemaphore*)arg);
 #endif
@@ -204,12 +198,9 @@ p9_cme_stop_rgwu_handler(void* arg, PkIrqId irq)
     PK_TRACE_INF("RGWU Handler Trigger %d", irq);
     out32(CME_LCL_EIMR_OR, BITS32(12, 10));
 #if defined(__IOTA__)
-    wrteei(1);
     p9_cme_stop_exit();
-
     // re-evaluate g_eimr_override then restore eimr
     p9_cme_stop_eval_eimr_override();
-    iota_uih_irq_vec_restore();
 #else
     pk_semaphore_post((PkSemaphore*)arg);
 #endif
@@ -224,14 +215,10 @@ p9_cme_stop_enter_handler(void* arg, PkIrqId irq)
     PK_TRACE_INF("PM_ACTIVE Handler Trigger %d", irq);
     out32(CME_LCL_EIMR_OR, BITS32(12, 10));
 #if defined(__IOTA__)
-    wrteei(1);
-
     // The actual entry sequence
     p9_cme_stop_entry();
-
     // re-evaluate g_eimr_override then restore eimr
     p9_cme_stop_eval_eimr_override();
-    iota_uih_irq_vec_restore();
 #else
     pk_semaphore_post((PkSemaphore*)arg);
 #endif
diff --git a/import/chips/p9/procedures/ppe_closed/cme/topfiles.mk b/import/chips/p9/procedures/ppe_closed/cme/topfiles.mk
index 94196dc9..cdc5e737 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/topfiles.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/topfiles.mk
@@ -27,6 +27,7 @@ ifdef IMAGE
 
 
 TOP-C-SOURCES    = p9_cme_main.c \
+                   p9_cme_irq_priority_table.c \
                    p9_cme_irq.c 
                    
 UTILS-C-SOURCES  = utils/p9_putringutils.c \