STOP: scominit adding initfile calls

Change-Id: I060917f4350fbb213a01868e54a75bfda6b6bc06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32797
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: ADAM S. HALE <ashale@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

7 files changed, 220 insertions, 31 deletions

diff --git a/import/chips/p9/common/pmlib/include/gpehw_common.h b/import/chips/p9/common/pmlib/include/gpehw_common.h
index 6465983b..baba2484 100644
--- a/import/chips/p9/common/pmlib/include/gpehw_common.h
+++ b/import/chips/p9/common/pmlib/include/gpehw_common.h
@@ -63,9 +63,13 @@ enum GPE_SCOM_ADDRESS_PARAMETERS
     CORE_ADDR_OFFSET            = 0x01000000,
     QUAD_ADDR_BASE              = 0x10000000,
     QUAD_ADDR_OFFSET            = 0x01000000,
-    EX_ADDR_BASE                = 0x10011000,
+    EX_ADDR_BASE                = 0x10010000,
     EX0_ADDR_OFFSET             = 0x00000000,
     EX1_ADDR_OFFSET             = 0x00000400,
+    L2_ADDR_BASE                = 0x10010800,
+    NCU_ADDR_BASE               = 0x10011000,
+    L3_ADDR_BASE                = 0x10011800,
+    L2_TRA_ADDR_BASE            = 0x10012800,
     CME_ADDR_BASE               = 0x10012000,
     CME0_ADDR_OFFSET            = 0x00000000,
     CME1_ADDR_OFFSET            = 0x00000400
@@ -80,13 +84,13 @@ enum GPE_SCOM_ADDRESS_PARAMETERS
     GPE_SCOM_ADDR(addr, CORE_ADDR_BASE, core, 0)
 
 #define GPE_SCOM_ADDR_EX(addr, quad, ex) \
-    GPE_SCOM_ADDR(addr, QUAD_ADDR_BASE|EX_ADDR_BASE, quad, ex)
+    GPE_SCOM_ADDR(addr, EX_ADDR_BASE, quad, ex)
 
 #define GPE_SCOM_ADDR_QUAD(addr, quad) \
     GPE_SCOM_ADDR(addr, QUAD_ADDR_BASE, quad, 0)
 
 #define GPE_SCOM_ADDR_CME(addr, quad, cme) \
-    GPE_SCOM_ADDR(addr, QUAD_ADDR_BASE|CME_ADDR_BASE, quad, cme)
+    GPE_SCOM_ADDR(addr, CME_ADDR_BASE, quad, cme)
 
 #define GPE_GETSCOM(addr, data)   getscom(0, addr, &data);
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
index 12e7e9d9..bb34c751 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
@@ -70,7 +70,11 @@
 #define RAM_MTSPR_PSSCR_GPR0   0x7C17D3A6000000
 
 /// handcoded addresses TO BE REMOVED
+#define CORE_FIRMASK           0x20010A43
+#define CORE_ACTION0           0x20010A46
+#define CORE_ACTION1           0x20010A47
 
+#define C_HANG_CONTROL         0x20010A00
 #define RAS_STATUS             0x20010A02
 #define RAM_MODEREG            0x20010A4E
 #define RAM_CTRL               0x20010A4F
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
index 059c322c..0e7d7cfa 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
@@ -26,6 +26,9 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
+#define CORE_HANG_DIVIDER_4X  0x9F
+#define CORE_HANG_DIVIDER_64X 0x7B
+
 int
 p9_hcd_core_scominit(uint32_t core)
 {
@@ -45,5 +48,18 @@ p9_hcd_core_scominit(uint32_t core)
     scom_data.words.upper |= BITS32(20, 2);// DTS loop1 enable
     CME_PUTSCOM(C_THERM_MODE_REG, core, scom_data.value);
 
+    // content of p9_core_scom
+    PK_TRACE("Initialize FIR MASK/ACT0/ACT1");
+    CME_PUTSCOM(CORE_FIRMASK, core, 0x4301D70000AB7696);
+    CME_PUTSCOM(CORE_ACTION0, core, 0x0000000000000000);
+    CME_PUTSCOM(CORE_ACTION1, core, 0xA858009775100008);
+
+    // update core hang pulse dividers
+    CME_GETSCOM(C_HANG_CONTROL, core, CME_SCOM_AND, scom_data.value);
+    scom_data.words.upper &= ~BITS32(0, 16);
+    scom_data.words.upper |= (CORE_HANG_DIVIDER_4X << SHIFT32(7));
+    scom_data.words.upper |= (CORE_HANG_DIVIDER_4X << SHIFT32(15));
+    CME_PUTSCOM(C_HANG_CONTROL, core, scom_data.value);
+
     return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c
index c3c237f8..6e076d18 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c
@@ -28,12 +28,13 @@
 #include "p9_hcode_image_defines.H"
 
 int
-p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_l2, uint32_t m_pg, int is_stop8)
+p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_ex, int is_stop8)
 {
     int rc = SGPE_STOP_SUCCESS;
     int i;
     uint32_t qoffset = 0;
     uint32_t qaddr   = 0;
+    uint64_t qdata   = 0;
     uint32_t rid     = 0;
 
     // doing this instead of multiply since there is no multiply instruction with ppe.
@@ -61,17 +62,15 @@ p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_l2, uint32_t m_pg, int is_stop8)
         // L2_TRA(0,1) 001010 001011
         rid   = (qaddr & BITS32(18, 4)) >> SHIFT32(21);
 
-        // STOP11: Partial bad ex and non exiting l2 address detection
+        // STOP11: Partial bad ex and l2 address detection
         // First had to be an EX address not quad address to check for partial bad
+        // then skip all l2 addresses for stop11, leave it stop8 portion
         // if ex0 is partial bad and bit21 is 0, skip this address
         // if ex1 is partial bad and bit21 is 1, skip this address
-        // if l20 is not exiting and bit18:21 is 0010 or 1010, skip this address
-        // if l21 is not exiting and bit18:21 is 0011 or 1011, skip this address
         if ((!is_stop8) && (rid & 0xE) &&
-            ((((~m_pg) & FST_EX_IN_QUAD) && ((~rid) & 0x1)) ||
-             (((~m_pg) & SND_EX_IN_QUAD) && (( rid) & 0x1)) ||
-             (((~m_l2) & FST_EX_IN_QUAD) && ((rid == 0x2) || (rid == 0xA))) ||
-             (((~m_l2) & SND_EX_IN_QUAD) && ((rid == 0x3) || (rid == 0xB)))))
+            ((rid <= 0x3) || (rid >= 0xA) ||
+             (((~m_ex) & FST_EX_IN_QUAD) && ((~rid) & 0x1)) ||
+             (((~m_ex) & SND_EX_IN_QUAD) && (( rid) & 0x1))))
         {
             continue;
         }
@@ -80,14 +79,15 @@ p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_l2, uint32_t m_pg, int is_stop8)
         // if l20 exiting and rid != l20, skip this address
         // if l21 exiting and rid != l21, skip this address
         if (is_stop8 &&
-            (!((m_l2 & FST_EX_IN_QUAD) && ((rid == 0x2) || (rid == 0xA)))) &&
-            (!((m_l2 & SND_EX_IN_QUAD) && ((rid == 0x3) || (rid == 0xB)))))
+            (!((m_ex & FST_EX_IN_QUAD) && ((rid == 0x2) || (rid == 0xA)))) &&
+            (!((m_ex & SND_EX_IN_QUAD) && ((rid == 0x3) || (rid == 0xB)))))
         {
             continue;
         }
 
-        PK_TRACE("scom[%d] addr[%x] data[%016llx]", i, qaddr, pSgpeScomRes->data);
-        GPE_PUTSCOM(qaddr, pSgpeScomRes->data);
+        qdata = pSgpeScomRes->data;
+        PK_TRACE("scom[%d] addr[%x] data[%016llx]", i, qaddr, qdata);
+        GPE_PUTSCOM(qaddr, qdata);
     }
 
     return rc;
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
index 36847c1f..957f7ec3 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
@@ -25,21 +25,169 @@
 
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
+#include "p9_hcode_image_defines.H"
 
 extern SgpeStopRecord G_sgpe_stop_record;
 
 int
-p9_hcd_cache_scominit(uint32_t quad, uint32_t ex)
+p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
 {
     int rc = SGPE_STOP_SUCCESS;
-    data64_t   scom_data;
-
-    PK_TRACE("Enable DTS via THERM_MODE_REG[5,6-9,20-21]");
-    GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_THERM_MODE_REG, quad), scom_data.value);
-    scom_data.words.upper |= BIT32(5);     // DTS sampling enable
-    scom_data.words.upper |= BITS32(6, 4); // sample pulse count
-    scom_data.words.upper |= BITS32(20, 2);// DTS loop1 enable
-    GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_THERM_MODE_REG, quad), scom_data.value);
+    /// @todo change this back to 0, when flag bit is ready via image build
+    int attr_proc_fabric_addr_bar_mode_small_system = 1; // default small
+    int attr_proc_fabric_dump_mode_chip_is_node     = 0; // default group
+    data64_t scom_data;
+    sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET);
+
+    if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(16))
+    {
+        attr_proc_fabric_addr_bar_mode_small_system = 1;
+    }
+
+    if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT64(17))
+    {
+        attr_proc_fabric_dump_mode_chip_is_node = 1;
+    }
+
+    // Note: Epsilon settings are done via image build and scom restore(scomcust), not here
+
+    if (!is_stop8) // Quad overall + L3/NCU(except L2) settings goes here
+    {
+        PK_TRACE("Enable DTS via THERM_MODE_REG[5,6-9,20-21]");
+        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_THERM_MODE_REG, quad), scom_data.value);
+        scom_data.words.upper |= BIT32(5);     // DTS sampling enable
+        scom_data.words.upper |= BITS32(6, 4); // sample pulse count
+        scom_data.words.upper |= BITS32(20, 2);// DTS loop1 enable
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_THERM_MODE_REG, quad), scom_data.value);
+
+        if (m_ex & FST_EX_IN_QUAD)
+        {
+            // p9_l3_scom
+
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 0), scom_data.value);
+            scom_data.words.upper &= ~(BIT32(1) | BITS32(14, 8) | BIT32(22));
+            scom_data.words.upper |= (BIT32(2) | BIT32(17) | BIT32(19)); // set b11 with L2
+
+            if (attr_proc_fabric_addr_bar_mode_small_system)
+            {
+                scom_data.words.upper |= BIT32(22);
+            }
+
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 0), scom_data.value);
+
+            // p9_ncu_scom
+
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG,  quad, 0), scom_data.value);
+            scom_data.words.upper &= ~BIT32(9);
+
+            if (attr_proc_fabric_addr_bar_mode_small_system)
+            {
+                scom_data.words.upper |= BIT32(9);
+            }
+
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG,  quad, 0), scom_data.value);
+
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG2, quad, 0), 0x1402220100000000);
+        }
+
+        if (m_ex & SND_EX_IN_QUAD)
+        {
+            // p9_l3_scom
+
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 1), scom_data.value);
+            scom_data.words.upper &= ~(BIT32(1) | BITS32(14, 8) | BIT32(22));
+            scom_data.words.upper |= (BIT32(2) | BIT32(17) | BIT32(19)); // set b11 with L2
+
+            if (attr_proc_fabric_addr_bar_mode_small_system)
+            {
+                scom_data.words.upper |= BIT32(22);
+            }
+
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 1), scom_data.value);
+
+            // p9_ncu_scom
+
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG,  quad, 1), scom_data.value);
+            scom_data.words.upper &= ~BIT32(9);
+
+            if (attr_proc_fabric_addr_bar_mode_small_system)
+            {
+                scom_data.words.upper |= BIT32(9);
+            }
+
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG,  quad, 1), scom_data.value);
+
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG2, quad, 1), 0x1402220100000000);
+        }
+    }
+    else
+    {
+        if (m_ex & FST_EX_IN_QUAD)
+        {
+            // L3_MODE0[11] L3_ADDR_HASH_EN_CFG must be set along with
+            // L2_MODE0[21] CFG_HASH_L3_ADDR_EN
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 0), scom_data.value);
+            scom_data.words.upper |= BIT32(11);
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 0), scom_data.value);
+
+            // p9_l2_scom
+
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, 0), scom_data.value);
+            scom_data.words.lower |= BIT32(6); // bit38
+            scom_data.words.upper |= (BIT32(15) | BIT32(21));
+            scom_data.words.upper &= ~BIT32(23);
+
+            if (attr_proc_fabric_addr_bar_mode_small_system)
+            {
+                scom_data.words.upper |= BIT32(23);
+            }
+
+            if (attr_proc_fabric_dump_mode_chip_is_node)
+            {
+                scom_data.words.lower &= ~BIT32(6);
+            }
+
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, 0), scom_data.value);
+
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, 0), scom_data.value);
+            scom_data.words.upper &= BITS32(4, 8);
+            scom_data.words.upper |= (BIT32(7) | BIT32(9));
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, 0), scom_data.value);
+        }
+
+        if (m_ex & SND_EX_IN_QUAD)
+        {
+            // L3_MODE0[11] L3_ADDR_HASH_EN_CFG must be set along with
+            // L2_MODE0[21] CFG_HASH_L3_ADDR_EN
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 1), scom_data.value);
+            scom_data.words.upper |= BIT32(11);
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, 1), scom_data.value);
+
+            // p9_l2_scom
+
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, 1), scom_data.value);
+            scom_data.words.lower |= BIT32(6); // bit38
+            scom_data.words.upper |= (BIT32(15) | BIT32(21));
+            scom_data.words.upper &= ~BIT32(23);
+
+            if (attr_proc_fabric_addr_bar_mode_small_system)
+            {
+                scom_data.words.upper |= BIT32(23);
+            }
+
+            if (attr_proc_fabric_dump_mode_chip_is_node)
+            {
+                scom_data.words.lower &= ~BIT32(6);
+            }
+
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG0, quad, 1), scom_data.value);
+
+            GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, 1), scom_data.value);
+            scom_data.words.upper &= BITS32(4, 8);
+            scom_data.words.upper |= (BIT32(7) | BIT32(9));
+            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, 1), scom_data.value);
+        }
+    }
 
     return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index 16aea250..70fc6f05 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -110,9 +110,20 @@ extern "C" {
 #define EQ_QPPM_QCCR_WCLEAR      0x100F01BE
 #define EQ_QPPM_QCCR_WOR         0x100F01BF
 
-#define EX_NCU_STATUS_REG        0x1001100F
+#define EX_L2_MODE_REG0          0x1001080A
+#define EX_L2_MODE_REG1          0x1001080B
+#define EX_L2_RD_EPS_REG         0x10010810
+#define EX_L2_WR_EPS_REG         0x10010811
+
+#define EX_L3_RD_EPSILON_CFG_REG 0x10011829
+#define EX_L3_WR_EPSILON_CFG_REG 0x1001182A
 #define EX_L3_MODE_REG0          0x1001182B
 #define EX_L3_MODE_REG1          0x1001180A
+
+#define EX_NCU_MODE_REG          0x1001100A
+#define EX_NCU_MODE_REG2         0x1001100B
+#define EX_NCU_STATUS_REG        0x1001100F
+
 #define EX_DRAM_REF_REG          0x1001180F
 #define EX_PM_PURGE_REG          0x10011813
 #define EX_PM_LCO_DIS_REG        0x10011816
@@ -264,8 +275,8 @@ int  p9_hcd_cache_arrayinit(uint32_t, uint32_t ex);
 int  p9_hcd_cache_initf(uint32_t);
 int  p9_hcd_cache_startclocks(uint32_t, uint32_t);
 int  p9_hcd_cache_l2_startclocks(uint32_t, uint32_t, uint32_t);
-int  p9_hcd_cache_scominit(uint32_t, uint32_t);
-int  p9_hcd_cache_scomcust(uint32_t, uint32_t, uint32_t, int);
+int  p9_hcd_cache_scominit(uint32_t, uint32_t, int);
+int  p9_hcd_cache_scomcust(uint32_t, uint32_t, int);
 int  p9_hcd_cache_ras_runtime_scom(uint32_t);
 int  p9_hcd_cache_occ_runtime_scom(uint32_t);
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
index 4bccdef1..60739c28 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
@@ -464,10 +464,16 @@ p9_sgpe_stop_exit()
             PK_TRACE_INF("SX8.A: Cache L2 Startclocks");
             p9_hcd_cache_l2_startclocks(qloop, m_l2, m_pg);
 
+            // for l2 scom init and restore that cannot be done via stop11
+            // as if that certain l2 wasnt exiting(thus lack of clock for scom)
+
+            PK_TRACE_INF("SX8.B: Cache L2 Scominit");
+            p9_hcd_cache_scominit(qloop, m_l2, 1);
+
 #if !SKIP_HOMER_ACCESS
 
-            // for l2 scom restore that cannot be done via stop11 as l2 wasnt exiting
-            p9_hcd_cache_scomcust(qloop, m_l2, m_pg, 1);
+            PK_TRACE_INF("SX8.C: Cache L2 Scomcust");
+            p9_hcd_cache_scomcust(qloop, m_l2, 1);
 
 #endif
 
@@ -529,12 +535,12 @@ p9_sgpe_stop_exit()
             //====================================
 
             PK_TRACE_INF("SX11.M: Cache Scom Init");
-            p9_hcd_cache_scominit(qloop, m_pg);
+            p9_hcd_cache_scominit(qloop, m_pg, 0);
 
 #if !SKIP_HOMER_ACCESS
 
             PK_TRACE_INF("SX11.N: Cache Scom Cust");
-            p9_hcd_cache_scomcust(qloop, m_l2, m_pg, 0);
+            p9_hcd_cache_scomcust(qloop, m_pg, 0);
 
 #endif