STOP/PSTATE: Fix CACCR Dual Cast Machine Check on Data mismatch

Key_Cronus_Test=PM_REGRESS

Change-Id: I093f1b98abf5f48e99c901d64aa47750c1abc83c
CQ: SW426908
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57958
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

1 files changed, 25 insertions, 12 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c
index d0b00ca3..64dc4468 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c
@@ -391,6 +391,7 @@ void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable)
     {
         uint32_t pstate;
         uint32_t curr_idx;
+        uint32_t next_idx;
         uint64_t val;
 
         if(enable)
@@ -420,18 +421,30 @@ void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable)
         else
         {
             PK_TRACE_INF("resclk | disabling resclks");
+
+            pstate = ANALOG_PSTATE_RESCLK_OFF;
+            next_idx = p9_cme_resclk_get_index(pstate);
+            curr_idx = p9_cme_resclk_get_index(G_cme_pstate_record.quadPstate);
+
             // 1) copy QACCR[0:12] into CACCR[0:12], with CACCR[13:14]=0b00,
             //    to switch away from common control. QACCR will already be set
             //    to a value corresponding to the current quad Pstate
-            ippm_read(QPPM_QACCR, &val);
-            val &= BITS64(0, 13);
-            // clk_sync enable (bit 15) is ALWAYS 0b0 at this point due to the
-            // sequence of function calls in Stop Entry
-            CME_PUTSCOM(CPPM_CACCR, core_mask, val);
-            curr_idx = p9_cme_resclk_get_index(G_cme_pstate_record.quadPstate);
+
+            if (curr_idx != next_idx)
+            {
+                ippm_read(QPPM_QACCR, &val);
+                val &= BITS64(0, 13);
+                // clk_sync enable (bit 15) is ALWAYS 0b0 at this point due to the
+                // sequence of function calls in Stop Entry
+                CME_PUTSCOM(CPPM_CACCR, core_mask, val);
+            }
+            else
+            {
+                CME_PUTSCOM(CPPM_CACCR_CLR, core_mask, (BITS64(13, 2)));
+            }
+
             // 2) step CACCR to a value which disables resonance
-            pstate = ANALOG_PSTATE_RESCLK_OFF;
-            p9_cme_resclk_update(core_mask, p9_cme_resclk_get_index(pstate), curr_idx);
+            p9_cme_resclk_update(core_mask, next_idx, curr_idx);
         }
     }
 
@@ -797,9 +810,9 @@ uint32_t p9_cme_vdm_update(uint32_t pstate)
 #ifdef USE_CME_RESCLK_FEATURE
 void p9_cme_resclk_update(ANALOG_TARGET target, uint32_t next_idx, uint32_t curr_idx)
 {
-    uint64_t base_val;
-    uint64_t val;
-    int32_t  step;
+    uint64_t base_val = 0;
+    uint64_t val      = 0;
+    int32_t  step     = 0;
 
     PK_TRACE_DBG("resclk | target=%08x", (uint32_t)target);
     PK_TRACE_DBG("resclk | curr_idx=%d", curr_idx);
@@ -820,7 +833,7 @@ void p9_cme_resclk_update(ANALOG_TARGET target, uint32_t next_idx, uint32_t curr
     {
         ippm_read(QPPM_QACCR, &base_val);
     }
-    else
+    else if (curr_idx != next_idx)
     {
         CME_GETSCOM(CPPM_CACCR, target, base_val);
     }