HW389511: fix cme write to wakeup switch suppress sgpe writes

Change-Id: I05a30c065d3ef3c899ebc2be2fc67adb32e9804e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34316
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: JAMES DEZELLE <jdezelle@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

3 files changed, 35 insertions, 2 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/lib/p9_dd1_doorbell_wr.c b/import/chips/p9/procedures/ppe_closed/lib/p9_dd1_doorbell_wr.c
index 936da2ba..0ae3919f 100644
--- a/import/chips/p9/procedures/ppe_closed/lib/p9_dd1_doorbell_wr.c
+++ b/import/chips/p9/procedures/ppe_closed/lib/p9_dd1_doorbell_wr.c
@@ -34,6 +34,28 @@
 #define PCB_MC_READ_AND 0x48000000ul
 #define PCB_MC_WRITE    0x68000000ul
 
+void p9_dd1_cppm_unicast_wr(uint32_t baddr, uint32_t laddr, uint64_t wdata, int op)
+{
+    uint64_t rdata;
+
+    wrteei(0);
+
+    do
+    {
+        GPE_PUTSCOM(laddr, wdata);
+        GPE_GETSCOM(baddr, rdata);
+    }
+    while(((op == NO_OP)  && (  rdata != wdata)) ||
+          // Basic Write and data was not updated
+          ((op == OR_OP)  && ((~rdata) & wdata)) ||
+          //Write-OR and the requested bits were not set
+          ((op == CLR_OP) && ( (rdata) & wdata)));
+
+    //Write-CLR and the requested bit were not cleared
+
+    wrteei(1);
+}
+
 /// Note: External and timer interrupts are disabled during the "polling"
 //        portions of the code to allow for timeouts using the WDT.
 //        MSR[EE] == 0 will disable the WDT callback and therefore cause
diff --git a/import/chips/p9/procedures/ppe_closed/lib/p9_dd1_doorbell_wr.h b/import/chips/p9/procedures/ppe_closed/lib/p9_dd1_doorbell_wr.h
index 03ec64ac..61b9f702 100644
--- a/import/chips/p9/procedures/ppe_closed/lib/p9_dd1_doorbell_wr.h
+++ b/import/chips/p9/procedures/ppe_closed/lib/p9_dd1_doorbell_wr.h
@@ -27,6 +27,15 @@
 
 #include "stdint.h"
 
+enum LOGIC_INTERFACES
+{
+    NO_OP  = 0,
+    OR_OP  = 1,
+    CLR_OP = 2
+};
+
+void p9_dd1_cppm_unicast_wr(uint32_t baddr, uint32_t laddr, uint64_t wdata, int is_or);
+
 void p9_dd1_db_unicast_wr  (uint32_t addr, uint64_t data);
 
 //
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
index 60739c28..aef08d1d 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
@@ -876,8 +876,10 @@ p9_sgpe_stop_exit()
 
             PK_TRACE_DBG("Check: Core[%d] will clear wakeup_notify_select",
                          ((qloop << 2) + cloop));
-            GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR_CLR,
-                                           ((qloop << 2) + cloop)), BIT64(13));
+            p9_dd1_cppm_unicast_wr(
+                GPE_SCOM_ADDR_CORE(CPPM_CPMMR,     ((qloop << 2) + cloop)),
+                GPE_SCOM_ADDR_CORE(CPPM_CPMMR_CLR, ((qloop << 2) + cloop)),
+                BIT64(13), CLR_OP);
             PK_TRACE_INF("SX0.B: Switch CorePPM Wakeup back to CME via CPMMR[13]");
         }