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| author | Michael Floyd <mfloyd@us.ibm.com> | 2017-05-15 13:45:04 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-08-22 17:54:50 -0500 |
| commit | b46f051b988499b3f18a48f23ec4e469daf6e17a (patch) | |
| tree | c47e295a9ef48e3b469dc68e1edc919449006b70 | |
| parent | 6b5e4bb67b411108291e412a8484f5fe8c8005e3 (diff) | |
| download | talos-hcode-b46f051b988499b3f18a48f23ec4e469daf6e17a.tar.gz talos-hcode-b46f051b988499b3f18a48f23ec4e469daf6e17a.zip | |
STOP: Actually enable Manual Stop1 for Nimbus DD1 to fix the PSSCR PLS reporting
Change-Id: I7b0b25ae5d470288bbcba51da1bf8f1839ecae2d
Original-Change-Id: Ib001a6b4afe22b84f6cbf389cafec71dce86aa7b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40510
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
| -rwxr-xr-x | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index 11274fe2..27b4c7d5 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -378,10 +378,13 @@ p9_cme_stop_entry() out32(CME_LCL_SICR_OR, core_stop1 << SHIFT32(1)); out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1)); - PK_TRACE("Update STOP history: in core stop level 1"); - scom_data.words.lower = 0; - scom_data.words.upper = SSH_ACT_LV1_COMPLETE; - CME_PUTSCOM(PPM_SSHSRC, core_stop1, scom_data.value); + // Removed: Do not want users to become accustomed to seeing Stop1 reflected in Stop History on DD1 + // + //PK_TRACE("Update STOP history: in core stop level 1"); + //scom_data.words.lower = 0; + //scom_data.words.upper = SSH_ACT_LV1_COMPLETE; + //CME_PUTSCOM(PPM_SSHSRC, core_stop1, scom_data.value); + // core = core & ~core_stop1; @@ -415,7 +418,6 @@ p9_cme_stop_entry() out32(CME_LCL_SICR_OR, core << SHIFT32(11)); // Poll Infinitely for PCB Mux Grant - // MF: change watchdog timer in pk to ensure forward progress while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core); PK_TRACE("PCB Mux Granted on Core[%d]", core); @@ -562,7 +564,6 @@ p9_cme_stop_entry() while((lclr_data & core) != core); // Waits quiesce done for at least 512 core cycles - // MF: verify generate FCB otherwise math is wrong. PPE_WAIT_CORE_CYCLES(512) PK_TRACE_INF("SE.2B: Interfaces Quiesced"); @@ -691,9 +692,6 @@ p9_cme_stop_entry() PK_PANIC(CME_STOP_ENTRY_STOPCLK_FAILED); } - // MF: verify compiler generate single rlwmni - // MF: delay may be needed for stage latch to propagate thold - PK_TRACE_INF("SE.2C: Core Clock Stopped"); //============================== |
