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| author | Greg Still <stillgs@us.ibm.com> | 2017-09-14 11:10:46 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 19:16:03 -0500 |
| commit | 99e0fb28edbba5cd495acc7db633cc0ec0c90b6d (patch) | |
| tree | 0f177e997186f04d2ed346d3dbe7ce78f9c7743e | |
| parent | 17d5a643299369a48fad08571e7422a09e0332f6 (diff) | |
| download | talos-hcode-99e0fb28edbba5cd495acc7db633cc0ec0c90b6d.tar.gz talos-hcode-99e0fb28edbba5cd495acc7db633cc0ec0c90b6d.zip | |
PM: Added nest frequency to all HCcode headers for trace timebases
- needed for accurate timestamps in PK Traces
- applies to CME, SGPE and PGPE
Change-Id: I30e27cddead8ba4f2edb1919edbf935e40774e2e
RTC: 179852
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46208
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
| -rw-r--r-- | import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 9567811e..332047f1 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -232,7 +232,7 @@ HCD_HDR_UINT64(g_sgpe_magic_number, SGPE_MAGIC_NUMBER); //SGPE 1.0 HCD_HDR_UINT32(g_sgpe_reset_address, 0); HCD_HDR_UINT32(g_sgpe_reserve1, 0); HCD_HDR_UINT32(g_sgpe_ivpr_address, 0); -HCD_HDR_UINT32(g_sgpe_reserve2, 0); +HCD_HDR_UINT32(g_sgpe_timebase_hz, 0); HCD_HDR_UINT32(g_sgpe_build_date, 0); HCD_HDR_UINT32(g_sgpe_build_ver, 0); HCD_HDR_UINT32(g_sgpe_reserve_flags, 0); @@ -291,7 +291,7 @@ HCD_HDR_UINT32(g_cme_scom_length, 0); HCD_HDR_UINT32(g_cme_mode_flags, 0); HCD_HDR_UINT16(g_cme_location_id, 0); HCD_HDR_UINT16(g_cme_qm_mode_flags, 0); -HCD_HDR_UINT32(g_cme_reserved2, 0); //Retain next field at 8B boundary +HCD_HDR_UINT32(g_cme_timebase_hz, 0); //Retain next field at 8B boundary HCD_HDR_UINT64(g_cme_cpmr_PhyAddr, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ @@ -337,7 +337,7 @@ HCD_HDR_UINT32(g_pgpe_build_date, 0 ); // Build date for PG HCD_HDR_UINT32(g_pgpe_build_ver, 0 ); // Build Version HCD_HDR_UINT16(g_pgpe_flags, 0 ); // PGPE Flags HCD_HDR_UINT16(g_pgpe_reserve1, 0 ); // Reserve field -HCD_HDR_UINT32(g_pgpe_reserve2, 0 ); // Reserve field +HCD_HDR_UINT32(g_pgpe_timebase_hz, 0 ); // Timebase (in Hz) - dependent on nest frequency HCD_HDR_UINT32(g_pgpe_gppb_sram_addr, 0 ); // Offset to Global P State Parameter Block HCD_HDR_UINT32(g_pgpe_hcode_length, 0 ); // Length of PGPE Hcode HCD_HDR_UINT32(g_pgpe_gppb_mem_offset, |
