Add Periodic Core Quiesce Disable Scom Propagation

Change-Id: Ie25cba244f9ea69d8aca04efc9d5c47c30be1218
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45140
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

4 files changed, 52 insertions, 1 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
index 5146c568..9e6ffd2f 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
@@ -181,6 +181,7 @@ enum PM_GPE_OCCFLG_DEFS
     SGPE_IGNORE_STOP_ACTION             = 10,
     SGPE_IGNORE_STOP_EXITS              = 11,
     SGPE_IGNORE_STOP_ENTRIES            = 12,
+    OCCFLG_CORE_QUIESCE_WORKARND_DIS    = 13,
     SGPE_24_7_ACTIVATE                  = 14,
     SGPE_24_7_ACTIVE                    = 15,
     PIB_I2C_MASTER_ENGINE_1_LOCK_BIT0   = 16, //BIT0 ored BIT1 gives the field
@@ -224,6 +225,7 @@ enum PM_CME_FLAGS_DEFS
     CME_FLAGS_OCC_HB_SAFE_MODE              = 7,
     CME_FLAGS_BLOCK_WKUP_C0                 = 8,
     CME_FLAGS_BLOCK_WKUP_C1                 = 9,
+    CME_CORE_QUIESCE_WORKARND_DIS           = 23,
     CME_FLAGS_PSTATES_ENABLED               = 24,
     CME_FLAGS_FREQ_UPDT_DISABLE             = 25,
     CME_FLAGS_EX_ID                         = 26,
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
index 04bb496d..fb2699ab 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
@@ -49,6 +49,8 @@ uint32_t G_aux_task_count;
 uint32_t G_tb_sync_count_threshold;
 uint32_t G_tb_sync_count;
 
+uint32_t G_last_core_quiesce_dis;
+
 extern GlobalPstateParmBlock* G_gppb;
 extern PgpeHeader_t* G_pgpe_header_data;
 extern PgpePstateRecord G_pgpe_pstate_record;
@@ -101,6 +103,7 @@ void p9_pgpe_fit_init()
     G_throttleCount = 0;
     G_beacon_count = 0;
     G_tb_sync_count = 0;
+    G_last_core_quiesce_dis = (in32(OCB_OCCFLG) & BIT32(OCCFLG_CORE_QUIESCE_WORKARND_DIS));
     ppe42_fit_setup(p9_pgpe_fit_handler, NULL);
 }
 
@@ -273,6 +276,33 @@ __attribute__((always_inline)) inline void handle_fit_timebase_sync()
     }
 }
 
+__attribute__((always_inline)) inline void handle_core_quiesce_dis()
+{
+    if(G_last_core_quiesce_dis != (in32(OCB_OCCFLG) & BIT32(OCCFLG_CORE_QUIESCE_WORKARND_DIS)))
+    {
+        G_last_core_quiesce_dis = (in32(OCB_OCCFLG) & BIT32(OCCFLG_CORE_QUIESCE_WORKARND_DIS));
+        uint64_t wrtAddr = G_last_core_quiesce_dis ? CME_SCOM_FLAGS_OR : CME_SCOM_FLAGS_CLR;
+        uint32_t q;
+        ocb_qcsr_t qcsr;
+        qcsr.value = in32(OCB_QCSR);
+
+        for (q = 0; q < MAX_QUADS; q++)
+        {
+            if (qcsr.fields.ex_config &  (0x800 >> (q << 1)))
+            {
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(wrtAddr,
+                                              q, 0), BIT64(CME_CORE_QUIESCE_WORKARND_DIS));
+            }
+
+            if (qcsr.fields.ex_config &  (0x400 >> (q << 1)))
+            {
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(wrtAddr,
+                                              q, 1), BIT64(CME_CORE_QUIESCE_WORKARND_DIS));
+            }
+        }
+    }
+}
+
 //p9_pgpe_fit_handler
 //
 //This is a periodic FIT Handler whose period is determined
@@ -284,4 +314,5 @@ void p9_pgpe_fit_handler(void* arg, PkIrqId irq)
     handle_core_throttle();
     handle_aux_task();
     handle_fit_timebase_sync();
+    handle_core_quiesce_dis();
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
index d8503a92..c3a837fd 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
@@ -322,6 +322,15 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
                 GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIXCR,
                                               (l_cmeIndex >> 1), (l_cmeIndex % 2)), HARD_RESET_PPE);
 
+                //Set CME DIS_CORE_QUIESCE_WORKARND accordingly
+                PK_TRACE_INF("OCB_OCCFLG: %X", in32(OCB_OCCFLG));
+
+                if(in32(OCB_OCCFLG) & BIT32(OCCFLG_CORE_QUIESCE_WORKARND_DIS))
+                {
+                    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS_OR,
+                                                  (l_cmeIndex >> 1), (l_cmeIndex % 2)), BIT64(CME_CORE_QUIESCE_WORKARND_DIS));
+                }
+
                 // Kick off CME by giving resume command through PPE External Control Register
                 // Writing to XCR to resume PPE operation
                 GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIXCR,
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c
index da7514fa..0631087b 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c
@@ -302,6 +302,16 @@ p9_sgpe_stop_init()
 
     G_sgpe_stop_record.group.core[VECTOR_PCWU]   = 0;
 
+    //Write Core Quiesce Workaround Disable bit to OCC Flag
+    uint32_t occflg = in32(OCB_OCCFLG) & ~BIT32(13);
+    sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR);
+
+    if(pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(7))//SGPE_CORE_PERIODIC_QUIESCE_DISABLE_POS))
+    {
+        out32(OCB_OCCFLG, occflg | BIT32(OCCFLG_CORE_QUIESCE_WORKARND_DIS));
+    }
+
+
     for(qloop = 0, m_1c = BIT32(0), m_2c = BITS32(0, 2), m_4c = BITS32(0, 4),
         m_1x = BIT32(0), m_2x = BITS32(0, 2), m_qs = BIT32(14);
         qloop < MAX_QUADS;
@@ -456,7 +466,6 @@ p9_sgpe_stop_init()
 
     uint32_t cme_flags   = 0;
     uint16_t cmeBootList = ((~qssr.value) >> 16) & 0xFFF0;
-    sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR);
 
     PK_TRACE_INF("Setup: Prepare CME[%x] to be Booted", cmeBootList);