diff options
| author | Yue Du <daviddu@us.ibm.com> | 2018-02-23 09:57:34 -0600 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-03-22 14:04:55 -0500 |
| commit | 8ef47fdd07e007ce609add736156bd1585954ec5 (patch) | |
| tree | d2d30c34934189e1289baa4fd9915344fb9ea2f4 | |
| parent | a28b4fd8c2ce94b19867c94574597fb635899fc2 (diff) | |
| download | talos-hcode-8ef47fdd07e007ce609add736156bd1585954ec5.tar.gz talos-hcode-8ef47fdd07e007ce609add736156bd1585954ec5.zip | |
STOP: Support Suspend Entry/Exit and Fix Pig Collision
1) also cleanup todos in Stop Hcode
2) make STOP3 complete trans in SSH
Key_Cronus_Test=PM_REGRESS
Change-Id: I83a3387d0666080c60b167234e44564d90f193f5
Original-Change-Id: I28a146e15e455f09f8d8ff588e122d5ecf34110a
CQ: SW416550
CQ: HW437955
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54660
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
3 files changed, 9 insertions, 1 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h index cff41489..bb641c8f 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h +++ b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h @@ -119,6 +119,7 @@ enum PM_CME_FLAGS_DEFS CME_FLAGS_CORE_QUIESCE_ACTIVE = 12, CME_FLAGS_PM_DEBUG_HALT_ENABLE = 13, CME_FLAGS_WAIT_ON_PSTATE_START = 14, + CME_FLAGS_BLOCK_ENTRY_STOP11 = 23, CME_FLAGS_PSTATES_ENABLED = 24, CME_FLAGS_FREQ_UPDT_DISABLE = 25, CME_FLAGS_EX_ID = 26, diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 9ef0e60e..321359f6 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -323,7 +323,8 @@ p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop) // chiplet fence forces pm_active to zero // Note: pm_exit is asserted above for every core waking up including spwu PK_TRACE_DBG("SX.0B: Core[%d] Assert SPWU_DONE via SICR[16/17]", spwu_stop); - out32(CME_LCL_EISR_CLR, (spwu_stop << SHIFT32(15)) | (spwu_stop << SHIFT32(21))); // clear spwu in EISR + // Note: clear pm_active so that potential stop1 wont use leftover pm_active upon drop spwu later + out32(CME_LCL_EISR_CLR, ((spwu_stop << SHIFT32(15)) | (spwu_stop << SHIFT32(21)))); // clear spwu in EISR out32(CME_LCL_EIPR_CLR, spwu_stop << SHIFT32(15)); // flip EIPR to falling edge out32(CME_LCL_SICR_OR, spwu_stop << SHIFT32(17)); // assert spwu_done now G_cme_stop_record.core_in_spwu |= spwu_stop; @@ -571,6 +572,7 @@ p9_cme_stop_exit() { // Process special wakeup on a core that is already running PK_TRACE_DBG("SP.WU: Core[%d] Assert PM_EXIT and SPWU_DONE via SICR[4/5, 16/17]", spwu_wake); + // Note: clear pm_active so that potential stop1 wont use leftover pm_active upon drop spwu later out32(CME_LCL_SICR_OR, spwu_wake << SHIFT32(5)); // assert pm_exit out32(CME_LCL_EISR_CLR, ((spwu_wake << SHIFT32(15)) | (spwu_wake << SHIFT32(21)))); // clear spwu in EISR out32(CME_LCL_EIPR_CLR, spwu_wake << SHIFT32(15)); // flip EIPR to falling edge diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c index 9233c05c..ae06639b 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c @@ -60,6 +60,11 @@ void p9_sgpe_stop_cme_scominit(uint32_t quad, uint32_t cme, uint32_t cme_flags) uint64_t chtm_size = 0; data64_t scom_data = {0}; + if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKE] & BIT32(quad)) + { + cme_flags |= BIT32(CME_FLAGS_BLOCK_ENTRY_STOP11); + } + PK_TRACE("Setup CME Flags"); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS, quad, cme), ((uint64_t)cme_flags) << 32); |
