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authorYue Du <daviddu@us.ibm.com>2017-05-17 16:18:50 -0500
committerhostboot <hostboot@us.ibm.com>2018-08-22 17:54:52 -0500
commit8e8f54fb5906f78a7ef84fd9e76451847e63e38e (patch)
treed58cd60cac7062d46fd0e5110247ea58a77b7806
parent69de20ee7f498298401e1239327525453e3cf452 (diff)
downloadtalos-hcode-8e8f54fb5906f78a7ef84fd9e76451847e63e38e.tar.gz
talos-hcode-8e8f54fb5906f78a7ef84fd9e76451847e63e38e.zip
STOP: Stop1 overall fix
Change-Id: I004d8662343da64c4aff31a23a8a5037e1f811e2 Original-Change-Id: I101179bce569ad47970d17e15c1213eee00fe447 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40680 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
-rwxr-xr-ximport/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c38
1 files changed, 23 insertions, 15 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 9de96183..8f15f4c7 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -380,17 +380,14 @@ p9_cme_stop_entry()
out32(CME_LCL_SICR_OR, core_stop1 << SHIFT32(1));
out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1));
+ // Removed: Do not want users to become accustomed to
+ // seeing Stop1 reflected in Stop History on DD1
+ /*
PK_TRACE("Update STOP history: in core stop level 1");
scom_data.words.lower = 0;
scom_data.words.upper = SSH_ACT_LV1_COMPLETE;
CME_PUTSCOM(PPM_SSHSRC, core_stop1, scom_data.value);
-
- core = core & ~core_stop1;
-
- if (!core)
- {
- break;
- }
+ */
#else
@@ -403,9 +400,6 @@ p9_cme_stop_entry()
}
- //----------------------------------------------------------------------
- PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++");
- //----------------------------------------------------------------------
#if HW405292_NDD1_PCBMUX_SAVIOR
@@ -417,7 +411,6 @@ p9_cme_stop_entry()
out32(CME_LCL_SICR_OR, core << SHIFT32(11));
// Poll Infinitely for PCB Mux Grant
- // MF: change watchdog timer in pk to ensure forward progress
while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core);
PK_TRACE("PCB Mux Granted on Core[%d]", core);
@@ -428,6 +421,25 @@ p9_cme_stop_entry()
#endif
+#if HW386841_NDD1_DSL_STOP1_FIX
+
+ // check target after getting PCBMUX for Stop1 Workaround
+ if (core_stop1)
+ {
+ core = core & ~core_stop1;
+
+ if (!core)
+ {
+ break;
+ }
+ }
+
+#endif
+
+ //----------------------------------------------------------------------
+ PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++");
+ //----------------------------------------------------------------------
+
// set target_level from pm_state for both cores or just one core
target_level = (core == CME_MASK_C0) ? G_cme_stop_record.req_level[0] :
G_cme_stop_record.req_level[1];
@@ -564,7 +576,6 @@ p9_cme_stop_entry()
while((lclr_data & core) != core);
// Waits quiesce done for at least 512 core cycles
- // MF: verify generate FCB otherwise math is wrong.
PPE_WAIT_CORE_CYCLES(512)
PK_TRACE_INF("SE.2B: Interfaces Quiesced");
@@ -693,9 +704,6 @@ p9_cme_stop_entry()
PK_PANIC(CME_STOP_ENTRY_STOPCLK_FAILED);
}
- // MF: verify compiler generate single rlwmni
- // MF: delay may be needed for stage latch to propagate thold
-
PK_TRACE_INF("SE.2C: Core Clock Stopped");
//==============================
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