WOF/PGPE Bug Fixes(Set 2)

    -Fixes Inter-CME interrupt issue
    -Fixed back to back CLIP Updt issue
    -reverses CLIP_UPDT clip_min and clip_max(as per OCC)
    -Fixes AVS_Driver issues
    -Moved VPD points from GeneratedPstateInfo to Global Parm
    -Added nest frequency field to OCCParmBlock
    -Picking up slopes from Global Parm

Change-Id: I7578a8a51efde59f0678b9c3f44be77bf7a15603
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36741
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

16 files changed, 437 insertions, 343 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
index 5113d8d8..2d8f3bea 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
@@ -120,8 +120,8 @@
 #define VPD_SLOPES_RAW      0
 #define VPD_SLOPES_BIASED   1
 #define VPD_NUM_SLOPES_REGION       3
-#define REGION_POWERSAVE_NOMINAL    1
-#define REGION_NOMINAL_TURBO        0
+#define REGION_POWERSAVE_NOMINAL    0
+#define REGION_NOMINAL_TURBO        1
 #define REGION_TURBO_ULTRA          2
 
 // Different points considered for calculating slopes
@@ -130,6 +130,8 @@
 #define VPD_PT_SET_SYSP             1
 #define VPD_PT_SET_BIASED           2
 #define VPD_PT_SET_BIASED_SYSP      3
+#define VPD_PT_SET_ORDER {VPD_PT_SET_RAW, VPD_PT_SET_SYSP, VPD_PT_SET_BIASED, VPD_PT_SET_BIASED_SYSP}
+#define VPD_PT_SET_ORDER_STR {"Raw          ", "SysParam       ","Biased        ", "Biased/SysParam"}
 
 #define EVID_SLOPE_FP_SHIFT         13
 
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
index f61dcb00..f945adc2 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
@@ -185,6 +185,8 @@ typedef struct
     // Minimum Pstate;  Maximum is always 0.
     uint32_t pstate_min;    // Comes from PowerSave #V point after biases
 
+    /// Nest frequency in Mhz. This is used by FIT interrupt
+    uint32_t nest_frequency_mhz;
 } __attribute__((aligned(128))) OCCPstateParmBlock;
 
 #ifdef __cplusplus
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
index a06f586b..cd5895c0 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
@@ -241,6 +241,8 @@ typedef struct
     /// Precalculated Voltage-Pstates Slopes
     uint16_t VPsSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
 
+    /// All operating points
+    VpdOperatingPoint operating_points_set[NUM_VPD_PTS_SET][VPD_PV_POINTS];
 
     // @todo DPLL Droop Settings.  These need communication to SGPE for STOP
 
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
index 5e8ac7a1..8cbb744a 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
@@ -122,15 +122,6 @@ typedef struct
     /// Note: if all bias attributes are 0, this content will be the same
     /// as the raw_pstates content.
     PstateTable biased_pstates[MAX_PSTATE_TABLE_ENTRIES];
-
-    ///VPD Operating points generated after applying biases
-    VpdOperatingPoint operating_points_biased[VPD_PV_POINTS];
-
-    ///VPD Operating points generated after applying system parameters
-    VpdOperatingPoint operating_points_sysp[VPD_PV_POINTS];
-
-    ///VPD Operating points generated after applying system parameters and biases
-    VpdOperatingPoint operating_points_biased_sysp[VPD_PV_POINTS];
 } GeneratedPstateInfo;
 
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
index 45860434..4e3ac93d 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
@@ -55,38 +55,55 @@ void p9_cme_pstate_intercme_in0_handler(void* arg, PkIrqId irq)
     int32_t c = 0;
     PkMachineContext  ctx;
 
-    PK_TRACE("INTERCME_IN0: Enter\n");
+    PK_TRACE("INTER0: Enter\n");
 
     for (c = 0; c < CORES_PER_EX; c++ )
     {
         if (cme_flags & (CME_FLAGS_CORE0_GOOD >> c))
         {
+            if (c == 0)
+            {
+                CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C0, CME_SCOM_EQ, dbData.value);
+
+            }
+            else
+            {
+                CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C1, CME_SCOM_EQ, dbData.value);
+            }
+
+            //Determine PMSR
+            localPS = (dbData.value >>
+                       ((MAX_QUADS - G_cme_pstate_record.quadNum - 1) << 3)) & 0xFF;
+            pmsrData = (dbData.value << 8) & 0xFF00000000000000;
+            pmsrData |= ((uint64_t)localPS << 48) & 0x00FF000000000000;
+            PK_TRACE_INF("INTER0:C%d PMSR=0x%08x%08x\n", c, pmsrData >> 32, pmsrData);
+
             if(dbData.fields.cme_message_number0 == MSGID_DB0_START_PSTATE_BROADCAST)
             {
-                PK_TRACE("INTERCME_IN0: DB0 Start\n");
+                PK_TRACE("INTER0:C%d DB0 Start\n", c);
+                out64((CME_LCL_PMSRS0 + (c << 5)), pmsrData);
+
                 //Clear any pending PMCR interrupts
                 out32_sh(CME_LCL_EISR_CLR, BIT32(2) >> c);
                 out32_sh(CME_LCL_EIMR_CLR, BIT32(2) >> c);//Enable PMCR0/1
+
             }
             else if(dbData.fields.cme_message_number0 == MSGID_DB0_GLOBAL_ACTUAL_BROADCAST)
             {
-                PK_TRACE("INTERCME_IN0: DB0 GlbBcast\n");
-                localPS = (dbData.value >>
-                           ((MAX_QUADS - G_cme_pstate_record.quadNum - 1) << 8)) & 0xFF;
-                pmsrData = (dbData.value << 8) & 0xFF00000000000000;
-                pmsrData |= ((uint64_t)localPS << 48) & 0x00FF000000000000;
+                PK_TRACE("INTER0:C%d DB0 GlbBcast\n", c);
                 out64((CME_LCL_PMSRS0 + (c << 5)), pmsrData);
-                out32_sh(CME_LCL_EISR_CLR, BIT32(4) >> c);//Clear DB0_C0
             }
             else if(dbData.fields.cme_message_number0 == MSGID_DB0_STOP_PSTATE_BROADCAST)
             {
-                PK_TRACE("INTERCME_IN0: DB0 Stop\n");
-                out32_sh(CME_LCL_EIMR_OR,  BIT32(2) >> c);//Enable PMCR0/1
+                PK_TRACE("INTER0:C%d DB0 Stop\n");
+                out32_sh(CME_LCL_EIMR_OR,  BIT32(2) >> c);//Disable PMCR0/1
             }
             else
             {
                 pk_halt();
             }
+
+            out32_sh(CME_LCL_EISR_CLR, BIT32(4) >> c);//Clear DB0_C0/C1
         }
     }
 
@@ -95,5 +112,6 @@ void p9_cme_pstate_intercme_in0_handler(void* arg, PkIrqId irq)
     out32(CME_LCL_EISR_CLR, BIT32(7));//Clear InterCME_IN0
 
     pk_irq_vec_restore(&ctx);
-    PK_TRACE("INTERCME_IN0: Exit\n");
+
+    PK_TRACE("INTER0: Exit\n");
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
index 166a817e..e553dfba 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
@@ -55,8 +55,8 @@ cme_pstate_db_data_t G_db_thread_data;
 
 //\todo Use PState Parameter Block structures. RTC
 extern global_pstate_table_t G_gpst;
-extern freq_2_idx_entry_t G_freq2idx[NUM_FREQ_REGIONS];
-extern uint16_t G_cgm_table[CGM_TRANSITIONS];
+//extern freq_2_idx_entry_t G_freq2idx[NUM_FREQ_REGIONS];
+//extern uint16_t G_cgm_table[CGM_TRANSITIONS];
 extern uint8_t G_resclkEnabled;
 extern cme_header_t* G_cme_header;
 
@@ -70,6 +70,7 @@ inline void p9_cme_pstate_db0_suspend(cppm_cmedb0_t dbData, uint32_t cme_flags);
 inline void p9_cme_pstate_freq_update(uint64_t dbData);
 inline void p9_cme_pstate_resclk_update();
 inline void p9_cme_pstate_pmsr_updt(uint64_t dbData, uint32_t cme_flags);
+inline void p9_cme_pstate_notify_sib();
 
 //
 //Doorbell0 interrupt handler
@@ -77,7 +78,9 @@ inline void p9_cme_pstate_pmsr_updt(uint64_t dbData, uint32_t cme_flags);
 //Only enabled on QuadManager-CME
 void p9_cme_pstate_db_handler(void* arg, PkIrqId irq)
 {
+    PK_TRACE_INF("DB_HDL: Entered\n");
     pk_semaphore_post((PkSemaphore*)arg);
+    PK_TRACE_INF("DB_HDL: Exited\n");
 }
 
 //
@@ -85,7 +88,7 @@ void p9_cme_pstate_db_handler(void* arg, PkIrqId irq)
 //
 void p9_cme_pstate_db_thread(void* arg)
 {
-    PK_TRACE_INF("DB_TH: Started\n");
+    PK_TRACE("DB_TH: Started\n");
     uint32_t cme_flags;
     PkMachineContext  ctx;
     uint32_t pir;
@@ -175,7 +178,6 @@ void p9_cme_pstate_db_thread(void* arg)
         g_eimr_override |= BIT64(37);
         g_eimr_override |= BIT64(36);
 
-        while(1) {}
     }
 
     //Doorbell Thread(this thread) will continue to run on
@@ -185,7 +187,7 @@ void p9_cme_pstate_db_thread(void* arg)
     {
         pk_semaphore_create(&G_cme_pstate_record.sem[1], 0, 1);
 
-        PK_TRACE_INF("DB_TH: Inited\n");
+        PK_TRACE("DB_TH: Inited\n");
 
         while(1)
         {
@@ -277,6 +279,7 @@ inline void p9_cme_pstate_db0_start(cppm_cmedb0_t dbData, uint32_t cme_flags)
     //Pstate Update
 #if !SIMICS_TUNING
     p9_cme_pstate_freq_update(dbData.value);
+    p9_cme_pstate_notify_sib(); //Notify sibling
 #endif
 
     p9_cme_pstate_pmsr_updt(dbData.value, cme_flags);
@@ -330,13 +333,16 @@ inline void p9_cme_pstate_db0_glb_bcast(cppm_cmedb0_t dbData, uint32_t cme_flags
     }
 
     //Update analog
+    /*
     if (G_resclkEnabled)
     {
         p9_cme_pstate_resclk_update();
     }
+    */
 
 #if !SIMICS_TUNING
     p9_cme_pstate_freq_update(dbData.value);
+    p9_cme_pstate_notify_sib(); //Notify sibling
 #endif
     p9_cme_pstate_pmsr_updt(dbData.value, cme_flags);
 
@@ -378,6 +384,8 @@ inline void p9_cme_pstate_db0_suspend(cppm_cmedb0_t dbData, uint32_t cme_flags)
         out64(CME_LCL_EIMR_OR,  BIT64(35));//Disable PMCR1
     }
 
+    p9_cme_pstate_notify_sib(); //Notify sibling
+
     //\TODO RTC: 152965
     //Disable iVRM, move into bypass
     //Disable resonant clocking, move to non-resonant value
@@ -395,10 +403,38 @@ inline void p9_cme_pstate_db0_suspend(cppm_cmedb0_t dbData, uint32_t cme_flags)
 //
 inline void p9_cme_pstate_pmsr_updt(uint64_t dbData, uint32_t cme_flags)
 {
-    uint32_t intercme_acked;
-    uint64_t eisr, pmsrData;
+    PK_TRACE_INF("DB_TH: PMSR Enter\n");
+    uint64_t pmsrData;
     uint8_t localPS;
 
+    //Update PMSR
+    localPS = (dbData >>
+               ((MAX_QUADS - G_cme_pstate_record.quadNum - 1) << 3)) & 0xFF;
+    pmsrData = (dbData << 8) & 0xFF00000000000000;
+    pmsrData |= ((uint64_t)localPS << 48) & 0x00FF000000000000;
+
+    if (cme_flags & CME_FLAGS_CORE0_GOOD)
+    {
+        PK_TRACE_INF("DB_TH: PMSR=0x%08x%08x\n", pmsrData >> 32, pmsrData);
+        out64(CME_LCL_PMSRS0, pmsrData);
+    }
+
+    if (cme_flags & CME_FLAGS_CORE1_GOOD)
+    {
+        PK_TRACE_INF("DB_TH: PMSR=0x%08x%08x\n", pmsrData >> 32, pmsrData);
+        out64(CME_LCL_PMSRS1, pmsrData);
+    }
+
+    PK_TRACE_INF("DB_TH: PMSR Exit\n");
+}
+
+inline void p9_cme_pstate_notify_sib()
+{
+    uint32_t intercme_acked;
+    uint64_t eisr;
+
+    PK_TRACE_INF("DB_TH: Notify Enter\n");
+
     //Notify sibling CME(if any)
     if (G_db_thread_data.siblingCMEFlag == 1)
     {
@@ -426,23 +462,7 @@ inline void p9_cme_pstate_pmsr_updt(uint64_t dbData, uint32_t cme_flags)
         out32(CME_LCL_EISR_CLR, BIT32(7));//Clear InterCME_IN0
     }
 
-    //Update PMSR
-    localPS = (dbData >>
-               ((MAX_QUADS - G_cme_pstate_record.quadNum - 1) << 3)) & 0xFF;
-    pmsrData = (dbData << 8) & 0xFF00000000000000;
-    pmsrData |= ((uint64_t)localPS << 48) & 0x00FF000000000000;
-
-    if (cme_flags & CME_FLAGS_CORE0_GOOD)
-    {
-        PK_TRACE_INF("DB_TH: PMSR=0x%08x%08x\n", pmsrData >> 32, pmsrData);
-        out64(CME_LCL_PMSRS0, pmsrData);
-    }
-
-    if (cme_flags & CME_FLAGS_CORE1_GOOD)
-    {
-        PK_TRACE_INF("DB_TH: PMSR=0x%08x%08x\n", pmsrData >> 32, pmsrData);
-        out64(CME_LCL_PMSRS1, pmsrData);
-    }
+    PK_TRACE_INF("DB_TH: Notify Exit\n");
 }
 
 //
@@ -452,19 +472,20 @@ inline void p9_cme_pstate_freq_update(uint64_t dbData)
 {
     PK_TRACE_INF("DB_TH: Freq Updt Enter\n");
     uint8_t localPS = (dbData >>
-                       ((MAX_QUADS - G_cme_pstate_record.quadNum - 1) * 8)) & 0xFF;
+                       ((MAX_QUADS - G_cme_pstate_record.quadNum - 1) << 3)) & 0xFF;
 
     PK_TRACE_INF("DB_TH: DBData=0x%08x%08x\n", dbData >> 32, dbData);
     PK_TRACE_INF("DB_TH: Dpll0=0x%x\n", G_db_thread_data.dpll_pstate0_value);
     //Adjust DPLL
+
     cppm_ippmcmd_t  cppm_ippmcmd;
     qppm_dpll_freq_t dpllFreq;
 
     //Write new value of DPLL using INTERPPM
     dpllFreq.value = 0;
-    dpllFreq.fields.fmax  = (uint16_t)(G_db_thread_data.dpll_pstate0_value - localPS) << 3;
-    dpllFreq.fields.fmult = (uint16_t)(G_db_thread_data.dpll_pstate0_value - localPS) << 3;
-    dpllFreq.fields.fmin  = (uint16_t)(G_db_thread_data.dpll_pstate0_value - localPS) << 3;
+    dpllFreq.fields.fmax  = (uint16_t)(G_db_thread_data.dpll_pstate0_value - localPS);
+    dpllFreq.fields.fmult = (uint16_t)(G_db_thread_data.dpll_pstate0_value - localPS);
+    dpllFreq.fields.fmin  = (uint16_t)(G_db_thread_data.dpll_pstate0_value - localPS);
     CME_PUTSCOM(CPPM_IPPMWDATA, G_db_thread_data.cmeMaskGoodCore, dpllFreq.value);
     cppm_ippmcmd.value = 0;
     cppm_ippmcmd.fields.qppm_reg = QPPM_DPLL_FREQ & 0x000000ff;
@@ -476,6 +497,7 @@ inline void p9_cme_pstate_freq_update(uint64_t dbData)
 //
 //p9_cme_pstate_resclk_update
 //
+/*
 inline void p9_cme_pstate_resclk_update()
 {
     uint64_t val;
@@ -521,3 +543,5 @@ inline void p9_cme_pstate_resclk_update()
 #endif
     }
 }
+
+*/
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c
index f76eec79..d6ac4ae5 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c
@@ -32,13 +32,14 @@
 /// \brief OCC level voltage change driver
 ///
 ///
-/// Creator: Chris Jones & Michael Olsen
-///
 
 #include "pk.h"
 #include "avs_driver.h"
-//#include "pstate.h"
+#include "p9_pgpe_gppb.h"
+
+#define CLOCK_SPIVID_MHZ        10 //\todo determine if this should come from attribute
 
+extern GlobalPstateParmBlock* G_gppb;
 
 //#################################################################################################
 // Function which generates a 3 bit CRC value for 29 bit data
@@ -137,7 +138,7 @@ uint8_t driveWrite(uint32_t CmdDataType, uint32_t CmdData)
     uint8_t  rc = 0;
     uint32_t ocbRegWriteData = 0;
 
-    uint32_t RailSelect  = 0xF;
+    uint32_t RailSelect  = 0;
     uint32_t StartCode   = 1;
     uint32_t CmdType     = 0; // 0:write+commit, 1:write+hold, 2: d/c, 3:read
     uint32_t CmdGroup    = 0;
@@ -157,6 +158,7 @@ uint8_t driveWrite(uint32_t CmdDataType, uint32_t CmdData)
     ocbRegWriteData = ocbRegWriteData | CRC;
 
     // Send frame
+    //PK_TRACE_DBG("RegWrite=0x%x", ocbRegWriteData);
     out32(OCB_O2SWD0A, ocbRegWriteData);
 
     // Wait on o2s_ongoing = 0
@@ -175,7 +177,7 @@ uint8_t driveRead(uint32_t CmdDataType, uint32_t* CmdData)
     uint32_t ocbRegReadData = 0;
     uint32_t ocbRegWriteData = 0;
 
-    uint32_t RailSelect  = 0xF;
+    uint32_t RailSelect  = 0;
     uint32_t StartCode   = 1;
     uint32_t CmdType     = 3; // 0:write+commit, 1:write+hold, 2: d/c, 3:read
     uint32_t CmdGroup    = 0;
@@ -208,6 +210,7 @@ uint8_t driveRead(uint32_t CmdDataType, uint32_t* CmdData)
 
     // Read returned voltage value from Read frame
     ocbRegReadData = in32(OCB_O2SRD0A);
+    PK_TRACE_DBG("RegRead=0x%x", ocbRegReadData);
     *CmdData = (ocbRegReadData >> 8) & 0x0000FFFF;
 
     return rc;
@@ -220,20 +223,21 @@ uint8_t driveRead(uint32_t CmdDataType, uint32_t* CmdData)
 void external_voltage_control_init(uint32_t* vext_read_mv)
 {
     uint8_t   rc = 0;
-    uint32_t  ocbRegReadData = 0;
-    uint32_t  ocbRegWriteData = 0;
     uint32_t  CmdDataRead = 0;
 
-#if EPM_P9_TUNING
+//#if EPM_P9_TUNING
 // We do not need to initialize O2S and AVS slave in product
 //   because this is done in istep 6. But for EPM, we need to do it.
-#define CLOCK_NEST_MHZ          2400
+//\todo Read from Parameter Block. These are attributes
 #define CLOCK_SPIVID_MHZ        10
-    uint32_t  O2SCTRLF_value = 0b10000010000011111100000000000000;
-    uint32_t  O2SCTRLS_value = 0b00000000000010000000000000000000;
-    uint32_t  O2SCTRL2_value = 0b00000000000000000000000000000000;
-    uint32_t  O2SCTRL1_value = 0b10000000000000000100000000000000 |
-                               (CLOCK_NEST_MHZ / (8 * CLOCK_SPIVID_MHZ) - 1) << 18; // Divider=0b11101
+    PK_TRACE_DBG("NestFreq=0x%x", G_gppb->nest_frequency_mhz);
+    uint32_t  ocbRegReadData = 0;
+    uint32_t  ocbRegWriteData = 0;
+    uint32_t  O2SCTRLF_value = 0b10000010000011111100000000000000; //0x820FC000
+    uint32_t  O2SCTRLS_value = 0b00000000000010000000000000000000; //0x00080000
+    uint32_t  O2SCTRL2_value = 0b00000000000000000000000000000000; //0x00000000
+    uint32_t  O2SCTRL1_value = 0b10010000000000000100000000000000 |
+                               (G_gppb->nest_frequency_mhz / (8 * CLOCK_SPIVID_MHZ) - 1) << 18;
 
     //
     // OCI to SPIPMBus (O2S) bridge initialization
@@ -275,40 +279,42 @@ void external_voltage_control_init(uint32_t* vext_read_mv)
         pk_halt();
     }
 
-#endif
+//#endif
 
     //
     // Set rail Vout transition rate (slew-rate)
     //
+    /*
+        // Drive write transaction with a target slew-rate on specific rail and wait on o2s_ongoing=0
+        rc = driveWrite(1, VEXT_SLEW_RATE_MVPERUS);
 
-    // Drive write transaction with a target slew-rate on specific rail and wait on o2s_ongoing=0
-    rc = driveWrite(1, VEXT_SLEW_RATE_MVPERUS);
-
-    if (rc)
-    {
-        pk_halt();
-    }
+        if (rc)
+        {
+            PK_TRACE_DBG("Slew-rate driveWrite FAIL");
+            pk_halt();
+        }
 
-    // Drive read transaction to return slew-rate on the same rail and wait on o2s_ongoing=0
-    rc = driveRead(1, &CmdDataRead);
-
-    if (rc)
-    {
-        pk_halt();
-    }
+        // Drive read transaction to return slew-rate on the same rail and wait on o2s_ongoing=0
+        rc = driveRead(1, &CmdDataRead);
 
+        if (rc)
+        {
+            PK_TRACE_DBG("Slew-rate driveRead FAIL");
+            pk_halt();
+        }
+    */
 #if !EPM_P9_TUNING
-
-    if (CmdDataRead == VEXT_SLEW_RATE_MVPERUS)
-    {
-        MY_TRACE_DBG("Slew-rate write PASS");
-    }
-    else
-    {
-        MY_TRACE_ERR("Slew-rate write FAIL");
-        pk_halt();
-    }
-
+    /*
+        if (CmdDataRead == VEXT_SLEW_RATE_MVPERUS)
+        {
+            PK_TRACE_DBG("Slew-rate write PASS");
+        }
+        else
+        {
+            PK_TRACE_DBG("Slew-rate write FAIL %d",CmdDataRead);
+            pk_halt();
+        }
+    */
 #endif
 
     // Drive read transaction to return initial setting of rail voltage and wait on o2s_ongoing=0
@@ -316,6 +322,7 @@ void external_voltage_control_init(uint32_t* vext_read_mv)
 
     if (rc)
     {
+        PK_TRACE_DBG("Slew-rate driveRead Init FAIL");
         pk_halt();
     }
 
@@ -348,13 +355,14 @@ void external_voltage_control_write(uint32_t vext_write_mv)
 
     if (rc)
     {
+        PK_TRACE_DBG("Drive Read  driveRead FAIL");
         pk_halt();
     }
 
 
     if (CmdDataRead != vext_write_mv)
     {
-        MY_TRACE_ERR("Vext write FAIL: Read=%d != Write=%d", CmdDataRead, vext_write_mv);
+        PK_TRACE_DBG("Vext write FAIL: Read=%d != Write=%d", CmdDataRead, vext_write_mv);
         pk_halt();
     }
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_boot_temp.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_boot_temp.c
index 9368d5b5..97d6db0b 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_boot_temp.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_boot_temp.c
@@ -84,7 +84,7 @@ void p9_pgpe_boot_gppb_init()
     GlobalPstateParmBlock* gppb = (GlobalPstateParmBlock*)gppb_sram_offset;
     gppb->magic = PSTATE_PARMSBLOCK_MAGIC;
     gppb->options.options = 0;
-    gppb->reference_frequency_khz = 4150000;
+    gppb->reference_frequency_khz = 2800000;
     gppb->frequency_step_khz = 16667;
     gppb->ext_vrm_transition_start_ns = 50;
     gppb->ext_vrm_transition_rate_inc_uv_per_us = 10000;
@@ -93,24 +93,24 @@ void p9_pgpe_boot_gppb_init()
     gppb->ext_vrm_step_size_mv = 50;
     gppb->nest_frequency_mhz = 2000;
 
-    gppb->operating_points[ULTRA].frequency_mhz = 4150;
-    gppb->operating_points[ULTRA].vdd_mv = 1100;
+    gppb->operating_points[ULTRA].frequency_mhz = 2800;
+    gppb->operating_points[ULTRA].vdd_mv = 1000;
     gppb->operating_points[ULTRA].pstate = 0;
     gppb->operating_points[ULTRA].idd_100ma = 2;
     gppb->operating_points[ULTRA].ics_100ma = 1;
-    gppb->operating_points[TURBO].frequency_mhz = 3816;
-    gppb->operating_points[TURBO].vdd_mv = 1000;
-    gppb->operating_points[TURBO].pstate = 20;
+    gppb->operating_points[TURBO].frequency_mhz = 2600;
+    gppb->operating_points[TURBO].vdd_mv = 900;
+    gppb->operating_points[TURBO].pstate = 12;
     gppb->operating_points[TURBO].idd_100ma = 2;
     gppb->operating_points[TURBO].ics_100ma = 1;
-    gppb->operating_points[NOMINAL].frequency_mhz = 3400;
-    gppb->operating_points[NOMINAL].vdd_mv = 875;
-    gppb->operating_points[NOMINAL].pstate = 45;
+    gppb->operating_points[NOMINAL].frequency_mhz = 2400;
+    gppb->operating_points[NOMINAL].vdd_mv = 825;
+    gppb->operating_points[NOMINAL].pstate = 24;
     gppb->operating_points[NOMINAL].idd_100ma = 2;
     gppb->operating_points[NOMINAL].ics_100ma = 1;
-    gppb->operating_points[POWERSAVE].frequency_mhz = 2067;
-    gppb->operating_points[POWERSAVE].vdd_mv = 675;
-    gppb->operating_points[POWERSAVE].pstate = 125;
+    gppb->operating_points[POWERSAVE].frequency_mhz = 2000;
+    gppb->operating_points[POWERSAVE].vdd_mv = 750;
+    gppb->operating_points[POWERSAVE].pstate = 48;
     gppb->operating_points[POWERSAVE].idd_100ma = 2;
     gppb->operating_points[POWERSAVE].ics_100ma = 1;
 
@@ -151,8 +151,8 @@ void p9_pgpe_boot_gppb_init()
     gppb->vdn_sysparm.distloss_uohm = 10;
     gppb->vdn_sysparm.distoffset_uv = 10;
 
-    gppb->safe_voltage_mv = 875;
-    gppb->safe_frequency_khz = 3400;
+    gppb->safe_voltage_mv = 825;
+    gppb->safe_frequency_khz = 2400;
     gppb->vrm_stepdelay_range = 1;
     gppb->vrm_stepdelay_value = 12;
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
index 7d4d652a..b9ce3e9a 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
@@ -46,6 +46,7 @@ void p9_pgpe_fit_init()
 {
     uint16_t freq = G_gppb->nest_frequency_mhz;
 
+    PK_TRACE_DBG("Fit NestFreq=0x%x", G_gppb->nest_frequency_mhz);
     //Set fit count threshold
     G_fit_count_threshold = (freq < 1049) ? 7 :
                             (freq < 1180) ? 8 :
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
index a49f009f..2d89aa35 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
@@ -32,7 +32,7 @@
 //Generated PState Table in SRAM
 GeneratedPstateInfo G_gpi;
 extern PgpeHeader_t* G_pgpe_header_data;
-extern VpdOperatingPoint G_operating_points[NUM_VPD_PTS_SET][VPD_PV_POINTS];
+//extern VpdOperatingPoint gppb->operating_points_set[NUM_VPD_PTS_SET][VPD_PV_POINTS];
 
 //
 //Local function prototypes
@@ -48,7 +48,7 @@ void p9_pgpe_gen_pstate_info()
 {
     PK_TRACE_DBG("> p9_pgpe_gen_pstate_info to memory 0x%X",
                  (uint32_t)G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset);
-    int p;
+    //int p;
     //Get GlobalPstateParmBlock offset from pgpe_header
     uint32_t* pstate_tbl_memory_offset  = G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset;
     uint32_t pstate_tbl_length = G_pgpe_header_data->g_pgpe_gen_pstables_length;
@@ -58,21 +58,22 @@ void p9_pgpe_gen_pstate_info()
     //Fill out GeneratedPstateInfo structure
     G_gpi.magic = GEN_PSTATES_TBL_MAGIC;
     G_gpi.globalppb = *gppb;
-    G_gpi.pstate0_frequency_khz = G_operating_points[VPD_PT_SET_BIASED_SYSP][ULTRA].frequency_mhz * 1000;
+    G_gpi.pstate0_frequency_khz = gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][ULTRA].frequency_mhz * 1000;
 
-    G_gpi.highest_pstate = ((G_operating_points[VPD_PT_SET_BIASED_SYSP][ULTRA].frequency_mhz -
-                             G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].frequency_mhz) * 1000) / gppb->frequency_step_khz;
+    G_gpi.highest_pstate = ((gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][ULTRA].frequency_mhz -
+                             gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].frequency_mhz) * 1000) / gppb->frequency_step_khz;
 
     //Generate tables
     p9_pgpe_gen_raw_pstates(gppb, &G_gpi);
     p9_pgpe_gen_biased_pstates(gppb, &G_gpi);
 
+    /*
     for (p = 0; p < VPD_PV_POINTS; p++)
     {
-        G_gpi.operating_points_biased[p] = G_operating_points[VPD_PT_SET_BIASED][p];
-        G_gpi.operating_points_sysp[p] = G_operating_points[VPD_PT_SET_SYSP][p];
-        G_gpi.operating_points_biased_sysp[p] = G_operating_points[VPD_PT_SET_BIASED_SYSP][p];
-    }
+        G_gpi.operating_points_biased[p] = gppb->operating_points_set[VPD_PT_SET_BIASED][p];
+        G_gpi.operating_points_sysp[p] = gppb->operating_points_set[VPD_PT_SET_SYSP][p];
+        G_gpi.operating_points_biased_sysp[p] = gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][p];
+    }*/
 
     //Write Generated Pstate out to main memory(HOMER/PPMR.PstateTable)
     uint32_t* gpi = (uint32_t*)&G_gpi;
@@ -98,7 +99,7 @@ void p9_pgpe_gen_raw_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* g
     PK_TRACE_DBG(">> p9_pgpe_gen_raw_pstates");
     int32_t p;
     uint32_t freq_khz_offset = 0, highest_pstate;
-    highest_pstate = G_operating_points[VPD_PT_SET_SYSP][POWERSAVE].pstate;
+    highest_pstate = gppb->operating_points_set[VPD_PT_SET_SYSP][POWERSAVE].pstate;
 
     for (p = 0; p <= highest_pstate; p++)
     {
@@ -129,7 +130,7 @@ void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo
     PK_TRACE_DBG(">> p9_pgpe_gen_biased_pstates");
     int32_t p;
     uint32_t freq_khz_offset = 0, highest_pstate;
-    highest_pstate = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+    highest_pstate = gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
 
     for (p = 0; p <= highest_pstate; p++)
     {
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
index 177d5875..684cfd62 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
@@ -28,9 +28,8 @@
 //Global pointer to GlobalPstateParmBlock
 GlobalPstateParmBlock* G_gppb;
 
-//Global array to store calculated slopes
-VpdOperatingPoint G_operating_points[NUM_VPD_PTS_SET][VPD_PV_POINTS];
-uint8_t G_pstate0_dpll_value;
+//VpdOperatingPoint *G_gppb->operating_points_set[NUM_VPD_PTS_SET][VPD_PV_POINTS];
+uint32_t G_pstate0_dpll_value;
 uint32_t G_ext_vrm_inc_rate_mult_usperus;
 uint32_t G_ext_vrm_dec_rate_mult_usperus;
 extern PgpeHeader_t* G_pgpe_header_data;
@@ -65,11 +64,16 @@ void p9_pgpe_gppb_init()
     G_pstate0_dpll_value = ((G_gppb->reference_frequency_khz + (G_gppb->frequency_step_khz - 1)) /
                             G_gppb->frequency_step_khz);
 
+    PK_TRACE_INF("GPP: DPLL0Value=0x%x", G_pstate0_dpll_value );
+    PK_TRACE_INF("GPP: PowerSave PS=0x%x", G_gppb->operating_points[POWERSAVE].pstate );
+    PK_TRACE_INF("GPP: Nominal PS=0x%x", G_gppb->operating_points[NOMINAL].pstate );
     //External VRM increasing rate in us/uv
     G_ext_vrm_inc_rate_mult_usperus = 1 / G_gppb->ext_vrm_transition_rate_inc_uv_per_us;
 
     //External VRM decreasing rate in us/uv
     G_ext_vrm_dec_rate_mult_usperus = 1 / G_gppb->ext_vrm_transition_rate_dec_uv_per_us;
+
+    //G_gppb->nest_frequency_mhz = 1866;
 }
 
 //
@@ -82,12 +86,12 @@ void p9_pgpe_gppb_compute_vpd_pts()
     //RAW POINTS. We just copy them as is
     for (p = 0; p < VPD_PV_POINTS; p++)
     {
-        G_operating_points[VPD_PT_SET_RAW][p].vdd_mv = G_gppb->operating_points[p].vdd_mv ;
-        G_operating_points[VPD_PT_SET_RAW][p].vcs_mv = G_gppb->operating_points[p].vcs_mv;
-        G_operating_points[VPD_PT_SET_RAW][p].idd_100ma = G_gppb->operating_points[p].idd_100ma;
-        G_operating_points[VPD_PT_SET_RAW][p].ics_100ma = G_gppb->operating_points[p].ics_100ma;
-        G_operating_points[VPD_PT_SET_RAW][p].frequency_mhz = G_gppb->operating_points[p].frequency_mhz;
-        G_operating_points[VPD_PT_SET_RAW][p].pstate = G_gppb->operating_points[p].pstate;
+        G_gppb->operating_points_set[VPD_PT_SET_RAW][p].vdd_mv = G_gppb->operating_points[p].vdd_mv ;
+        G_gppb->operating_points_set[VPD_PT_SET_RAW][p].vcs_mv = G_gppb->operating_points[p].vcs_mv;
+        G_gppb->operating_points_set[VPD_PT_SET_RAW][p].idd_100ma = G_gppb->operating_points[p].idd_100ma;
+        G_gppb->operating_points_set[VPD_PT_SET_RAW][p].ics_100ma = G_gppb->operating_points[p].ics_100ma;
+        G_gppb->operating_points_set[VPD_PT_SET_RAW][p].frequency_mhz = G_gppb->operating_points[p].frequency_mhz;
+        G_gppb->operating_points_set[VPD_PT_SET_RAW][p].pstate = G_gppb->operating_points[p].pstate;
     }
 
     //SYSTEM PARAMS APPLIED POINTS
@@ -95,39 +99,40 @@ void p9_pgpe_gppb_compute_vpd_pts()
     //that integer division doesn't result in 0 for intermediate terms
     for (p = 0; p < VPD_PV_POINTS; p++)
     {
-        G_operating_points[VPD_PT_SET_SYSP][p].vdd_mv =
+        G_gppb->operating_points_set[VPD_PT_SET_SYSP][p].vdd_mv =
             (G_gppb->operating_points[p].vdd_mv * 1000 +
              ((G_gppb->operating_points[p].idd_100ma * 100) * (G_gppb->vdd_sysparm.loadline_uohm +
                      G_gppb->vdd_sysparm.distloss_uohm)) +
              (G_gppb->vdd_sysparm.distoffset_uv)) / 1000 ;
-        G_operating_points[VPD_PT_SET_SYSP][p].vcs_mv =
+        G_gppb->operating_points_set[VPD_PT_SET_SYSP][p].vcs_mv =
             (G_gppb->operating_points[p].vcs_mv * 1000 +
              ((G_gppb->operating_points[p].ics_100ma * 100) * (G_gppb->vcs_sysparm.loadline_uohm +
                      G_gppb->vcs_sysparm.distloss_uohm)) +
              (G_gppb->vcs_sysparm.distoffset_uv)) / 1000 ;
-        G_operating_points[VPD_PT_SET_SYSP][p].idd_100ma = G_gppb->operating_points[p].idd_100ma;
-        G_operating_points[VPD_PT_SET_SYSP][p].ics_100ma = G_gppb->operating_points[p].ics_100ma;
-        G_operating_points[VPD_PT_SET_SYSP][p].frequency_mhz = G_gppb->operating_points[p].frequency_mhz;
-        G_operating_points[VPD_PT_SET_SYSP][p].pstate = G_gppb->operating_points[p].pstate;
+        G_gppb->operating_points_set[VPD_PT_SET_SYSP][p].idd_100ma = G_gppb->operating_points[p].idd_100ma;
+        G_gppb->operating_points_set[VPD_PT_SET_SYSP][p].ics_100ma = G_gppb->operating_points[p].ics_100ma;
+        G_gppb->operating_points_set[VPD_PT_SET_SYSP][p].frequency_mhz = G_gppb->operating_points[p].frequency_mhz;
+        G_gppb->operating_points_set[VPD_PT_SET_SYSP][p].pstate = G_gppb->operating_points[p].pstate;
     }
 
     //BIASED POINTS
     for (p = 0; p < VPD_PV_POINTS; p++)
     {
-        G_operating_points[VPD_PT_SET_BIASED][p].vdd_mv = (G_gppb->operating_points[p].vdd_mv *
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].vdd_mv = (G_gppb->operating_points[p].vdd_mv *
                 (200 + G_gppb->ext_biases[p].vdd_ext_hp)) / 200;
-        G_operating_points[VPD_PT_SET_BIASED][p].vcs_mv = (G_gppb->operating_points[p].vcs_mv *
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].vcs_mv = (G_gppb->operating_points[p].vcs_mv *
                 (200 + G_gppb->ext_biases[p].vcs_ext_hp)) / 200;
-        G_operating_points[VPD_PT_SET_BIASED][p].idd_100ma = G_gppb->operating_points[p].idd_100ma;
-        G_operating_points[VPD_PT_SET_BIASED][p].ics_100ma = G_gppb->operating_points[p].ics_100ma;
-        G_operating_points[VPD_PT_SET_BIASED][p].frequency_mhz = (G_gppb->operating_points[p].frequency_mhz *
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].idd_100ma = G_gppb->operating_points[p].idd_100ma;
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].ics_100ma = G_gppb->operating_points[p].ics_100ma;
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].frequency_mhz = (G_gppb->operating_points[p].frequency_mhz *
                 (200 + G_gppb->ext_biases[p].frequency_hp)) / 200;
     }
 
     for (p = 0; p < VPD_PV_POINTS; p++)
     {
-        G_operating_points[VPD_PT_SET_BIASED][p].pstate =
-            ((G_operating_points[VPD_PT_SET_BIASED][ULTRA].frequency_mhz - G_operating_points[VPD_PT_SET_BIASED][p].frequency_mhz) *
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].pstate =
+            ((G_gppb->operating_points_set[VPD_PT_SET_BIASED][ULTRA].frequency_mhz -
+              G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].frequency_mhz) *
              1000) /
             G_gppb->frequency_step_khz;
     }
@@ -137,20 +142,24 @@ void p9_pgpe_gppb_compute_vpd_pts()
     //that integer division doesn't result in 0 for intermediate terms
     for (p = 0; p < VPD_PV_POINTS; p++)
     {
-        G_operating_points[VPD_PT_SET_BIASED_SYSP][p].vdd_mv =
-            ((G_operating_points[VPD_PT_SET_BIASED][p].vdd_mv * 1000) +
-             ((G_operating_points[VPD_PT_SET_BIASED][p].idd_100ma * 100) *
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][p].vdd_mv =
+            ((G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].vdd_mv * 1000) +
+             ((G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].idd_100ma * 100) *
               (G_gppb->vdd_sysparm.loadline_uohm + G_gppb->vdd_sysparm.distloss_uohm)) +
              (G_gppb->vdd_sysparm.distoffset_uv)) / 1000 ;
-        G_operating_points[VPD_PT_SET_BIASED_SYSP][p].vcs_mv =
-            ((G_operating_points[VPD_PT_SET_BIASED][p].vcs_mv * 1000) +
-             ((G_operating_points[VPD_PT_SET_BIASED][p].ics_100ma * 100) *
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][p].vcs_mv =
+            ((G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].vcs_mv * 1000) +
+             ((G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].ics_100ma * 100) *
               (G_gppb->vcs_sysparm.loadline_uohm + G_gppb->vcs_sysparm.distloss_uohm)) +
              (G_gppb->vcs_sysparm.distoffset_uv)) / 1000 ;
-        G_operating_points[VPD_PT_SET_BIASED_SYSP][p].idd_100ma = G_operating_points[VPD_PT_SET_BIASED][p].idd_100ma;
-        G_operating_points[VPD_PT_SET_BIASED_SYSP][p].ics_100ma = G_operating_points[VPD_PT_SET_BIASED][p].ics_100ma;
-        G_operating_points[VPD_PT_SET_BIASED_SYSP][p].frequency_mhz = G_operating_points[VPD_PT_SET_BIASED][p].frequency_mhz;
-        G_operating_points[VPD_PT_SET_BIASED_SYSP][p].pstate = G_operating_points[VPD_PT_SET_BIASED][p].pstate;
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][p].idd_100ma =
+            G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].idd_100ma;
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][p].ics_100ma =
+            G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].ics_100ma;
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][p].frequency_mhz =
+            G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].frequency_mhz;
+        G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][p].pstate =
+            G_gppb->operating_points_set[VPD_PT_SET_BIASED][p].pstate;
     }
 }
 
@@ -181,90 +190,94 @@ void p9_pgpe_gppb_compute_PsV_slopes()
     //RAW VPD PTS SLOPES
     //
     //convert to a fixed-point number
-    eVidFP[POWERSAVE] = G_operating_points[VPD_PT_SET_RAW][POWERSAVE].vdd_mv << EVID_SLOPE_FP_SHIFT;
-    eVidFP[NOMINAL] = G_operating_points[VPD_PT_SET_RAW][NOMINAL].vdd_mv << EVID_SLOPE_FP_SHIFT;
-    eVidFP[TURBO] = G_operating_points[VPD_PT_SET_RAW][TURBO].vdd_mv << EVID_SLOPE_FP_SHIFT;
-    eVidFP[ULTRA] = G_operating_points[VPD_PT_SET_RAW][ULTRA].vdd_mv << EVID_SLOPE_FP_SHIFT;
+    eVidFP[POWERSAVE] = G_gppb->operating_points_set[VPD_PT_SET_RAW][POWERSAVE].vdd_mv << EVID_SLOPE_FP_SHIFT;
+    eVidFP[NOMINAL] = G_gppb->operating_points_set[VPD_PT_SET_RAW][NOMINAL].vdd_mv << EVID_SLOPE_FP_SHIFT;
+    eVidFP[TURBO] = G_gppb->operating_points_set[VPD_PT_SET_RAW][TURBO].vdd_mv << EVID_SLOPE_FP_SHIFT;
+    eVidFP[ULTRA] = G_gppb->operating_points_set[VPD_PT_SET_RAW][ULTRA].vdd_mv << EVID_SLOPE_FP_SHIFT;
 
     //Calculate slopes
     tmp = (uint32_t)(eVidFP[NOMINAL] - eVidFP[POWERSAVE]) /
-          (uint32_t)(-G_operating_points[VPD_PT_SET_RAW][NOMINAL].pstate + G_operating_points[VPD_PT_SET_RAW][POWERSAVE].pstate);
+          (uint32_t)(-G_gppb->operating_points_set[VPD_PT_SET_RAW][NOMINAL].pstate +
+                     G_gppb->operating_points_set[VPD_PT_SET_RAW][POWERSAVE].pstate);
     G_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL] = tmp;
 
     tmp = (uint32_t)(eVidFP[TURBO] - eVidFP[NOMINAL]) /
-          (uint32_t)(-G_operating_points[VPD_PT_SET_RAW][TURBO].pstate + G_operating_points[VPD_PT_SET_RAW][NOMINAL].pstate);
+          (uint32_t)(-G_gppb->operating_points_set[VPD_PT_SET_RAW][TURBO].pstate +
+                     G_gppb->operating_points_set[VPD_PT_SET_RAW][NOMINAL].pstate);
     G_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO] = tmp;
 
     tmp = (uint32_t)(eVidFP[ULTRA] - eVidFP[TURBO]) /
-          (uint32_t)(-G_operating_points[VPD_PT_SET_RAW][ULTRA].pstate + G_operating_points[VPD_PT_SET_RAW][TURBO].pstate);
+          (uint32_t)(-G_gppb->operating_points_set[VPD_PT_SET_RAW][ULTRA].pstate +
+                     G_gppb->operating_points_set[VPD_PT_SET_RAW][TURBO].pstate);
     G_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA] = tmp;
 
     //Calculate inverted slopes
-    tmp =  (uint32_t)((-G_operating_points[VPD_PT_SET_RAW][NOMINAL].pstate +
-                       G_operating_points[VPD_PT_SET_RAW][POWERSAVE].pstate) <<
+    tmp =  (uint32_t)((-G_gppb->operating_points_set[VPD_PT_SET_RAW][NOMINAL].pstate +
+                       G_gppb->operating_points_set[VPD_PT_SET_RAW][POWERSAVE].pstate) <<
                       EVID_SLOPE_FP_SHIFT)
-           / (uint32_t) (G_operating_points[VPD_PT_SET_RAW][NOMINAL].vdd_mv -
-                         G_operating_points[VPD_PT_SET_RAW][POWERSAVE].vdd_mv);
+           / (uint32_t) (G_gppb->operating_points_set[VPD_PT_SET_RAW][NOMINAL].vdd_mv -
+                         G_gppb->operating_points_set[VPD_PT_SET_RAW][POWERSAVE].vdd_mv);
     G_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL] = tmp;
 
-    tmp =  (uint32_t)((-G_operating_points[VPD_PT_SET_RAW][TURBO].pstate +
-                       G_operating_points[VPD_PT_SET_RAW][NOMINAL].pstate) <<
+    tmp =  (uint32_t)((-G_gppb->operating_points_set[VPD_PT_SET_RAW][TURBO].pstate +
+                       G_gppb->operating_points_set[VPD_PT_SET_RAW][NOMINAL].pstate) <<
                       EVID_SLOPE_FP_SHIFT)
-           / (uint32_t) (G_operating_points[VPD_PT_SET_RAW][TURBO].vdd_mv -
-                         G_operating_points[VPD_PT_SET_RAW][NOMINAL].vdd_mv);
+           / (uint32_t) (G_gppb->operating_points_set[VPD_PT_SET_RAW][TURBO].vdd_mv -
+                         G_gppb->operating_points_set[VPD_PT_SET_RAW][NOMINAL].vdd_mv);
     G_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO] = tmp;
 
-    tmp =  (uint32_t)((-G_operating_points[VPD_PT_SET_RAW][ULTRA].pstate +
-                       G_operating_points[VPD_PT_SET_RAW][TURBO].pstate) <<
+    tmp =  (uint32_t)((-G_gppb->operating_points_set[VPD_PT_SET_RAW][ULTRA].pstate +
+                       G_gppb->operating_points_set[VPD_PT_SET_RAW][TURBO].pstate) <<
                       EVID_SLOPE_FP_SHIFT)
-           / (uint32_t) (G_operating_points[VPD_PT_SET_RAW][ULTRA].vdd_mv -
-                         G_operating_points[VPD_PT_SET_RAW][TURBO].vdd_mv);
+           / (uint32_t) (G_gppb->operating_points_set[VPD_PT_SET_RAW][ULTRA].vdd_mv -
+                         G_gppb->operating_points_set[VPD_PT_SET_RAW][TURBO].vdd_mv);
     G_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA] = tmp;
 
     //
     //BIASED VPD PTS SLOPES
     //
     //convert to fixed-point number
-    eVidFP[POWERSAVE] = G_operating_points[VPD_PT_SET_BIASED][POWERSAVE].vdd_mv << EVID_SLOPE_FP_SHIFT;
-    eVidFP[NOMINAL] = G_operating_points[VPD_PT_SET_BIASED][NOMINAL].vdd_mv << EVID_SLOPE_FP_SHIFT;
-    eVidFP[TURBO] = G_operating_points[VPD_PT_SET_BIASED][TURBO].vdd_mv << EVID_SLOPE_FP_SHIFT;
-    eVidFP[ULTRA] = G_operating_points[VPD_PT_SET_BIASED][ULTRA].vdd_mv << EVID_SLOPE_FP_SHIFT;
+    eVidFP[POWERSAVE] = G_gppb->operating_points_set[VPD_PT_SET_BIASED][POWERSAVE].vdd_mv << EVID_SLOPE_FP_SHIFT;
+    eVidFP[NOMINAL] = G_gppb->operating_points_set[VPD_PT_SET_BIASED][NOMINAL].vdd_mv << EVID_SLOPE_FP_SHIFT;
+    eVidFP[TURBO] = G_gppb->operating_points_set[VPD_PT_SET_BIASED][TURBO].vdd_mv << EVID_SLOPE_FP_SHIFT;
+    eVidFP[ULTRA] = G_gppb->operating_points_set[VPD_PT_SET_BIASED][ULTRA].vdd_mv << EVID_SLOPE_FP_SHIFT;
 
     //Calculate slopes
     tmp = (uint32_t)(eVidFP[NOMINAL] - eVidFP[POWERSAVE]) /
-          (uint32_t)(-G_operating_points[VPD_PT_SET_BIASED][NOMINAL].pstate +
-                     G_operating_points[VPD_PT_SET_BIASED][POWERSAVE].pstate);
+          (uint32_t)(-G_gppb->operating_points_set[VPD_PT_SET_BIASED][NOMINAL].pstate +
+                     G_gppb->operating_points_set[VPD_PT_SET_BIASED][POWERSAVE].pstate);
     G_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL] = tmp;
 
     tmp = (uint32_t)(eVidFP[TURBO] - eVidFP[NOMINAL]) /
-          (uint32_t)(-G_operating_points[VPD_PT_SET_BIASED][TURBO].pstate +
-                     G_operating_points[VPD_PT_SET_BIASED][NOMINAL].pstate);
+          (uint32_t)(-G_gppb->operating_points_set[VPD_PT_SET_BIASED][TURBO].pstate +
+                     G_gppb->operating_points_set[VPD_PT_SET_BIASED][NOMINAL].pstate);
     G_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO] = tmp;
 
     tmp = (uint32_t)(eVidFP[ULTRA] - eVidFP[TURBO]) /
-          (uint32_t)(-G_operating_points[VPD_PT_SET_BIASED][ULTRA].pstate + G_operating_points[VPD_PT_SET_BIASED][TURBO].pstate);
+          (uint32_t)(-G_gppb->operating_points_set[VPD_PT_SET_BIASED][ULTRA].pstate +
+                     G_gppb->operating_points_set[VPD_PT_SET_BIASED][TURBO].pstate);
     G_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA] = tmp;
 
     //Calculate inverted slopes
-    tmp =  (uint32_t)((-G_operating_points[VPD_PT_SET_BIASED][NOMINAL].pstate +
-                       G_operating_points[VPD_PT_SET_BIASED][POWERSAVE].pstate) <<
+    tmp =  (uint32_t)((-G_gppb->operating_points_set[VPD_PT_SET_BIASED][NOMINAL].pstate +
+                       G_gppb->operating_points_set[VPD_PT_SET_BIASED][POWERSAVE].pstate) <<
                       EVID_SLOPE_FP_SHIFT)
-           / (uint32_t) (G_operating_points[VPD_PT_SET_BIASED][NOMINAL].vdd_mv -
-                         G_operating_points[VPD_PT_SET_BIASED][POWERSAVE].vdd_mv);
+           / (uint32_t) (G_gppb->operating_points_set[VPD_PT_SET_BIASED][NOMINAL].vdd_mv -
+                         G_gppb->operating_points_set[VPD_PT_SET_BIASED][POWERSAVE].vdd_mv);
     G_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL] = tmp;
 
-    tmp =  (uint32_t)((-G_operating_points[VPD_PT_SET_BIASED][TURBO].pstate +
-                       G_operating_points[VPD_PT_SET_BIASED][NOMINAL].pstate) <<
+    tmp =  (uint32_t)((-G_gppb->operating_points_set[VPD_PT_SET_BIASED][TURBO].pstate +
+                       G_gppb->operating_points_set[VPD_PT_SET_BIASED][NOMINAL].pstate) <<
                       EVID_SLOPE_FP_SHIFT)
-           / (uint32_t) (G_operating_points[VPD_PT_SET_BIASED][TURBO].vdd_mv -
-                         G_operating_points[VPD_PT_SET_BIASED][NOMINAL].vdd_mv);
+           / (uint32_t) (G_gppb->operating_points_set[VPD_PT_SET_BIASED][TURBO].vdd_mv -
+                         G_gppb->operating_points_set[VPD_PT_SET_BIASED][NOMINAL].vdd_mv);
     G_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO] = tmp;
 
-    tmp =  (uint32_t)((-G_operating_points[VPD_PT_SET_BIASED][ULTRA].pstate +
-                       G_operating_points[VPD_PT_SET_BIASED][TURBO].pstate) <<
+    tmp =  (uint32_t)((-G_gppb->operating_points_set[VPD_PT_SET_BIASED][ULTRA].pstate +
+                       G_gppb->operating_points_set[VPD_PT_SET_BIASED][TURBO].pstate) <<
                       EVID_SLOPE_FP_SHIFT)
-           / (uint32_t) (G_operating_points[VPD_PT_SET_BIASED][ULTRA].vdd_mv -
-                         G_operating_points[VPD_PT_SET_BIASED][TURBO].vdd_mv);
+           / (uint32_t) (G_gppb->operating_points_set[VPD_PT_SET_BIASED][ULTRA].vdd_mv -
+                         G_gppb->operating_points_set[VPD_PT_SET_BIASED][TURBO].vdd_mv);
     G_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA] = tmp;
 }
 
@@ -278,8 +291,8 @@ uint32_t p9_pgpe_gppb_intp_vdd_from_ps(Pstate ps, uint8_t vpd_pt_set, uint8_t vp
     uint32_t vdd;
     uint8_t r  = p9_pgpe_gppb_get_ps_region(ps, vpd_pt_set);
     vdd = (((G_gppb->PsVSlopes[vpd_slope_set][r]) *
-            (-ps + G_operating_points[vpd_pt_set][r].pstate)) >> EVID_SLOPE_FP_SHIFT)
-          + G_operating_points[vpd_pt_set][r].vdd_mv;
+            (-ps + G_gppb->operating_points_set[vpd_pt_set][r].pstate)) >> EVID_SLOPE_FP_SHIFT)
+          + G_gppb->operating_points_set[vpd_pt_set][r].vdd_mv;
 
     return vdd;
 }
@@ -291,11 +304,11 @@ uint32_t p9_pgpe_gppb_intp_vdd_from_ps(Pstate ps, uint8_t vpd_pt_set, uint8_t vp
 //
 uint8_t p9_pgpe_gppb_get_ps_region(Pstate ps, uint8_t vpd_pt_set)
 {
-    if (ps < G_operating_points[vpd_pt_set][TURBO].pstate)
+    if (ps < G_gppb->operating_points_set[vpd_pt_set][TURBO].pstate)
     {
         return REGION_TURBO_ULTRA;
     }
-    else if (ps > G_operating_points[vpd_pt_set][NOMINAL].pstate)
+    else if (ps > G_gppb->operating_points_set[vpd_pt_set][NOMINAL].pstate)
     {
         return REGION_POWERSAVE_NOMINAL;
     }
@@ -314,8 +327,8 @@ uint8_t p9_pgpe_gppb_intp_ps_from_ext_vdd(uint16_t ext_vdd)
     Pstate ps;
     uint8_t  r = p9_pgpe_gppb_get_ext_vdd_region(ext_vdd);
     ps = -(((G_gppb->VPsSlopes[VPD_SLOPES_BIASED][r]) *
-            (ext_vdd - G_operating_points[VPD_PT_SET_BIASED_SYSP][r].vdd_mv)) >> EVID_SLOPE_FP_SHIFT)
-         + G_operating_points[VPD_SLOPES_BIASED][r].pstate;
+            (ext_vdd - G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][r].vdd_mv)) >> EVID_SLOPE_FP_SHIFT)
+         + G_gppb->operating_points_set[VPD_SLOPES_BIASED][r].pstate;
     return ps;
 }
 
@@ -326,11 +339,11 @@ uint8_t p9_pgpe_gppb_intp_ps_from_ext_vdd(uint16_t ext_vdd)
 //
 uint8_t p9_pgpe_gppb_get_ext_vdd_region(uint32_t ext_vdd)
 {
-    if (ext_vdd >  G_operating_points[VPD_PT_SET_BIASED_SYSP][TURBO].vdd_mv)
+    if (ext_vdd >  G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][TURBO].vdd_mv)
     {
         return REGION_TURBO_ULTRA;
     }
-    else if (ext_vdd < G_operating_points[VPD_PT_SET_BIASED_SYSP][NOMINAL].vdd_mv)
+    else if (ext_vdd < G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][NOMINAL].vdd_mv)
     {
         return REGION_POWERSAVE_NOMINAL;
     }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index ed131971..fd2466c2 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -34,10 +34,18 @@
 #include "ipc_messages.h"
 #include "p9_pgpe_header.h"
 
+#if PK_TRACE_PSTATE_ENABLE_
+    #define PK_TRACE_PSTATE(...) PKTRACE(__VA_ARGS__)
+#else
+    #define PK_TRACE_PSTATE(...)
+#endif
+
+
 //
 //Global External Data
 //
 extern PgpeHeader_t* G_pgpe_header_data;
+extern GlobalPstateParmBlock* G_gppb;
 
 //
 //Global Data
@@ -47,8 +55,8 @@ uint32_t G_pstatesStatus;
 uint8_t G_pmcrOwner;
 uint8_t G_wofEnabled;                   //wof enable/disable
 uint8_t G_wofPending;                   //wof enable pending
-uint8_t G_psClipMax[MAX_QUADS],
-        G_psClipMin[MAX_QUADS];         //pmin and pmax clips
+uint8_t G_psClipMax[MAX_QUADS],         //higher numbered(min freq and volt)
+        G_psClipMin[MAX_QUADS];         //lower numbered(max freq and volt)
 uint8_t G_wofClip;                      //wof clip
 uint8_t G_coresPSRequest[MAX_CORES];    //per core requested pstate
 uint8_t G_quadPSComputed[MAX_QUADS];    //computed Pstate per quad
@@ -78,7 +86,6 @@ GPE_BUFFER(ipcmsg_p2s_ctrl_stop_updates_t G_sgpe_control_updt);
 ipc_req_t G_ipc_pend_tbl[MAX_IPC_PEND_TBL_ENTRIES];
 uint32_t G_already_sem_posted;
 
-extern VpdOperatingPoint G_operating_points[NUM_VPD_PTS_SET][VPD_PV_POINTS];
 
 //
 //p9_pgpe_pstate_init
@@ -94,16 +101,16 @@ void p9_pgpe_pstate_init()
 
     for (q = 0; q < MAX_QUADS; q++)
     {
-        G_psClipMax[q] = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_psClipMin[q] = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_quadPSComputed[q] = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_globalPSComputed = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_quadPSTarget[q] = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_globalPSTarget = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_quadPSCurr[q] = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_globalPSCurr  = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_quadPSNext[q] = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-        G_globalPSNext  = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_psClipMax[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_psClipMin[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_quadPSComputed[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_globalPSComputed = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_quadPSTarget[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_globalPSTarget = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_quadPSCurr[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_globalPSCurr  = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_quadPSNext[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+        G_globalPSNext  = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
     }
 
     G_quadState0 = (quad_state0_t*)G_pgpe_header_data->g_quad_status_addr;
@@ -135,7 +142,7 @@ void p9_pgpe_pstate_update(uint8_t* s)
 //
 void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest)
 {
-    PK_TRACE_DBG("AUCT: Enter\n");
+    PK_TRACE_PSTATE("AUCT: Enter");
     //Get active cores and quads
     uint32_t q, c;
     uint32_t activeCores = G_quadState0->fields.active_cores;
@@ -151,7 +158,7 @@ void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest)
         {
             //Go through all the cores in this quad with pending request
             //and find the lowest numbered PState
-            G_quadPSComputed[q] = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+            G_quadPSComputed[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
 
             for (c = (q * CORES_PER_QUAD); c < (q + 1)*CORES_PER_QUAD; c++)
             {
@@ -169,11 +176,11 @@ void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest)
             G_quadPSComputed[q] = 0xFF;
         }
 
-        //   PK_TRACE_DBG("AUCTION: G_quadPSComputed: 0x%x\n", G_quadPSComputed[q]);
+        PK_TRACE_PSTATE("AUCTION: G_quadPSComputed: 0x%x", G_quadPSComputed[q]);
     }
 
     //Global PState Auction
-    G_globalPSComputed = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+    G_globalPSComputed = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
 
     for (q = 0; q < MAX_QUADS; q++)
     {
@@ -186,8 +193,8 @@ void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest)
         }
     }
 
-    PK_TRACE_DBG("AUCT glbPSCmpted: 0x%x\n", G_globalPSComputed);
-    PK_TRACE_DBG("AUCT: Exit\n");
+    PK_TRACE_INF("AUCT glbPSCmpted: 0x%x", G_globalPSComputed);
+    PK_TRACE_PSTATE("AUCT: Exit");
 }
 
 //
@@ -195,12 +202,12 @@ void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest)
 //
 void p9_pgpe_pstate_apply_clips()
 {
-    PK_TRACE_DBG("APCLP: Enter\n");
+    PK_TRACE_PSTATE("APCLP: Enter");
     uint32_t q;
     uint32_t activeQuads = G_reqActQuads->fields.requested_active_quads;
 
     //Apply clips to quad computed
-    PK_TRACE_DBG("APCLP: 0x%x\n", activeQuads);
+    PK_TRACE_PSTATE("APCLP: 0x%x", activeQuads);
 
     for (q = 0; q < MAX_QUADS; q++)
     {
@@ -235,11 +242,11 @@ void p9_pgpe_pstate_apply_clips()
             G_quadPSTarget[q] = 0xFF;
         }
 
-        PK_TRACE_DBG("APP_CLIP: G_qPSTgt: 0x%x,cl=0x%x,0x%x\n", G_quadPSTarget[q], maxPS, G_psClipMin[q]);
+        PK_TRACE_INF("APCLP: qPSTgt: 0x%x,cl=0x%x,0x%x", G_quadPSTarget[q], maxPS, G_psClipMin[q]);
     }
 
     //Global PState Auction
-    G_globalPSTarget = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
+    G_globalPSTarget = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
 
     for (q = 0; q < MAX_QUADS; q++)
     {
@@ -252,8 +259,8 @@ void p9_pgpe_pstate_apply_clips()
         }
     }
 
-    PK_TRACE_DBG("APCLP: glbPSTgt: 0x%x\n", G_globalPSTarget);
-    PK_TRACE_DBG("APCLP: Exit\n");
+    PK_TRACE_INF("APCLP: glbPSTgt: 0x%x", G_globalPSTarget);
+    PK_TRACE_PSTATE("APCLP: Exit");
 }
 
 //
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
index 30567e7a..26760412 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
@@ -34,6 +34,12 @@
 #include "p9_dd1_doorbell_wr.h"
 #include "avs_driver.h"
 
+#if PK_TRACE_ACT_TH_ENABLE_
+    #define PK_TRACE_ACT_TH(...) PKTRACE(__VA_ARGS__)
+#else
+    #define PK_TRACE_ACT_TH(...)
+#endif
+
 //Constants, #defines
 #define CCSR_CORE_CONFIG_MASK    0x80000000
 
@@ -80,7 +86,7 @@ GPE_BUFFER(extern ipcmsg_p2s_ctrl_stop_updates_t G_sgpe_control_updt);
 //
 void p9_pgpe_thread_actuate_pstates(void* arg)
 {
-    PK_TRACE_DBG("ACT_TH: Started\n");
+    PK_TRACE_ACT_TH("ACT_TH: Started");
     uint32_t inRange, q  = 0;
     PkMachineContext  ctx;
     uint32_t restore_irq = 0;
@@ -90,7 +96,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
     pk_semaphore_create(&(G_pgpe_pstate_record.sem_actuate), 0, 1);
     pk_semaphore_create(&(G_pgpe_pstate_record.sem_sgpe_wait), 0, 1);
 
-    PK_TRACE_DBG("ACT_TH: Inited\n");
+    PK_TRACE_ACT_TH("ACT_TH: Inited");
 
     //Initialize Shared SRAM to a known state
     p9_pgpe_thread_actuate_init_actual_quad();
@@ -101,13 +107,13 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
 #if PGPE_UNIT_TEST
     occScr2 |= BIT32(30);
 #endif
-    PK_TRACE_DBG("Setting PGPE_ACTIVE in OCC SCRATCH2 addr %X = %X\n", OCB_OCCS2, occScr2);
+    PK_TRACE_INF("Setting PGPE_ACTIVE in OCC SCRATCH2 addr %X = %X", OCB_OCCS2, occScr2);
     out32(OCB_OCCS2, occScr2);
 
     //Thread Loop
     while(1)
     {
-        PK_TRACE_DBG("ACT_TH: Pend\n");
+        PK_TRACE_ACT_TH("ACT_TH: Pend");
         pk_semaphore_pend(&(G_pgpe_pstate_record.sem_actuate), PK_WAIT_FOREVER);
         wrteei(1);
 
@@ -115,13 +121,15 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
         p9_pgpe_thread_actuate_start();
 
         //Loop while Pstate is enabled
-        PK_TRACE_DBG("ACT_TH: Status=%d\n", G_pstatesStatus);
+        PK_TRACE_ACT_TH("ACT_TH: Status=%d", G_pstatesStatus);
+
+        restore_irq = 0;
 
         while(G_pstatesStatus == PSTATE_ENABLE || G_pstatesStatus == PSTATE_SUSPENDED)
         {
-
             if(G_pstatesStatus != PSTATE_SUSPENDED)
             {
+                //Actuate step(if needed)
                 if( G_globalPSCurr != G_globalPSTarget ||
                     G_quadPSCurr[0] ^ G_quadPSTarget[0] ||
                     G_quadPSCurr[1] ^ G_quadPSTarget[1] ||
@@ -137,13 +145,19 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
                     pk_irq_save_and_set_mask(0);
                     pk_critical_section_exit(&ctx);
 
-                    restore_irq = 0;
-
                     //Do one actuate step
-                    PK_TRACE_DBG("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x\n", G_globalPSTarget, G_globalPSCurr);
+                    PK_TRACE_ACT_TH("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr);
                     p9_pgpe_thread_actuate_do_step();
 
-                    //evaluate conditions for pending ACKs
+
+                    //Now, PGPE is done with actuate step, let's
+                    //restore the interrupts in OIMR through UIH
+                    pk_irq_vec_restore(&ctx);
+                }
+
+                //Check if CLIP_UPDT is pending and Pstates are clipped
+                if (G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_ack == 1)
+                {
                     inRange = 1;
 
                     for (q = 0; q < MAX_QUADS; q++)
@@ -154,7 +168,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
                             if (G_quadPSCurr[q] > G_psClipMax[q] ||
                                 G_quadPSCurr[q] <  G_psClipMin[q])
                             {
-                                PK_TRACE_DBG("ACT_TH:!Clipped[%d) qPSCur: 0x%x\n", q, G_quadPSCurr[q]);
+                                PK_TRACE_ACT_TH("ACT_TH:!Clipped[%d) qPSCur: 0x%x", q, G_quadPSCurr[q]);
                                 inRange = 0;
                             }
                         }
@@ -163,26 +177,20 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
                     //ACK any pending and unmask IPC interrupt
                     if (inRange == 1)
                     {
-                        if (G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_ack == 1)
-                        {
-                            ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].cmd;
-                            ipcmsg_clip_update_t* args = (ipcmsg_clip_update_t*)async_cmd->cmd_data;
-                            args->msg_cb.rc = PGPE_RC_SUCCESS;
-                            G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_ack = 0;
-                            ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].cmd, IPC_RC_SUCCESS);
-                            restore_irq = 1;
-                        }
+                        ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].cmd;
+                        ipcmsg_clip_update_t* args = (ipcmsg_clip_update_t*)async_cmd->cmd_data;
+                        args->msg_cb.rc = PGPE_RC_SUCCESS;
+                        G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_ack = 0;
+                        ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].cmd, IPC_RC_SUCCESS);
+                        restore_irq = 1;
                     }
-
-                    //Now, PGPE is done with actuate step, let's
-                    //restore the interrupts in OIMR through UIH
-                    pk_irq_vec_restore(&ctx);
                 }
 
+
                 //Check if IPC should be opened again
                 if (restore_irq == 1)
                 {
-                    PK_TRACE_DBG("ACT_TH: IRQ Restore\n");
+                    PK_TRACE_ACT_TH("ACT_TH: IRQ Restore");
                     restore_irq = 0;
                     pk_irq_vec_restore(&ctx);
                 }
@@ -200,14 +208,14 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
 //
 void p9_pgpe_thread_actuate_start()
 {
-    PK_TRACE_DBG("ACT_TH: Start Enter\n");
+    PK_TRACE_ACT_TH("ACT_TH: Start Enter");
     ocb_ccsr_t ccsr;
     ccsr.value = in32(OCB_CCSR);
     ocb_qcsr_t qcsr;
     qcsr.value = in32(OCB_QCSR);
     uint8_t quadPstates[MAX_QUADS];
-    uint8_t lowestDpll, syncPstate;
-    qppm_dpll_freq_t dpll;
+    uint32_t lowestDpll, syncPstate;
+    qppm_dpll_stat_t dpll;
     PkMachineContext  ctx;
     uint32_t active_conf_cores = 0;
     uint32_t q;
@@ -227,7 +235,7 @@ void p9_pgpe_thread_actuate_start()
                  (void*)&G_pgpe_pstate_record.sem_sgpe_wait);
 
     //send the command
-    PK_TRACE_DBG("ACT_TH: CtrlStopUpdt Sent\n");
+    PK_TRACE_ACT_TH("ACT_TH: CtrlStopUpdt Sent");
     rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd);
 
     if(rc)
@@ -239,7 +247,7 @@ void p9_pgpe_thread_actuate_start()
     pk_irq_vec_restore(&ctx);
     pk_semaphore_pend(&(G_pgpe_pstate_record.sem_sgpe_wait), PK_WAIT_FOREVER);
 
-    PK_TRACE_DBG("ACT_TH: CtrlStopUpdt Resp\n");
+    PK_TRACE_ACT_TH("ACT_TH: CtrlStopUpdt Resp");
 
     if (G_sgpe_control_updt.fields.return_code == SGPE_PGPE_IPC_RC_SUCCESS)
     {
@@ -247,9 +255,9 @@ void p9_pgpe_thread_actuate_start()
         G_quadState0->fields.active_cores = (ccsr.value >> 16);
         G_quadState1->fields.active_cores = ccsr.value & 0xFF00 ;
         G_reqActQuads->fields.requested_active_quads = G_sgpe_control_updt.fields.active_quads << 2;
-        PK_TRACE_DBG("ACT_TH: core_pwr_st0=0x%x\n", (uint32_t)G_quadState0->fields.active_cores);
-        PK_TRACE_DBG("ACT_TH: core_pwr_st1=0x%x\n", (uint32_t)G_quadState1->fields.active_cores);
-        PK_TRACE_DBG("ACT_TH: req_active_quad=0x%x\n", (uint32_t)G_reqActQuads->fields.requested_active_quads);
+        PK_TRACE_ACT_TH("ACT_TH: core_pwr_st0=0x%x", (uint32_t)G_quadState0->fields.active_cores);
+        PK_TRACE_ACT_TH("ACT_TH: core_pwr_st1=0x%x", (uint32_t)G_quadState1->fields.active_cores);
+        PK_TRACE_ACT_TH("ACT_TH: req_active_quad=0x%x", (uint32_t)G_reqActQuads->fields.requested_active_quads);
     }
     else
     {
@@ -271,12 +279,12 @@ void p9_pgpe_thread_actuate_start()
 
 #endif //_SGPE_IPC_ENABLED_
 
-    PK_TRACE_DBG("ACT_TH: Shr Mem Updt\n");
+    PK_TRACE_ACT_TH("ACT_TH: Shr Mem Updt");
 
     //2. Read DPLLs
-    lowestDpll = 255;
+    lowestDpll = 0xFFF;
     dpll.value = 0;
-    PK_TRACE_DBG("ACT_TH: DPLL0Value=0x%x\n", G_pstate0_dpll_value );
+    PK_TRACE_INF("ACT_TH: DPLL0Value=0x%x", G_pstate0_dpll_value );
 
     for (q = 0; q < MAX_QUADS; q++)
     {
@@ -284,18 +292,18 @@ void p9_pgpe_thread_actuate_start()
            (qcsr.fields.ex_config & (0xC00 >> 2 * q)))
         {
 #if SIMICS_TUNING == 0
-            GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_DPLL_FREQ, q), dpll.value);
+            GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_DPLL_STAT, q), dpll.value);
 #else
-            dpll.fields.fmax = (G_pstate0_dpll_value
-                                - G_operating_points[VPD_PT_SET_BIASED_SYSP][NOMINAL].pstate) << 3;
+            dpll.fields.freqout = (G_pstate0_dpll_value
+                                   - G_operating_points[VPD_PT_SET_BIASED_SYSP][NOMINAL].pstate);
 #endif
 
-            if ((dpll.fields.fmax >> 3) < lowestDpll )
+            if ((dpll.fields.freqout)  < lowestDpll )
             {
-                lowestDpll = dpll.fields.fmax >> 3;
+                lowestDpll = dpll.fields.freqout;
             }
 
-            PK_TRACE_DBG("ACT_TH: Quad[%d]: DPLL=0x%x\n", q, (dpll.fields.fmax ));
+            PK_TRACE_ACT_TH("ACT_TH: Quad[%d]: DPLL=0x%x", q, (dpll.fields.freqout));
             active_conf_cores |= (0xF0000000 >> q * 4);
         }
     }
@@ -308,7 +316,14 @@ void p9_pgpe_thread_actuate_start()
     //DPLL encoding and frequency/pstate have same step size, so
     //they should correspond one to one
     //
-    syncPstate = G_pstate0_dpll_value - lowestDpll;
+    if (lowestDpll > G_pstate0_dpll_value)
+    {
+        syncPstate = G_pstate0_dpll_value;
+    }
+    else
+    {
+        syncPstate = G_pstate0_dpll_value - lowestDpll;
+    }
 
     //Init Core PStates
     for (q = 0; q < MAX_QUADS; q++)
@@ -324,50 +339,34 @@ void p9_pgpe_thread_actuate_start()
     }
 
     p9_pgpe_pstate_update(quadPstates);
-    PK_TRACE_DBG("ACT_TH: Sync Pstate=0x%x\n", syncPstate);
-    PK_TRACE_DBG("ACT_TH: LowDPLL:0x%x\n", q, lowestDpll);
-    PK_TRACE_DBG("ACT_TH: GlblPsTgt:0x%x\n", G_globalPSTarget);
+    PK_TRACE_INF("ACT_TH: Sync Pstate=0x%x", syncPstate);
+    PK_TRACE_INF("ACT_TH: LowDPLL:0x%x", lowestDpll);
+    PK_TRACE_INF("ACT_TH: GlblPsTgt:0x%x", G_globalPSTarget);
 
-    //4. Set External VRM
-    //\TODO: Need Greg's Response
-    //Why does spec says to read external VDD. Is there
-    //any other reason besides PGPE storing it
-    external_voltage_control_init(&G_eVidCurr);
-#if SIMICS_TUNING == 1
-    G_eVidCurr = p9_pgpe_gppb_intp_vdd_from_ps(G_globalPSTarget, VPD_PT_SET_BIASED_SYSP, VPD_SLOPES_BIASED);
-#endif
-    G_eVidNext = p9_pgpe_gppb_intp_vdd_from_ps(G_globalPSTarget, VPD_PT_SET_BIASED_SYSP, VPD_SLOPES_BIASED);
-    p9_pgpe_thread_actuate_updt_ext_volt(G_eVidNext);
-    G_globalPSCurr = G_globalPSTarget;
-
-    PK_TRACE_DBG("ACT_TH: eVidCurr=0x%x\n", G_eVidCurr);
-    PK_TRACE_DBG("ACT_TH: eVidNext=0x%x\n", G_eVidNext);
-    PK_TRACE_DBG("ACT_TH: GlbPSCurr:0x%x\n", G_globalPSCurr );
-
-    //5. Determine PMCR Owner
+    //4. Determine PMCR Owner
     //We save it off so that CMEs that are currently in STOP11
     //can be told upon STOP11 Exit
-    PK_TRACE_DBG("ACT_TH: g_oimr_override:0x%llx\n", g_oimr_override);
+    PK_TRACE_ACT_TH("ACT_TH: g_oimr_override:0x%llx", g_oimr_override);
     ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_ipc_pend_tbl[IPC_PEND_PSTATE_START].cmd;
     ipcmsg_start_stop_t* args = (ipcmsg_start_stop_t*)async_cmd->cmd_data;
 
     if (args->pmcr_owner == PMCR_OWNER_HOST)
     {
-        PK_TRACE_DBG("ACT_TH: OWNER_HOST\n");
+        PK_TRACE_ACT_TH("ACT_TH: OWNER_HOST");
         G_pmcrOwner = PMCR_OWNER_HOST;
         g_oimr_override &= ~(BIT64(46));
         out32(OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
     }
     else if (args->pmcr_owner == PMCR_OWNER_OCC)
     {
-        PK_TRACE_DBG("ACT_TH: OWNER_OCC\n");
+        PK_TRACE_ACT_TH("ACT_TH: OWNER_OCC");
         G_pmcrOwner = PMCR_OWNER_OCC;
         g_oimr_override |= BIT64(46);
         out32(OCB_OIMR1_OR, BIT32(14)); //Disable PCB_INTR_TYPE1
     }
     else if (args->pmcr_owner == PMCR_OWNER_CHAR)
     {
-        PK_TRACE_DBG("ACT_TH: OWNER_CHAR\n");
+        PK_TRACE_ACT_TH("ACT_TH: OWNER_CHAR");
         G_pmcrOwner = PMCR_OWNER_CHAR;
         g_oimr_override &= ~(BIT64(46));
         out32(OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
@@ -377,7 +376,7 @@ void p9_pgpe_thread_actuate_start()
         pk_halt();
     }
 
-    PK_TRACE_DBG("ACT_TH: g_oimr_override:0x%llx\n", g_oimr_override);
+//    PK_TRACE_ACT_TH("ACT_TH: g_oimr_override:0x%llx", g_oimr_override);
     //Set LMCR for each CME
 #if !SIMICS_TUNING
 
@@ -417,14 +416,18 @@ void p9_pgpe_thread_actuate_start()
 
 #endif
 
-    //6. Send Doorbell0 to every active CME by doing a multicast operation
-    //
+    //4. Set External VRM and Send DB0 to every active CME
     //\TODO: Need Greg's Response
-    //Check if this is fine
-    //Slight deviation from Hcode Spec. PGPE sends DB0 to
-    //configured and active cores bc sibling CME reads DB register
-    //to set it's PMSR. They are not communicated by quad manager.
-    //
+    //Why does spec says to read external VDD. Is there
+    //any other reason besides PGPE storing it
+    external_voltage_control_init(&G_eVidCurr);
+    PK_TRACE_INF("ACT_TH: eVidCurr=%umV", G_eVidCurr);
+#if SIMICS_TUNING == 1
+    G_eVidCurr = p9_pgpe_gppb_intp_vdd_from_ps(G_globalPSTarget, VPD_PT_SET_BIASED_SYSP, VPD_SLOPES_BIASED);
+#endif
+    G_eVidNext = p9_pgpe_gppb_intp_vdd_from_ps(G_globalPSTarget, VPD_PT_SET_BIASED_SYSP, VPD_SLOPES_BIASED);
+    PK_TRACE_INF("ACT_TH: eVidNext=%umV", G_eVidNext);
+
     pgpe_db0_start_ps_bcast_t db0;
     db0.value = 0;
     db0.fields.msg_id = MSGID_DB0_START_PSTATE_BROADCAST;
@@ -435,10 +438,26 @@ void p9_pgpe_thread_actuate_start()
     db0.fields.quad3_ps = G_quadPSTarget[3];
     db0.fields.quad4_ps = G_quadPSTarget[4];
     db0.fields.quad5_ps = G_quadPSTarget[5];
-    p9_dd1_db_multicast_wr(PCB_MUTLICAST_GRP1 | CPPM_CMEDB0, db0.value, active_conf_cores);
-    PK_TRACE_DBG("ACT_TH: Mltcast DB0\n");
-    p9_pgpe_wait_cme_db_ack(MSGID_DB0_START_PSTATE_BROADCAST, active_conf_cores);//Wait for ACKs from all QuadManagers
-    PK_TRACE_DBG("ACT_TH: DB0 ACKed\n");
+
+    if (G_eVidCurr > G_eVidNext)
+    {
+        p9_dd1_db_multicast_wr(PCB_MUTLICAST_GRP1 | CPPM_CMEDB0, db0.value, active_conf_cores);
+        PK_TRACE_ACT_TH("ACT_TH: Send DB0");
+        p9_pgpe_wait_cme_db_ack(MSGID_DB0_START_PSTATE_BROADCAST, active_conf_cores);//Wait for ACKs from all QuadManagers
+        PK_TRACE_ACT_TH("ACT_TH: DB0 ACK");
+        p9_pgpe_thread_actuate_updt_ext_volt(G_eVidNext);
+    }
+    else
+    {
+        p9_pgpe_thread_actuate_updt_ext_volt(G_eVidNext);
+        p9_dd1_db_multicast_wr(PCB_MUTLICAST_GRP1 | CPPM_CMEDB0, db0.value, active_conf_cores);
+        PK_TRACE_ACT_TH("ACT_TH: Send DB0");
+        p9_pgpe_wait_cme_db_ack(MSGID_DB0_START_PSTATE_BROADCAST, active_conf_cores);//Wait for ACKs from all QuadManagers
+        PK_TRACE_ACT_TH("ACT_TH: DB0 ACK");
+    }
+
+    G_globalPSCurr = G_globalPSTarget;
+    PK_TRACE_INF("ACT_TH: GlbPSCurr:0x%x", G_globalPSCurr );
 
     for (q = 0; q < MAX_QUADS; q++)
     {
@@ -456,7 +475,7 @@ void p9_pgpe_thread_actuate_start()
 
     //7. Enable PStates
     G_pstatesStatus = PSTATE_ENABLE;
-    PK_TRACE_DBG("ACT_TH: PSTATE_ENABLE\n");
+    PK_TRACE_ACT_TH("ACT_TH: PSTATE_ENABLE");
 
     //8. Send Pstate Start ACK to OCC
     args->msg_cb.rc = PGPE_RC_SUCCESS;
@@ -466,16 +485,16 @@ void p9_pgpe_thread_actuate_start()
     if ((G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_CORES_UPDT].pending_processing == 1) ||
         (G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_processing == 1))
     {
-        PK_TRACE_DBG("ACT_TH: Post PROC_TH\n");
+        PK_TRACE_ACT_TH("ACT_TH: Post PROC_TH");
         pk_semaphore_post(&G_pgpe_pstate_record.sem_process_req);
     }
     else
     {
-        PK_TRACE_DBG("ACT_TH: Restoring IRQs\n");
+        PK_TRACE_ACT_TH("ACT_TH: Restoring IRQs");
         pk_irq_vec_restore(&ctx);
     }
 
-    PK_TRACE_DBG("ACT_TH: Start Exit\n");
+    PK_TRACE_ACT_TH("ACT_TH: Start Exit");
 }
 
 //
@@ -483,9 +502,9 @@ void p9_pgpe_thread_actuate_start()
 //
 void p9_pgpe_thread_actuate_stop()
 {
-    PK_TRACE_DBG("ACT_TH: Stop Enter\n");
-    PK_TRACE_DBG("ACT_TH: GlbPSCurr:0x%x\n", G_globalPSCurr );
-    PK_TRACE_DBG("ACT_TH: GlblPsTgt:0x%x\n", G_globalPSTarget);
+    PK_TRACE_ACT_TH("ACT_TH: Stop Enter");
+    PK_TRACE_ACT_TH("ACT_TH: GlbPSCurr:0x%x", G_globalPSCurr );
+    PK_TRACE_ACT_TH("ACT_TH: GlblPsTgt:0x%x", G_globalPSTarget);
     uint32_t q;
     PkMachineContext  ctx;
     uint32_t active_conf_cores = 0;
@@ -529,7 +548,7 @@ void p9_pgpe_thread_actuate_stop()
                  (void*)&G_pgpe_pstate_record.sem_sgpe_wait);
 
     //send the command
-    PK_TRACE_DBG("ACT_TH: CtrlStopUpdt Sent\n");
+    PK_TRACE_ACT_TH("ACT_TH: CtrlStopUpdt Sent");
     rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd);
 
     if(rc)
@@ -541,7 +560,7 @@ void p9_pgpe_thread_actuate_stop()
     pk_irq_vec_restore(&ctx);
     pk_semaphore_pend(&(G_pgpe_pstate_record.sem_sgpe_wait), PK_WAIT_FOREVER);
 
-    PK_TRACE_DBG("ACT_TH: CtrlStopUpdt Rcvd\n");
+    PK_TRACE_ACT_TH("ACT_TH: CtrlStopUpdt Rcvd");
 
     if (G_sgpe_control_updt.fields.return_code != SGPE_PGPE_IPC_RC_SUCCESS)
     {
@@ -557,10 +576,10 @@ void p9_pgpe_thread_actuate_stop()
     G_ipc_pend_tbl[IPC_PEND_PSTATE_STOP].pending_ack = 0;
     ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_PSTATE_STOP].cmd, IPC_RC_SUCCESS);
 
-    PK_TRACE_DBG("ACT_TH: GlbPSCurr:0x%x\n", G_globalPSCurr );
-    PK_TRACE_DBG("ACT_TH: GlblPsTgt:0x%x\n", G_globalPSTarget);
+    // PK_TRACE_ACT_TH("ACT_TH: GlbPSCurr:0x%x", G_globalPSCurr );
+    // PK_TRACE_ACT_TH("ACT_TH: GlblPsTgt:0x%x", G_globalPSTarget);
     pk_irq_vec_restore(&ctx);
-    PK_TRACE_DBG("ACT_TH: Stop Exit\n");
+    PK_TRACE_ACT_TH("ACT_TH: Stop Exit");
 }
 
 //
@@ -568,14 +587,14 @@ void p9_pgpe_thread_actuate_stop()
 //
 void p9_pgpe_thread_actuate_do_step()
 {
-    PK_TRACE_DBG("ACT_TH: Step Entry\n");
-    PK_TRACE_DBG("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x\n", G_globalPSTarget, G_globalPSCurr);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[0], G_quadPSCurr[0]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[1], G_quadPSCurr[1]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[2], G_quadPSCurr[2]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[3], G_quadPSCurr[3]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[4], G_quadPSCurr[4]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[5], G_quadPSCurr[5]);
+    PK_TRACE_ACT_TH("ACT_TH: Step Entry");
+    PK_TRACE_ACT_TH("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[0], G_quadPSCurr[0]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[1], G_quadPSCurr[1]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[2], G_quadPSCurr[2]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[3], G_quadPSCurr[3]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[4], G_quadPSCurr[4]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[5], G_quadPSCurr[5]);
     uint32_t q;
     ocb_qcsr_t qcsr;
     qcsr.value = in32(OCB_QCSR);
@@ -598,7 +617,7 @@ void p9_pgpe_thread_actuate_do_step()
             }
         }
 
-        PK_TRACE_DBG("ACT_TH: act_c=0x%x\n", active_conf_cores);
+        PK_TRACE_ACT_TH("ACT_TH: act_c=0x%x", active_conf_cores);
     }
 
     //Higher number PState
@@ -699,13 +718,13 @@ void p9_pgpe_thread_actuate_do_step()
     G_quadState1->fields.quad4_pstate = G_quadPSCurr[4];
     G_quadState1->fields.quad5_pstate = G_quadPSCurr[5];
 
-    PK_TRACE_DBG("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x\n", G_globalPSTarget, G_globalPSCurr);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[0], G_quadPSCurr[0]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[1], G_quadPSCurr[1]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[2], G_quadPSCurr[2]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[3], G_quadPSCurr[3]);
-    PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x\n", G_quadPSTarget[4], G_quadPSCurr[4]);
-    PK_TRACE_DBG("ACT_TH: Step Exit\n");
+    PK_TRACE_ACT_TH("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[0], G_quadPSCurr[0]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[1], G_quadPSCurr[1]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[2], G_quadPSCurr[2]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[3], G_quadPSCurr[3]);
+    PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[4], G_quadPSCurr[4]);
+    PK_TRACE_ACT_TH("ACT_TH: Step Exit");
 }
 
 //
@@ -715,7 +734,7 @@ void p9_pgpe_thread_actuate_do_step()
 void p9_pgpe_thread_actuate_updt_ext_volt(uint32_t tgtEVid)
 {
 #if !EPM_P9_TUNING
-    uint32_t delay_us;
+    uint32_t delay_us = 0;
 
     //Decreasing
     if (G_eVidNext < G_eVidCurr)
@@ -745,7 +764,7 @@ void p9_pgpe_thread_actuate_updt_ext_volt(uint32_t tgtEVid)
 
     if(G_eVidNext == tgtEVid)
     {
-        pk_sleep(PK_MICROSECONDS((G_gppd->ext_vrm_stabilization_time_us)));
+        pk_sleep(PK_MICROSECONDS((G_gppb->ext_vrm_stabilization_time_us)));
     }
 
 #endif
@@ -759,8 +778,8 @@ void p9_pgpe_thread_actuate_updt_ext_volt(uint32_t tgtEVid)
 //Sends a DB0 to all active CMEs, so that Quad Managers(CMEs) update DPLL
 void p9_pgpe_thread_actuate_freq_updt(uint32_t activeCores)
 {
-    PK_TRACE_DBG("ACT_TH: Freq Updt Enter\n");
-    PK_TRACE_DBG("ACT_TH: act_cores=0x%x\n", activeCores);
+    PK_TRACE_ACT_TH("ACT_TH: FreqUpdt Enter");
+    PK_TRACE_ACT_TH("ACT_TH: act_cores=0x%x", activeCores);
     pgpe_db0_glb_bcast_t db0;
     db0.value = 0;
     db0.fields.msg_id = MSGID_DB0_GLOBAL_ACTUAL_BROADCAST;
@@ -772,9 +791,9 @@ void p9_pgpe_thread_actuate_freq_updt(uint32_t activeCores)
     db0.fields.quad4_ps = G_quadPSNext[4];
     db0.fields.quad5_ps = G_quadPSNext[5];
     p9_dd1_db_multicast_wr(PCB_MUTLICAST_GRP1 | CPPM_CMEDB0, db0.value, activeCores);
-    PK_TRACE_DBG("ACT_TH: MCAST DB0\n");
+    PK_TRACE_ACT_TH("ACT_TH: MCAST DB0");
     p9_pgpe_wait_cme_db_ack(MSGID_DB0_GLOBAL_ACTUAL_BROADCAST, activeCores);//Wait for ACKs from all CMEs
-    PK_TRACE_DBG("ACT_TH: Freq Updt Exit\n");
+    PK_TRACE_ACT_TH("ACT_TH: Freq Updt Exit");
 }
 
 
@@ -818,15 +837,15 @@ void p9_pgpe_wait_cme_db_ack(uint8_t msg_id, uint32_t active_conf_cores)
                     /*#if SIMICS_TUNING == 1
                                         uint32_t opit4prCurr;
                                         opit4prCurr = in32(OCB_OPIT4PRA);
-                                        PK_TRACE_DBG("ACT_TH: temp=0x%x\n", opit4prCurr);
+                                        PK_TRACE_ACT_TH("ACT_TH: temp=0x%x", opit4prCurr);
                                         out32(OCB_OPIT4PRA, (~(CCSR_CORE_CONFIG_MASK >> c)) & opit4prCurr);
                     #endif*/
                     out32(OCB_OPIT4PRA_CLR, CCSR_CORE_CONFIG_MASK >> c); //Clear out pending bits
-                    PK_TRACE_DBG("ACT_TH: Got Ack. Core=0x%x\n", c);
+                    PK_TRACE_ACT_TH("ACT_TH: Ack C%02u", c);
                 }
                 else
                 {
-                    PK_TRACE_DBG("ACT_TH: Ack Mismatch. Core=0x%x\n", c);
+                    PK_TRACE_ACT_TH("ACT_TH: BadAck C%02u", c);
                     pk_halt();
                 }
             }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
index fcc193b8..f7849d6e 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
@@ -83,7 +83,7 @@ void p9_pgpe_thread_process_requests(void* arg)
     asm volatile ("tw 0, 31, 0");
 #endif
 
-    PK_TRACE_DBG("PROCTH:Inited; PGPE_ACTIVE set\n");
+    PK_TRACE_INF("PROCTH:Inited; PGPE_ACTIVE set\n");
 
     while(1)
     {
@@ -363,10 +363,13 @@ void p9_pgpe_process_clip_updt()
     else
     {
 
+        //IPC from 405 treats clip_min as Pstate for min frequency(higher numbered)
+        //and clip_max as Pstate for max frequency(lower numbered). However, PGPE
+        //Hcode stores them with reverse interpretation.
         for (q = 0; q < MAX_QUADS; q++)
         {
-            G_psClipMax[q] = args->ps_val_clip_max[q];
-            G_psClipMin[q] = args->ps_val_clip_min[q];
+            G_psClipMax[q] = args->ps_val_clip_min[q];
+            G_psClipMin[q] = args->ps_val_clip_max[q];
         }
 
         p9_pgpe_pstate_apply_clips(&G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT]);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
index fd5d46c9..03d2d8f2 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
@@ -35,11 +35,11 @@
 ///
 
 // --------------------
-#define EPM_P9_TUNING 1
+#define EPM_P9_TUNING 0
 #define SIMICS_TUNING 0
 #define GEN_PSTATE_TBL 1
 #define USE_BOOT_TEMP 0
-#define BOOT_TEMP_SET_FULL_OCC_IPC_FUNC 0
+#define BOOT_TEMP_SET_FULL_OCC_IPC_FUNC 1
 #define DEV_DEBUG     1
 #define PK_TRACE_TIMER_OUTPUT 0
 #define SGPE_IPC_ENABLED 0
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
index 4af98d07..0221d630 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
@@ -81,6 +81,9 @@ $(IMAGE)_TRACE_HASH_PREFIX := $(shell echo $(IMAGE) | md5sum | cut -c1-4 \
 
 # Options for PK_TRACE
 $(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=3
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_ACT_TH_ENABLE=1
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_PROC_TH_ENABLE=0
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_PSTATE_ENABLE=0
 $(IMAGE)_COMMONFLAGS+= -DPK_TRACE_TIMER_OUTPUT=0
 
 
@@ -93,7 +96,7 @@ $(IMAGE)_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
 $(IMAGE)_COMMONFLAGS+= -D__PPE_PLAT
 $(IMAGE)_COMMONFLAGS+= -D__PK__=1
 #$(IMAGE)_COMMONFLAGS+= -fstack-usage
-#$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SZ=1024
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SZ=1024
 
 # add include paths
 $(call ADD_PPEIMAGE_INCDIR,$(IMAGE),\