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authorChristopher M. Riedl <cmriedl@us.ibm.com>2017-05-05 21:05:19 -0500
committerJoshua Hunsberger <jahunsbe@us.ibm.com>2017-10-23 17:33:57 -0500
commit81414e17358bb611f95e84feb11ca308ac6aaef8 (patch)
treee88c85d5d6e895bdab70f03049028bbc50cae928
parent0c43435f789d34aea00bf315f6b1da2d09299ef5 (diff)
downloadtalos-hcode-81414e17358bb611f95e84feb11ca308ac6aaef8.tar.gz
talos-hcode-81414e17358bb611f95e84feb11ca308ac6aaef8.zip
Pstate: Remove legacy VDM code
- Remove legacy VDM code in preparation for actual VDM enablement commit - VDM enablement only occurs during istep15 - Does not introduce any inter-platform dependencies Change-Id: Ia46661f6133e2556bee0464a95c7109658a86beb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40185 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
-rwxr-xr-ximport/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c4
-rw-r--r--import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c4
-rw-r--r--import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C4
-rw-r--r--import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c4
4 files changed, 0 insertions, 16 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index d8d7aa9f..70aa5a07 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -733,10 +733,6 @@ p9_cme_stop_entry()
PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
CME_PUTSCOM(C_CPLT_CONF0_CLEAR, core, BIT64(34));
- /// @todo RTC166918 add VDM_ENABLE attribute control
- PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]");
- CME_PUTSCOM(PPM_VDMCR_CLR, core, BIT64(0));
-
PK_TRACE("Copy PECE CME sample to PPM Shadow via PECES");
if (core & CME_MASK_C0)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
index 8b0a8b9a..6948347e 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
@@ -109,10 +109,6 @@ p9_hcd_core_chiplet_reset(uint32_t core)
p9_hcd_core_scan0(core, SCAN0_REGION_ALL, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME);
#endif
- /// @todo RTC166918 add VDM_ENABLE attribute control
- PK_TRACE("Assert vdm enable via CPPM_VDMCR[0]");
- CME_PUTSCOM(PPM_VDMCR_OR, core, BIT64(0));
-
/// content of p9_hcd_core_dcc_skewadjust below:
PK_TRACE("Drop core DCC bypass via NET_CTRL[1]");
CME_PUTSCOM(CPPM_NC1INDIR_CLR, core, BIT64(1));
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
index 08400d52..56a17ad9 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
@@ -59,10 +59,6 @@ extern "C" void p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t quad)
FAPI_DBG("Drop L3 DCC bypass");
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WAND, quad), ~BIT64(1));
- /// @todo RTC166918 add VDM_ENABLE attribute control
- FAPI_DBG("Check if VDMs are to be enabled. If so, power them on");
- GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_OR, quad), BIT64(0));
-
fapi_try_exit:
FAPI_DBG("<<p9_hcd_cache_chiplet_l3_dcc_setup");
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 5c0ec63b..c244743f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -908,10 +908,6 @@ p9_sgpe_stop_entry()
PK_TRACE("Drop CME_INTERPPM_DPLL_ENABLE after DPLL is stopped via QPMMR[26]");
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_CLR, qloop), BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26));
- /// @todo RTC166918 add VDM_ENABLE attribute control
- PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]");
- GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_CLR, qloop), BIT64(0));
-
PK_TRACE_INF("SE.11D: Cache Clock Stopped");
PK_TRACE("Gate the PCBMux request so scanning doesn't cause random requests");
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