PGPE: Fixes and Cleanup for Mfg/Char team

    -Gen. correct number of entries in OCC Pstate table
    -Correctly correct aux thread period
    -Fill VDM fields in Pstate table

    Key_Cronus_Test=PM_REGRESS

Change-Id: I0f11b35ec5d6b3667e253f683325b559a93801af
CQ: SW436423
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61095
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

7 files changed, 162 insertions, 18 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
index 849e330c..65fa03ee 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
@@ -74,6 +74,7 @@ void p9_pgpe_fit_handler(void* arg, PkIrqId irq);
 void p9_pgpe_fit_init()
 {
     uint16_t freq = G_gppb->nest_frequency_mhz;
+    uint16_t aux_period;
 
     PK_TRACE_DBG("Fit NestFreq=0x%dMhz", G_gppb->nest_frequency_mhz);
 
@@ -92,9 +93,11 @@ void p9_pgpe_fit_init()
                                  (freq < 2097) ? 4 :
                                  (freq < 2621) ? 5 : 6;
 
-    if(G_pgpe_header_data->g_pgpe_aux_controls) //multiply by attribute if nonzero
+    aux_period = G_pgpe_header_data->g_pgpe_aux_controls >> 24;
+
+    if(aux_period) //multiply by attribute if nonzero
     {
-        G_aux_task_count_threshold *= G_pgpe_header_data->g_pgpe_aux_controls;
+        G_aux_task_count_threshold *= aux_period;
     }
 
     PK_TRACE_DBG("Fit AuxTaskThr=0x%d", G_aux_task_count_threshold);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
index 178a496e..8bf7f30f 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
@@ -100,16 +100,16 @@ void p9_pgpe_gen_pstate_info()
                  G_gpi->header.highest_ps_offset,
                  G_gpi->header.biased_pstate_tbl_offset);
     gppb = (GlobalPstateParmBlock*)((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
-                                    G_gpi->header.gppb_offset));
+                                    G_gpi->header.gppb_offset);
     ps0 = ((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) + G_gpi->header.ps0_offset);
     highest_pstate = ((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) + G_gpi->header.highest_ps_offset);
     rTbl = (PstateTable*)((uint32_t*)(G_(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
                                       G_gpi->header.raw_pstate_tbl_offset);
-           bTbl = (PstateTable*)(((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
+                          bTbl = (PstateTable*)(((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
                                   G_gpi->header.biased_pstate_tbl_offset);
-                                 PK_TRACE_DBG("INIT:highest_ps=0x%x, ps0=0x%x",
-                                         *highest_pstate,
-                                         *ps0);
+                                  PK_TRACE_DBG("INIT:highest_ps=0x%x, ps0=0x%x",
+                                          *highest_pstate,
+                                          *ps0);
 #elif USE_GEN_PSTATE_STRUCT_V == 2
     G_gpi = (GeneratedPstateInfo_v2*)G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset;
     G_gpi->magic = GEN_PSTATES_TBL_MAGIC_V2;
@@ -184,9 +184,9 @@ void p9_pgpe_gen_raw_pstates(PstateTable* tbl)
         tbl[p].effective_regulation_vdd_mv = G_gpi->raw_pstates[p].external_vdd_mv + G_gppb->ivrm.deadzone_mv;
         tbl[p].internal_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_RAW);
         tbl[p].internal_vid = (G_gpi->raw_pstates[p].internal_vdd_mv - 512) >> 4;
-        tbl[p].vdm_mv = 0;
-        tbl[p].vdm_vid = 0;
-        tbl[p].vdm_thresholds = 0;
+        tbl[p].vdm_vid = (uint8_t)p9_pgpe_gppb_vdm_vid_cmp_from_ps(p);
+        tbl[p].vdm_mv = (uint8_t)tbl[p].vdm_vid; //Note: the field in struct is 8 bits only, we can put in the value in mV
+        tbl[p].vdm_thresholds = (uint16_t)p9_pgpe_gppb_vdm_threshold_from_ps(p);
         freq_khz_offset += G_gppb->frequency_step_khz;
     }
 
@@ -214,9 +214,9 @@ void p9_pgpe_gen_biased_pstates(PstateTable* tbl)
                                              G_gppb->ivrm.deadzone_mv);
         tbl[p].internal_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_BIASED);
         tbl[p].internal_vid = (uint16_t)((G_gpi->biased_pstates[p].internal_vdd_mv - 512) >> 4);
-        tbl[p].vdm_mv = 0;
-        tbl[p].vdm_vid = 0;
-        tbl[p].vdm_thresholds = 0;
+        tbl[p].vdm_vid = (uint8_t)p9_pgpe_gppb_vdm_vid_cmp_from_ps(p);
+        tbl[p].vdm_mv = (uint8_t)tbl[p].vdm_vid; //Note: the field in struct is 8 bits only, we can put in the value in mV
+        tbl[p].vdm_thresholds = (uint16_t)p9_pgpe_gppb_vdm_threshold_from_ps(p);
         freq_khz_offset += G_gppb->frequency_step_khz;
     }
 
@@ -235,7 +235,7 @@ void p9_pgpe_gen_occ_pstate_tbl()
     OCCPstateTable_t* opst = (OCCPstateTable_t*)G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr;
     opst->entries = (G_pgpe_header_data->g_pgpe_occ_pstables_len) / sizeof(OCCPstateTable_entry_t);
 
-    for (p = 0; p <= opst->entries; p++)
+    for (p = 0; p < opst->entries; p++)
     {
         opst->table[p].pstate = G_gpi->biased_pstates[p].pstate;
         opst->table[p].frequency_mhz = G_gpi->biased_pstates[p].frequency_mhz ;
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
index fb94fdae..d97e2f8e 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
@@ -27,6 +27,48 @@
 #include "p9_pgpe_header.h"
 #include "p9_hcode_image_defines.H"
 
+typedef enum
+{
+    VDM_OVERVOLT_IDX = 0,
+    VDM_SMALL_IDX    = 1,
+    VDM_LARGE_IDX    = 2,
+    VDM_XTREME_IDX   = 3
+} VDM_THRESHOLD_IDX;
+
+typedef enum
+{
+    // VDM_OVERVOLT_ADJUST
+    // 4/8 rounding (8mV resolution so +/- 4 mV error)
+    // yields 3/7 aggressive and 4/7 conservative to slightly favor not
+    // increasing to Fmax as often
+    VDM_OVERVOLT_ADJUST = (uint32_t)((1 << THRESH_SLOPE_FP_SHIFT) * ((float)4 / 8)),
+    // VDM_SMALL_ADJUST
+    // 5/8 rounding (8mV resolution so +5/-3 mV error)
+    // yields 2/7 conservative and 5/7 aggressive to favor protecting against
+    // performance loss
+    VDM_SMALL_ADJUST    = (uint32_t)((1 << THRESH_SLOPE_FP_SHIFT) * ((float)5 / 8)),
+    // VDM_LARGE_ADJUST and VDM_XTREME_ADJUST
+    // 2/8 rounding (8mV resolution so +3/-5 mV error)
+    // yields 2/7 aggressive and 5/7 conservative to favor protecting droop
+    // guardband
+    VDM_LARGE_ADJUST    = (uint32_t)((1 << THRESH_SLOPE_FP_SHIFT) * ((float)2 / 8)),
+    VDM_XTREME_ADJUST   = (uint32_t)((1 << THRESH_SLOPE_FP_SHIFT) * ((float)2 / 8)),
+    //VDM_VID_COMP_ADJUST
+    // 2/4 rounding (4mV resolution so +/- 2mV error)
+    // yields 1/3 (1mV) aggressive and 2/3 (1 or 2mV) conservative answer
+    VDM_VID_COMP_ADJUST = (uint32_t)((1 << VID_SLOPE_FP_SHIFT_12) * ((float)2 / 4)),
+    //VDM_JUMP_VALUE_ADJUST
+    VDM_JUMP_VALUE_ADJUST = (uint32_t)((1 << THRESH_SLOPE_FP_SHIFT) * ((float)1 / 2))
+} VDM_ROUNDING_ADJUST;
+
+
+
+const uint8_t G_vdm_threshold_table[13] =
+{
+    0x00, 0x01, 0x03, 0x02, 0x06, 0x07, 0x05, 0x04,
+    0x0C, 0x0D, 0x0F, 0x0E, 0x0A
+};
+
 //Globals and externs
 GlobalPstateParmBlock* G_gppb;//Global pointer to GlobalPstateParmBlock
 uint32_t G_ext_vrm_inc_rate_mult_usperus;
@@ -50,7 +92,7 @@ void p9_pgpe_gppb_init()
     void* gppb_sram_offset = (void*)G_pgpe_header_data->g_pgpe_gppb_sram_addr;//GPPB Sram Offset
     G_gppb = (GlobalPstateParmBlock*)gppb_sram_offset;
 
-    PK_TRACE_INF("INIT: DPLL0Value=0x%x", G_gppb->dpll_pstate0_value);
+    //PK_TRACE_INF("INIT: DPLL0Value=0x%x", G_gppb->dpll_pstate0_value);
     //External VRM increasing rate in us/uv
     G_ext_vrm_inc_rate_mult_usperus = 1 / G_gppb->ext_vrm_transition_rate_inc_uv_per_us;
 
@@ -178,3 +220,84 @@ uint8_t p9_pgpe_gppb_get_ext_vdd_region(uint32_t ext_vdd)
         return REGION_NOMINAL_TURBO;
     }
 }
+
+//  Interpolate vdm vid compare from pstate.
+//
+//  Note: This function is hardcoded to use biased with system parameters applied
+//  VPD points because currently interpolating pstate from vdd is only needed
+//  for biased with system parameter applied VPD point
+//
+//  ps - Pstate from which to interpolate voltage
+//
+//  retval - VDM VID Compare value
+uint32_t p9_pgpe_gppb_vdm_vid_cmp_from_ps(Pstate ps)
+{
+    uint32_t vdd;
+    uint8_t r  = p9_pgpe_gppb_get_ps_region(ps, VPD_PT_SET_BIASED_SYSP);
+
+    //Round-up by adding 1/2
+    vdd = ((((uint32_t)G_gppb->PsVIDCompSlopes[r] *
+             ((uint32_t)G_gppb->operating_points[r].pstate - ps)
+             + VDM_VID_COMP_ADJUST) >> VID_SLOPE_FP_SHIFT_12)
+           + (uint32_t)G_gppb->vid_point_set[r]);
+
+    return vdd;
+}
+
+
+//  VDM Thresholds from pstate.
+//
+//  ps - Pstate from which to interpolate voltage
+//
+//  retval - VDM Thresholds
+uint16_t p9_pgpe_gppb_vdm_threshold_from_ps(uint32_t pstate)
+{
+    static uint32_t vdm_rounding_adjust[NUM_THRESHOLD_POINTS] =
+    {
+        VDM_OVERVOLT_ADJUST,
+        VDM_SMALL_ADJUST,
+        VDM_LARGE_ADJUST,
+        VDM_XTREME_ADJUST
+    };
+
+    uint32_t i = 0;
+    uint32_t indices[4];
+    uint32_t region = p9_pgpe_gppb_get_ps_region(pstate, VPD_PT_SET_BIASED_SYSP);
+    int32_t psdiff = (uint32_t)G_gppb->operating_points[region].pstate - pstate;
+
+    for(i = 0; i < NUM_THRESHOLD_POINTS; ++i)
+    {
+        indices[i] = (uint32_t)((int32_t)G_gppb->threshold_set[region][i]
+                                // delta = slope times difference in pstate (interpolate)
+                                + ((((int32_t)G_gppb->PsVDMThreshSlopes[region][i] * psdiff)
+                                    // Apply the rounding adjust
+                                    + (int32_t)vdm_rounding_adjust[i]) >> THRESH_SLOPE_FP_SHIFT));
+
+    }
+
+    // Check the interpolation result; since each threshold has a distinct round
+    // adjust, the calculated index can be invalid relative to another threshold
+    // index. Overvolt does not need to be checked and Small Droop will always
+    // be either 0 or greater than 0 by definition.
+    // Ensure that small <= large <= xtreme; where any can be == 0.
+    indices[VDM_LARGE_IDX] = ((indices[VDM_LARGE_IDX] < indices[VDM_SMALL_IDX])
+                              && (indices[VDM_LARGE_IDX] != 0))
+                             ? indices[VDM_SMALL_IDX] : indices[VDM_LARGE_IDX];
+    indices[VDM_XTREME_IDX] = ((indices[VDM_XTREME_IDX] < indices[VDM_LARGE_IDX])
+                               && (indices[VDM_XTREME_IDX] != 0))
+                              ? indices[VDM_LARGE_IDX] : indices[VDM_XTREME_IDX];
+    indices[VDM_XTREME_IDX] = ((indices[VDM_XTREME_IDX] < indices[VDM_SMALL_IDX])
+                               && (indices[VDM_LARGE_IDX]  == 0)
+                               && (indices[VDM_XTREME_IDX] != 0))
+                              ? indices[VDM_SMALL_IDX] : indices[VDM_XTREME_IDX];
+
+    PK_TRACE_DBG("%u %u %u %u", indices[0], indices[1], indices[2], indices[3]);
+    uint16_t ret = ((G_vdm_threshold_table[indices[0]] << 12)
+                    | (G_vdm_threshold_table[indices[1]] << 8)
+                    | (G_vdm_threshold_table[indices[2]] << 4)
+                    | (G_vdm_threshold_table[indices[3]]));
+
+    PK_TRACE_DBG("ps=%d, %x", pstate, ret);
+    return ret;
+
+}
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h
index 38a19101..bbcc2d74 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h
@@ -54,4 +54,22 @@ uint32_t p9_pgpe_gppb_intp_vdd_from_ps(Pstate ps, uint8_t vpd_pt_set);
 //  retval - Pstate interpolated corresponding to external voltage
 uint8_t p9_pgpe_gppb_intp_ps_from_ext_vdd(uint16_t ext_vdd);
 
+//  Interpolate vdm vid compare from pstate.
+//
+//  Note: This function is hardcoded to use biased with system parameters applied
+//  VPD points because currently interpolating pstate from vdd is only needed
+//  for biased with system parameter applied VPD point
+//
+//  ps - Pstate from which to interpolate voltage
+//
+//  retval - VDM VID Compare value
+uint32_t p9_pgpe_gppb_vdm_vid_cmp_from_ps(Pstate ps);
+
+//  Calculate vdm thresholds for a pstate.
+//
+//  Pstate - Pstate for which to calculate VDM thresholds
+//
+//  retval - VDM Threshold(VDM_OVERVOLT:VDM_DROOP_SMALL:VDM_DROOP_LARGE:VDM_DROOP_XTREME]
+uint16_t p9_pgpe_gppb_vdm_threshold_from_ps(uint32_t pstate);
+
 #endif //_P9_PGPE_GPPB_H_
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
index 4fed18a7..09b730c7 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
@@ -66,7 +66,7 @@ void p9_pgpe_header_init()
 
     G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr = (uint32_t)
             &occ_shared_data->pstate_table; //OCC Pstate table address
-    G_pgpe_header_data->g_pgpe_occ_pstables_len  = sizeof(OCCPstateTable_t); //OCC Pstate table length
+    G_pgpe_header_data->g_pgpe_occ_pstables_len  = MAX_PSTATE_TABLE_ENTRIES; //OCC Pstate table length
 
     G_pgpe_header_data->g_pgpe_beacon_addr = (uint32_t)&occ_shared_data->pgpe_beacon;//Beacon
     G_pgpe_header_data->g_quad_status_addr = (uint32_t)&occ_shared_data->quad_pstate_0;//Quad Pstate
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_common.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_common.mk
index 6e8376bf..989b13d3 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_common.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_common.mk
@@ -91,7 +91,7 @@ PSTATE_COMMONFLAGS+= -DPK_TRACE_SUPPORT=1
 PSTATE_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
 PSTATE_COMMONFLAGS+= -D__PPE_PLAT
 PSTATE_COMMONFLAGS+= -D__PK__=1
-PSTATE_COMMONFLAGS+= -DPK_TRACE_SZ=1024
+PSTATE_COMMONFLAGS+= -DPK_TRACE_SZ=512
 PSTATE_COMMONFLAGS+= -DPSTATE_GPE
 
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
index f7965d8f..9578d8d5 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
@@ -94,7 +94,7 @@ $(IMAGE)_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
 $(IMAGE)_COMMONFLAGS+= -D__PPE_PLAT
 $(IMAGE)_COMMONFLAGS+= -D__PK__=1
 #$(IMAGE)_COMMONFLAGS+= -fstack-usage
-$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SZ=1024
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SZ=512
 
 # add include paths
 $(call ADD_PPEIMAGE_INCDIR,$(IMAGE),\