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author | Michael Floyd <mfloyd@us.ibm.com> | 2018-02-09 16:50:43 -0600 |
---|---|---|
committer | hostboot <hostboot@us.ibm.com> | 2018-03-22 14:04:06 -0500 |
commit | 7754948e126027ed7481ccf2de401ca0141b5f69 (patch) | |
tree | be2114e581dcf54e4759278b92575e1c6f7243f2 | |
parent | 554ec892997079d31d094a9eba17c987ef5e2690 (diff) | |
download | talos-hcode-7754948e126027ed7481ccf2de401ca0141b5f69.tar.gz talos-hcode-7754948e126027ed7481ccf2de401ca0141b5f69.zip |
CME Size Reduction Fixes
-- sibling no longer clears g_eimr_override bit7
-- misplaced paren with invert mask for IRQ_VEC_STOP_C0_UPPER
-- fixed comment and removed redundant code in pstate start
for Enabling PMCR interrupts
-- removed bad trace message in sibling during registration
-- removed unneeded scom_data init to 0
-- removed annoying \n in cme pstate trace messages
Key_Cronus_Test=PM_REGRESS
Change-Id: I651c7eac42c1cde65f6480304a7f66249c7e3e36
CQ: SW415503
RTC: 178789
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53794
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
-rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index f565108b..5667b9c2 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -157,7 +157,7 @@ p9_cme_stop_spwu_handler(void) if (!(G_cme_stop_record.core_blockey & core_mask)) { // use 32 bit UPPER mask to prevent compiler from doing 64-bit shifting - g_eimr_override &= ((uint64_t)((~IRQ_VEC_STOP_C0_UPPER) >> core_index)) << 32 | 0xFFFFFFFF; + g_eimr_override &= ((uint64_t)~((IRQ_VEC_STOP_C0_UPPER) >> core_index)) << 32 | 0xFFFFFFFF; } } } |