Fix DD LEVEL to support minor ECs

Change-Id: I658b545b74e4aab8b766b1424632c25edd76c73f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42513
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

23 files changed, 35 insertions, 35 deletions

diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/div32.S b/import/chips/p9/procedures/ppe/pk/ppe42/div32.S
index 9108e4e9..25a23d60 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/div32.S
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/div32.S
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-#if (!defined(PSTATE_GPE) || NIMBUS_DD_LEVEL==1)
+#if (!defined(PSTATE_GPE) || NIMBUS_DD_LEVEL==10)
     .nolist
 #include "ppe42_asm.h"
     .list
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/math.c b/import/chips/p9/procedures/ppe/pk/ppe42/math.c
index a0fc0a5c..d6bd329c 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/math.c
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/math.c
@@ -38,7 +38,7 @@ extern "C"
 
 
 #ifdef PSTATE_GPE
-#if (NIMBUS_DD_LEVEL != 1)
+#if (NIMBUS_DD_LEVEL != 10)
 
 #include "ocb_register_addresses.h"
 #define out64(addr, data) \
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_p9c10.mk b/import/chips/p9/procedures/ppe_closed/cme/cme_p9c10.mk
index 167a169c..c267ad68 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_p9c10.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_p9c10.mk
@@ -28,7 +28,7 @@ IMAGE := $(CME_TARGET)
 
 # Options for Platforms specific
 $(IMAGE)_COMMONFLAGS = -DNIMBUS_DD_LEVEL=0
-$(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=1
+$(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=10
 
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
 $(IMAGE)_COMMONFLAGS+= -DEPM_P9_TUNING=0
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n10.mk b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n10.mk
index 5f32d2ba..743fc9e7 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n10.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n10.mk
@@ -28,7 +28,7 @@ IMAGE:=$(CME_TARGET)
 
 # Options for Platforms specific DD lvl
 
-$(IMAGE)_COMMONFLAGS = -DNIMBUS_DD_LEVEL=1
+$(IMAGE)_COMMONFLAGS = -DNIMBUS_DD_LEVEL=10
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n20.mk b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n20.mk
index aa709503..ae01bf98 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_p9n20.mk
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_p9n20.mk
@@ -29,7 +29,7 @@ IMAGE_EDITOR:=cmeImgEdit.exe
 
 # Options for Platforms specific tuning
 
-$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=2
+$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=20
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h
index 800f99ef..9ce0a2c5 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h
@@ -52,7 +52,7 @@
 
 // @todo RTC 161182
 
-#if NIMBUS_DD_LEVEL == 1
+#if NIMBUS_DD_LEVEL == 10
     #define HW386841_NDD1_DSL_STOP1_FIX         1
     #define HW402407_NDD1_TLBIE_STOP_WORKAROUND 1
     #define HW405292_NDD1_PCBMUX_SAVIOR         1
@@ -60,7 +60,7 @@
     #define RUN_NDD1_ABIST_IN_PARALLEL_MODE     1
 #endif
 
-#if NIMBUS_DD_LEVEL == 2 || DISABLE_CME_DUAL_CAST == 1
+#if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1
     // NDD2: no catchup due to dual cast bug
     #undef  SKIP_ENTRY_CATCHUP
     #undef  SKIP_EXIT_CATCHUP
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index e275f84b..4f54fae3 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -291,7 +291,7 @@ p9_cme_stop_entry()
     MARK_TAG(BEGINSCOPE_STOP_ENTRY, core)
     //===================================
 
-#if NIMBUS_DD_LEVEL == 2 || DISABLE_CME_DUAL_CAST == 1
+#if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1
 
     uint32_t dual_core   = core;
     uint32_t single_core = CME_MASK_C0;
@@ -693,7 +693,7 @@ p9_cme_stop_entry()
             PK_TRACE("Clear SCAN_REGION_TYPE prior to stop core clocks");
             CME_PUTSCOM(C_SCAN_REGION_TYPE, core, 0);
 
-#if NIMBUS_DD_LEVEL == 1
+#if NIMBUS_DD_LEVEL == 10
 
             // NDD1: Core Global Xstop FIR
             if (core & CME_MASK_C0)
@@ -1174,7 +1174,7 @@ p9_cme_stop_entry()
             //----------------------------------------------------------------------
 
 // NDD1 workaround to save cme image size
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
             if ((G_cme_stop_record.req_level[0] >= STOP_LEVEL_8) &&
                 (G_cme_stop_record.req_level[1] >= STOP_LEVEL_8))
@@ -1324,7 +1324,7 @@ p9_cme_stop_entry()
                 }
             }
 
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
             PK_TRACE("Drop PPM_WRITE_DISABLE via CPMMR[0]");
             CME_PUTSCOM(CPPM_CPMMR_CLR, core, BIT64(0));
@@ -1372,7 +1372,7 @@ p9_cme_stop_entry()
         PK_TRACE("+++++ +++++ END OF STOP ENTRY +++++ +++++");
         //--------------------------------------------------------------------------
 
-#if NIMBUS_DD_LEVEL == 2 || DISABLE_CME_DUAL_CAST == 1
+#if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1
 
         // NDD2: dual cast workaround loop end
     }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index cdff8d2e..e716ce7a 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -500,7 +500,7 @@ p9_cme_stop_exit()
     MARK_TAG(BEGINSCOPE_STOP_EXIT, core)
     //==================================
 
-#if NIMBUS_DD_LEVEL == 2 || DISABLE_CME_DUAL_CAST == 1
+#if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1
 
     uint32_t dual_core   = core;
     uint32_t single_core = CME_MASK_C0;
@@ -883,7 +883,7 @@ p9_cme_stop_exit()
 
             scom_data.value = pCmeImgHdr->g_cme_cpmr_PhyAddr & BITS64(13, 30); //HRMOR[13:42]
 
-#if NIMBUS_DD_LEVEL == 1
+#if NIMBUS_DD_LEVEL == 10
 #if !SKIP_RAM_HRMOR
 
             PK_TRACE("Activate thread0 for RAM via THREAD_INFO[18]");
@@ -1025,7 +1025,7 @@ p9_cme_stop_exit()
 
         p9_cme_stop_exit_end(core, spwu_stop);
 
-#if NIMBUS_DD_LEVEL == 2 || DISABLE_CME_DUAL_CAST == 1
+#if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1
 
         // NDD2: dual cast workaround loop end
     }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
index a103e6b4..53abdb2c 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
@@ -80,7 +80,7 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type)
     PK_TRACE("Setting scan length count");
 
     // Set bits 59:63 to 24 for the NSL_FILL_COUNT
-#if NIMBUS_DD_LEVEL == 1
+#if NIMBUS_DD_LEVEL == 10
     scom_data =  ((uint64_t)2410 << SHIFT64(11)) | 24;
 #else
     scom_data =  ((uint64_t)1024 << SHIFT64(11)) | 24;
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
index 8d852035..d1ed529b 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
@@ -70,7 +70,7 @@ p9_hcd_core_scominit(uint32_t core)
     PK_TRACE("Update Core Hang Pulse Dividers via C_HANG_CONTROL[0-15]");
     CME_GETSCOM(C_HANG_CONTROL, core, scom_data.value);
     scom_data.words.upper &= ~BITS32(0, 16);
-#if NIMBUS_DD_LEVEL == 1
+#if NIMBUS_DD_LEVEL == 10
     scom_data.words.upper |= (CORE_HANG_LIMIT_100_HANG_PULSES << SHIFT32(7));
 #else
     scom_data.words.upper |= (CORE_HANG_LIMIT_3_HANG_PULSES   << SHIFT32(7));
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9c10.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9c10.mk
index d1bb64e6..aebfb985 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9c10.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9c10.mk
@@ -28,7 +28,7 @@ IMAGE:=$(PSTATE_TARGET)
 #Note: Flags are resolved later - so local variables can't be
 # used to build them
 $(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=0
-$(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=1
+$(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=10
 #$(IMAGE)_COMMONFLAGS+= -fstack-usage
 
 include $(PGPE_SRCDIR)/pstate_gpe/pstate_common.mk
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9n10.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9n10.mk
index 597bd5b5..97525d45 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9n10.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9n10.mk
@@ -25,7 +25,7 @@
 PSTATE_TARGET := pstate_gpe_p9n10
 IMAGE := $(PSTATE_TARGET)
 
-$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=1
+$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=10
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
 include $(PGPE_SRCDIR)/pstate_gpe/pstate_common.mk
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9n20.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9n20.mk
index d1bc040a..719c100a 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9n20.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe_p9n20.mk
@@ -25,7 +25,7 @@
 PSTATE_TARGET:=pstate_gpe_p9n20
 IMAGE := $(PSTATE_TARGET)
 
-$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=2
+$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=20
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
 include $(PGPE_SRCDIR)/pstate_gpe/pstate_common.mk
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
index 444cbe24..52887185 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
@@ -118,7 +118,7 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg)
 
     /// @todo RTC166917 Check the Global Checkstop FIR
 
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
     PK_TRACE("Drop flushmode_inhibit via CPLT_CTRL0[2]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_CLEAR, quad), BIT64(2));
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
index 62f9d989..7d4fd60f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
@@ -116,7 +116,7 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
                 scom_data.words.upper &= ~(BIT32(1) | BITS32(14, 8) | BIT32(22));
                 scom_data.words.upper |= (BIT32(2) | BIT32(11) | BIT32(17) | BIT32(19));
 
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
                 scom_data.words.upper |=  (BIT32(5) | BIT32(30));
 
@@ -149,7 +149,7 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
                             scom_data.value);
                 scom_data.words.upper &= ~BIT32(9);
 
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
                 scom_data.words.lower |=  BIT64SH(51);
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
index eeaf6764..11d3aeb8 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
@@ -185,7 +185,7 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
 
 #endif
 
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
     PK_TRACE("Drop flushmode_inhibit via CPLT_CTRL0[2]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_CLEAR, quad), BIT64(2));
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index bc57a656..fbbd1584 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -346,7 +346,7 @@ p9_sgpe_stop_entry()
         }
 
 // NDD1 workaround to save cme image size
-#if NIMBUS_DD_LEVEL == 1
+#if NIMBUS_DD_LEVEL == 10
 
         PK_TRACE("Assert L2+NCU purge and NCU tlbie quiesce via SICR[18,21,22]");
         // insert tlbie quiesce before ncu purge to avoid window condition
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
index a353f591..0b6042b9 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
@@ -266,7 +266,7 @@ void p9_sgpe_stop_exit_end(uint32_t cexit, uint32_t qspwu, uint32_t qloop)
         // reset clevel to 0 if core is going to wake up
         G_sgpe_stop_record.level[qloop][cloop] = 0;
 
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
         p9_dd1_cppm_unicast_wr(
             GPE_SCOM_ADDR_CORE(CPPM_CPMMR,     ((qloop << 2) + cloop)),
@@ -318,7 +318,7 @@ p9_sgpe_stop_exit()
     uint32_t      spin            = 0;
 #endif
 #endif
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
     uint32_t      fused_core_mode = 0;
 #endif
 #if !SKIP_IPC
@@ -624,7 +624,7 @@ p9_sgpe_stop_exit()
 
 #endif
 
-#if NIMBUS_DD_LEVEL == 1
+#if NIMBUS_DD_LEVEL == 10
 
             // EPM only:
             // EPM doesnt have real homer images and pba setup to access homer
@@ -865,7 +865,7 @@ p9_sgpe_stop_exit()
                     }
 
 
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
                     GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SISR, qloop, ex_index),
                                 scom_data.value);
@@ -892,7 +892,7 @@ p9_sgpe_stop_exit()
                                 cme_flags |= (BIT32(CME_STOP_ENTRY_FIRST_C0) >> cloop);
                             }
 
-#if NIMBUS_DD_LEVEL != 1
+#if NIMBUS_DD_LEVEL != 10
 
                             if (fused_core_mode)
                             {
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
index 01e7745e..c7a32c22 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
@@ -39,7 +39,7 @@
 #define PLATFORM_PANIC_CODES_H "sgpe_panic_codes.h"
 // @todo RTC 161182
 
-#if NIMBUS_DD_LEVEL == 1
+#if NIMBUS_DD_LEVEL == 10
     #define HW386311_NDD1_PBIE_RW_PTR_STOP11_FIX            1
     #define HW388878_NDD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX 1
     #define NDD1_FUSED_CORE_MODE_SCAN_FIX                   1
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
index 30fdc996..cf8219e2 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
@@ -115,7 +115,7 @@ $(IMAGE)_COMMONFLAGS+= -DDEV_DEBUG=0
 
 # Options for Platforms specific tuning
 
-$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=1
+$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=10
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9c10.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9c10.mk
index 7766eb7d..5e48960c 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9c10.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9c10.mk
@@ -44,7 +44,7 @@ IMAGE := $(STOP_TARGET)
 # Options for Platforms specific tuning
 
 $(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=0
-$(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=1
+$(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=10
 
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9n10.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9n10.mk
index 29ea0fc8..70d3c5e4 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9n10.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9n10.mk
@@ -39,7 +39,7 @@ IMAGE := $(STOP_TARGET)
 
 # Options for Platforms specific tuning
 
-$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=1
+$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=10
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9n20.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9n20.mk
index dd56ceec..311a516a 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9n20.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe_p9n20.mk
@@ -40,7 +40,7 @@ IMAGE := $(STOP_TARGET)
 
 # Options for Platforms specific tuning
 
-$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=2
+$(IMAGE)_COMMONFLAGS+= -DNIMBUS_DD_LEVEL=20
 $(IMAGE)_COMMONFLAGS+= -DCUMULUS_DD_LEVEL=0
 
 $(IMAGE)_COMMONFLAGS+= -DLAB_P9_TUNING=0