diff options
| author | Chris Steffen <cwsteffen@us.ibm.com> | 2018-06-19 14:51:14 -0500 |
|---|---|---|
| committer | Richard J. Knight <rjknight@us.ibm.com> | 2018-07-03 15:45:40 -0500 |
| commit | 6d1fd2cc84e1a089c396eeed430236f7f8d44323 (patch) | |
| tree | 34bea334d690665d2e51f21327ae5e0a4ce147e6 | |
| parent | 169b85d36210a34d539dd770baf489f367b41870 (diff) | |
| download | talos-hcode-6d1fd2cc84e1a089c396eeed430236f7f8d44323.tar.gz talos-hcode-6d1fd2cc84e1a089c396eeed430236f7f8d44323.zip | |
Alink Hot Repair Fix
Change-Id: Ie6fc10cefe5084af41a14c5edfd31d4cdc6f591d
CQ: HW446279
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61067
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Gary A. Peterson <garyp@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
9 files changed, 7621 insertions, 13 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/io_lib.c b/import/chips/p9/procedures/ppe_closed/ippe/ioa/io_lib.c new file mode 100644 index 00000000..6c596ca0 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/io_lib.c @@ -0,0 +1,368 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/ippe/ioa/io_lib.c $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// *!--------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2016 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!--------------------------------------------------------------------------- +// *! FILENAME : io_lib.c +// *! TITLE : +// *! DESCRIPTION : +// *! +// *! OWNER NAME : John Rell Email: jgrell@us.ibm.com +// *! BACKUP NAME : Mike Spear Email: mspear@us.ibm.com +// *! +// *!--------------------------------------------------------------------------- +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version ID: |Author: | Comment: +// ------------|--------|------------------------------------------------------- +// vbr17072600 |vbr | Copied gcr_wr_raw from other branch. +// vbr16081800 |vbr | Moved some functions from eo_common to io_lib (and renamed some). +// vbr16070700 |vbr | Removed deprecated put/get; minor stack/code size optimizations +// vbr16070100 |vbr | Removed RMW option from put_ptr_int (only does RMW). +// vbr16062800 |vbr | Optimization +// mbs16062400 |mbs | Added gcr_addr struct +// mbs16062400 |mbs | Added put_ptr, put_ptr_fast, and get_ptr functions +// vbr16050500 |vbr |- Moved mem_regs and various functions from eo_common to io_lib +// vbr16050300 |vbr |- Added lcl_get() +// mbs16040800 |mbs |- Added instance parm to mmio_put and mmio_get, and adjusted bit fields +// ----------------------------------------------------------------------------- + +#include "io_lib.h" +#include "pk.h" + +#include "ppe_mem_reg_const_pkg.h" +#include "ppe_com_reg_const_pkg.h" +#include "ppe_opt_reg_const_pkg.h" + + + +//////////////////////////////////////////////////////////////////////////////////////////// +// GCR ADDRESS FORMING FUNCTIONS +//////////////////////////////////////////////////////////////////////////////////////////// + +// These functions are setup to interace with a "t_gcr_addr" structure which is only infrequently updated. +// A pointer to this structure can be passed down the call stack and provide all the necessary information +// to put and get functions as well as precalculated masks + +void set_gcr_addr(t_gcr_addr* gcr_addr, int bus_id, int reg_id, int lane) +{ + gcr_addr->bus_id = bus_id; + gcr_addr->reg_id = reg_id; + gcr_addr->lane = lane; + + // Single thread on gcr_port 0 + gcr_addr->gcr_port_addr = 0xC0000200; + + gcr_addr->gcr_read_packet = + 0x9000000000E00000 //base_gcr_write_msg + | ((uint64_t)bus_id << (63 - 10)) // 53 + | ((uint64_t)reg_id << (63 - 16)) // 47 + | ((uint64_t)lane << (63 - 31)); // 32 + + gcr_addr->gcr_write_packet = gcr_addr->gcr_read_packet | 0x0800000000000000; + + return; +}; + + +void set_gcr_addr_bus_id(t_gcr_addr* gcr_addr, int bus_id) +{ + gcr_addr->bus_id = bus_id; + + gcr_addr->gcr_read_packet = (gcr_addr->gcr_read_packet & 0xf81fffffffffffff) + | ((uint64_t)bus_id << (63 - 10)); + + gcr_addr->gcr_write_packet = gcr_addr->gcr_read_packet | 0x0800000000000000; + + return; +} + +void set_gcr_addr_reg_id(t_gcr_addr* gcr_addr, int reg_id) +{ + gcr_addr->reg_id = reg_id; + + gcr_addr->gcr_read_packet = (gcr_addr->gcr_read_packet & 0xffe07fffffffffff) + | ((uint64_t)reg_id << (63 - 16)); + + gcr_addr->gcr_write_packet = gcr_addr->gcr_read_packet | 0x0800000000000000; + + return; +} + +void set_gcr_addr_lane(t_gcr_addr* gcr_addr, int lane) +{ + gcr_addr->lane = lane; + + gcr_addr->gcr_read_packet = (gcr_addr->gcr_read_packet & 0xffffffe0ffffffff) + | ((uint64_t)lane << (63 - 31)); + + gcr_addr->gcr_write_packet = gcr_addr->gcr_read_packet | 0x0800000000000000; + + return; +} + + +//////////////////////////////////////////////////////////////////////////////////////////// +// HW I/O FUNCTIONS +//////////////////////////////////////////////////////////////////////////////////////////// + +void mmio_put(int instance, int addr, int data) +{ + uint64_t volatile* lclmem_addr = (uint64_t*)(0xC0000250); + + (*lclmem_addr) = + 0x8000000000000000 // 0, write + | ((uint64_t)instance << (63 - 11)) // 2:3, DL Instance (00 : DL0, 01 : DL1, 10 : DL2, 11 : PHY) + | ((uint64_t)addr << (63 - 11)) // 11:31 + | ((uint64_t)data); // 32:63 + + // poll for msg rcvd flag to indicate an echo + while ( ((*lclmem_addr) & 0x3) == 0x0 ); + + return; +} + +uint32_t mmio_get(int instance, int addr) +{ + uint64_t volatile* lclmem_addr = (uint64_t*)(0xC0000250); + + (*lclmem_addr) = + 0x0000000000000000 // 0, read + | ((uint64_t)instance << (63 - 11)) // 2:3, DL Instance (00 : DL0, 01 : DL1, 10 : DL2, 11 : PHY) + | ((uint64_t)addr << (63 - 11)); // 11:31 + + // poll for read data flag + uint64_t result = (*lclmem_addr); + + while ( (result & 0x1) == 0x0 ) + { + result = (*lclmem_addr); + }; + + uint32_t r_data = (uint32_t)(result >> 32); + + return r_data; // 16 bits + + //return; +} + + +// This allows writing a raw GCR packet to the bus. +// Primarily meant as a workaround for the GCR interrupt packet not being ack'd. +void gcr_wr_raw(t_gcr_addr* gcr_addr, uint64_t packet) +{ + // Setup the pointer + uint64_t volatile* lclmem_addr = (uint64_t*)gcr_addr->gcr_port_addr; + + // wait on previous op while start bit is set but echo flag is not set + while (((*lclmem_addr) & 0xC000000000000003) == 0x8000000000000000 ); + + // send write op and exit + (*lclmem_addr) = packet; +} //gcr_wr_raw + + +// fast put where the packet is preformed and the data field uses all 16 bits so we just need to fill in the reg addr and 16-bit data +//void put_ptr_fast_int(t_gcr_addr *gcr_addr, int reg_addr, int endbit, int data) { +void put_ptr_fast_int(t_gcr_addr* gcr_addr, uint64_t reg_addr, int shift_amt, int data) +{ + //uint64_t w_data = data << (15+4 - endbit); + uint64_t w_data = data << shift_amt; + + uint64_t packet = + gcr_addr->gcr_write_packet + | ((uint64_t)reg_addr) // already shifted + | ((uint64_t)w_data); + + // Put result to reg + uint64_t volatile* lclmem_addr = (uint64_t*)gcr_addr->gcr_port_addr; + + // wait on previous op while start bit is set but echo flag is not set + while (((*lclmem_addr) & 0xC000000000000003) == 0x8000000000000000 ); + + // send write op and exit + (*lclmem_addr) = packet; + + return; +} + + +// put where the packet is preformed. always does read-modify-write. +void put_ptr_int(t_gcr_addr* gcr_addr, uint64_t reg_addr, uint64_t and_mask, int shift_amt, int data) +{ + uint64_t volatile* lclmem_addr = (uint64_t*)gcr_addr->gcr_port_addr; + uint64_t packet; + uint64_t w_data; + + // For a read-modify-write, first do a read of the register in question. + // However we don't need to do a full get() because we don't care about shifting the + // data around. + + packet = + gcr_addr->gcr_read_packet + | ((uint64_t)reg_addr);// already shifted + + // wait on previous op while start bit is set but echo flag or read response flag is not set + while (((*lclmem_addr) & 0xC000000000000003) == 0x8000000000000000 ); + + (*lclmem_addr) = packet; + + + // ****************************************************************** + // Form AND and OR masks - do all this while the read command is running + // ****************************************************************** + + /* + // Form the mask by shifting a one N+1 times and then subtracting one to make a ones mask of length N + uint64_t and_mask = (1 << (endbit - startbit + 1)) - 1; + + // Shift the mask into the proper bit field for the gcr packet + and_mask <<= (15+4 - endbit); + + // Invert the mask so all the bits except the start/end bit data field are ones (e.g. xfffffffffffff1ff) + and_mask = (~and_mask); + + // Now mask off all but the actual 16 bit data field, so we have ones with hole in the middle (e.g. x00000000000ff1f0) + and_mask &= 0x00000000000ffff0; + + w_data = data << (15+4 - endbit); + */ + w_data = data << shift_amt; + + // Prepare or_mask + uint64_t or_mask = + gcr_addr->gcr_write_packet + | ((uint64_t)reg_addr) // already shifted + | ((uint64_t)w_data); // 4 + + // ****************************************************************** + + // poll for read response packet flag to indicate returned data + packet = (*lclmem_addr); + + while ( (packet & 0x4000000000000000) == 0x0 ) + { + packet = (*lclmem_addr); + }; + + // Apply masks + packet &= and_mask; + + packet |= or_mask; + + // write data back and exit + (*lclmem_addr) = packet; + + // poll for msg rcvd flag to indicate an echo + //while ( ((*lclmem_addr) & 0x3) == 0x0 ); + + return; +} //put_ptr_int + +void put_ptr_fast_id(t_gcr_addr* gcr_addr, int reg_id, uint64_t reg_addr, int endbit, int data) +{ + set_gcr_addr_reg_id(gcr_addr, reg_id); + put_ptr_fast(gcr_addr, reg_addr, endbit, data); +} + +void put_ptr_id (t_gcr_addr* gcr_addr, int reg_id, uint64_t reg_addr, int startbit, int endbit, int data, int rmw) +{ + set_gcr_addr_reg_id(gcr_addr, reg_id); + put_ptr(gcr_addr, reg_addr, startbit, endbit, data, rmw); +} + +uint32_t get_ptr_id (t_gcr_addr* gcr_addr, int reg_id, uint64_t reg_addr, int startbit, int endbit) +{ + set_gcr_addr_reg_id(gcr_addr, reg_id); + return get_ptr(gcr_addr, reg_addr, startbit, endbit); +} + + +// get where the packet is preformed +//uint32_t get_ptr_int(t_gcr_addr *gcr_addr, int reg_addr, int startbit, int endbit) { +uint32_t get_ptr_int(t_gcr_addr* gcr_addr, uint64_t reg_addr, uint64_t and_mask, int shift_amt) +{ + uint64_t volatile* lclmem_addr = (uint64_t*)(gcr_addr->gcr_port_addr); + + (*lclmem_addr) = + gcr_addr->gcr_read_packet + | ((uint64_t)reg_addr);// already shifted + + /* + // ****************************************************************** + // Form AND mask - do all this while the read command is running + // ****************************************************************** + // Form the mask by shifting a one N+1 times and then subtracting one to make a ones mask of length N + uint64_t and_mask = (1 << (endbit - startbit + 1)) - 1; + + // Shift the mask into the proper bit field for the gcr packet + uint32_t shift_amt = (4 + 15 - endbit); + + and_mask <<= shift_amt; + + // ****************************************************************** + */ + + // poll for read response packet flag to indicate returned data + uint64_t result = (*lclmem_addr); + + while ( (result & 0x4000000000000000) == 0x0 ) + { + result = (*lclmem_addr); + }; + + uint32_t r_data = (uint32_t)((result & and_mask) >> shift_amt); + + return r_data; // 16 bits +} + + +void lcl_put(int reg_addr, int width, int data) +{ + + uint64_t volatile* lclmem_addr = (uint64_t*)(0xC0000000 | reg_addr); + + (*lclmem_addr) = (uint64_t)data << (64 - width); + + return; +} + +uint32_t lcl_get(int reg_addr, int width) +{ + uint64_t volatile* lclmem_addr = (uint64_t*)(0xC0000000 | reg_addr); + uint32_t r_data = (uint32_t)((*lclmem_addr) >> (64 - width)); + return r_data; +} + +void set_fir() +{ + uint64_t volatile* fir_addr = (uint64_t*)(0xC0000240); + + (*fir_addr) = 0x1; // Any write will trigger the FIR, regardless of data + + return; +} diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/io_lib.h b/import/chips/p9/procedures/ppe_closed/ippe/ioa/io_lib.h new file mode 100644 index 00000000..9f28dfe6 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/io_lib.h @@ -0,0 +1,433 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/ippe/ioa/io_lib.h $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// *!--------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2016 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!--------------------------------------------------------------------------- +// *! FILENAME : io_lib.c +// *! TITLE : +// *! DESCRIPTION : +// *! +// *! OWNER NAME : John Rell Email: jgrell@us.ibm.com +// *! BACKUP NAME : Mike Spear Email: mspear@us.ibm.com +// *! +// *!--------------------------------------------------------------------------- +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version ID: |Author: | Comment: +// ------------|--------|------------------------------------------------------- +// vbr17072600 |vbr | Copied gcr_wr_raw from other branch. +// vbr16082300 |vbr | get_enabled_lanes() now returns 0 in bits 24-31. +// vbr16081900 |vbr | Adjusted the size of variables in the gcr_addr struct. +// vbr16081800 |vbr | Moved some functions from eo_common to io_lib (and renamed some). +// vbr16081700 |vbr | Added address range checking to pg_addr() and pl_addr() functions. +// vbr16072700 |vbr | Modified set_debug_state() to no longer read the debug_state before setting it (saves 1 instruction per call) +// vbr16072100 |vbr | Added div_uint32 (~216B saved versus __divsi3) and mult_int16 (~72B saved and much faster than __mulsi3) +// vbr16071200 |vbr | Changed to rx_eye_opt_state for set_debug_state. +// vbr16070700 |vbr | Removed deprecated put/get; minor stack/code size optimizations +// vbr16070100 |vbr | Removed RMW option from put_ptr_int (only does RMW). +// vbr16062800 |vbr | Optimization of put_ptr wrapper +// mbs16062400 |mbs | Added gcr_addr struct +// mbs16062400 |mbs | Added put_ptr, put_ptr_fast, and get_ptr functions +// vbr16060700 |vbr |- Simplified TwosCompToInt() +// vbr16052700 |vbr |- Removed hw write from debug_state +// vbr16052400 |vbr |- Added set_debug_state +// vbr16050500 |vbr |- Moved more from eo_common to io_lib (mem_regs, functions) +// vbr16050300 |vbr |- Added lcl_get() +// vbr16042100 |vbr |- Moved helpful constants from eo_common.h +// mbs16040800 |mbs |- Added instance parm to mmio_put and mmio_get, and adjusted bit fields +// ----------------------------------------------------------------------------- + +#ifndef _IO_LIB_H_ +#define _IO_LIB_H_ + +#define IOO 1 + +#include <stdbool.h> +#include <stdint.h> + +#include "pk.h" + +#include "ppe_mem_reg_const_pkg.h" +#include "ppe_com_reg_const_pkg.h" +#include "ppe_opt_reg_const_pkg.h" + + +//////////////////////////////////////////////////////////////////////////////////////////// +// MATH FUNCTIONS +// Most of these are so simple they should remain inline. +// Some can even be converted to macros (if careful to avoid double evaluation). +//////////////////////////////////////////////////////////////////////////////////////////// + +// Absolute value function to replace stdlib::abs() +// Note that it should compile to three instructions which are essentially a conditional NOT(v)+1: +// ffff1b00: 7d 47 fe 70 srawi r7,r10,31 +// ffff1b04: 7c e8 52 78 xor r8,r7,r10 +// ffff1b08: 7d 07 40 50 subf r8,r7,r8 +//static inline int abs(int v) { return ((v < 0) ? -v : v); } + +// Min/Max functions. MIN/MAX macros also exist in pk.h +//static inline int min(int a, int b) { return ((a < b) ? a : b); } +//static inline int max(int a, int b) { return ((a > b) ? a : b); } + +//Convert a two's complement value to an integer, length is number of bits of input (two's complement) value +static inline int TwosCompToInt(int val, int length) +{ + return (val << (32 - length) >> (32 - length)); +} + +//Convert a signed-magnitude value to an integer, length is number of bits of input (signed-magnitude) value +static inline int SignedMagToInt(int val, int length) +{ + int mask = (1 << (length - 1)) - 1; + int ret_val = val & mask; + + if (val > ret_val) + { + ret_val = -ret_val; + } + + return ret_val; +} + +//Convert an integer to a signed-magnitude value, length is number of bits of output (signed-magnitude) value +static inline int IntToSignedMag(int val, int length) +{ + int mag = (val < 0) ? -val : val; //abs(val); + int sign = (val < 0) ? (1 << (length - 1)) : 0; + return (sign | mag); +} + +// Convert servo_result (8-bit two's complement value) to a 32-bit integer; probably more efficeint than the TwosCompToInt function +static inline int ServoResultToInt(int v) +{ + return (v << 24 >> 24); // This should result in an extsb instruction +} + +// Convert DDC left/right edge (6-bit two's complement value) to a 32-bit integer; probably more efficeint than the TwosCompToInt function +static inline int DdcEdgeToInt(int v) +{ + return (v << 26 >> 26); +} + +// Convert path_offset (6-bit two's complement value) to a 32-bit integer; probably more efficeint than the TwosCompToInt function +static inline int PathOffsetToInt(int v) +{ + return (v << 26 >> 26); +} + +// Simple unsigned integer divide - returns floor(a/b) rather than rounding. Good to use when the expected result is small. +// Inline since very simple function that isn't used often. +static inline uint32_t div_uint32(uint32_t a, uint32_t b) +{ + int count = -1; + int val = a; + + do + { + val -= b; + count++; + } + while (val > 0); + + return ((uint32_t)count); +} + +// Simple signed 16x16 multiply (with a 32-bit result) that is meant to take advantage of the PPE's 16x16 multiplier. +// Do not pass in inputs as int16 because that causes the compiler to include extra instructions as it promotes everything to 32-bits. +// This function only looks at the bottom 16 bits of the value passed in, so it does not matter if it is a 32-bit input. +// Inline since it reduces to a single instruction. +static inline int mult_int16(int a, int b) +{ + int val; + // mullhw - Multiply Low Halfword to Word Signed + // (RT)0:31 <- (RA)16:31 x (RB)16:31 signed + // The low-order halfword of RA is multiplied by the low-order halfword of RB. The resulting signed product replaces the contents of RT. + asm( + "mullhw %[RT], %[RA], %[RB]" + : [RT] "=r" (val) + : [RA] "r" (a), [RB] "r" (b) + ); + return val; +} + + +// Simple macros for bit set/clear, register read/write, etc +// Address translation for RegDef to mem_reg. This must be used for mem_regs accesses. +// RX Per-Group Regs: 0b10xxxxxxx -> 0b11xxxxxxx (last 128 registers) +// RX Per-Lane Regs (0x60-0x67, 0x70-0x77): 0b0011x0xxx -> 0byyyyyxxxx (y = 5-bit lane #) +// Takes RegDef address (a), group/thread (g), and lane (l) +#define pg_addr(a, g) ({ PK_STATIC_ASSERT((a)>=0x100 && (a)<=0x17F); ((a) | 0x180); }) +#define pl_addr(a, g, l) ({ PK_STATIC_ASSERT(((a)>=0x60 && (a)<=0x67) || ((a)>=0x70 && (a)<=0x77)); ( ((a) & 0x007) | (((a) & 0x010) >> 1) | ((l) << 4) ); }) + +// bit_set/bit_clr take a register (r) and a mask (m) - NOT bit position +#define bit_set(r, m) (r |= (m)) +#define bit_clr(r, m) (r &= ~(m)) + +// bitfield_put/get take a register (r), a mask (m), a shift (s), and a value (v) for put +#define bitfield_get(r, m, s) ((r & (m)) >> (s)) +#define bitfield_put(r, m, s, v) (r = ( (r & ~(m)) | (((v) << (s)) & (m)) )) + +// put/get for work regs takes an address (a), a mask (m), a shift (s), and a value (v) for put +#define mem_regs_u16_get(a, m, s) (bitfield_get(mem_regs_u16[a], m, s)) +#define mem_regs_u16_put(a, m, s, v) (bitfield_put(mem_regs_u16[a], m, s, v)) +#define mem_regs_u16_bit_set(a, m) (bit_set(mem_regs_u16[a], m)) +#define mem_regs_u16_bit_clr(a, m) (bit_clr(mem_regs_u16[a], m)) + +// put/get for fw regs takes an address (a), a mask (m), a shift (s), and a value (v) for put +#define fw_regs_u16_get(a, m, s) (bitfield_get(fw_regs_u16[a], m, s)) +#define fw_regs_u16_put(a, m, s, v) (bitfield_put(fw_regs_u16[a], m, s, v)) +#define fw_regs_u16_bit_set(a, m) (bit_set(fw_regs_u16[a], m)) +#define fw_regs_u16_bit_clr(a, m) (bit_clr(fw_regs_u16[a], m)) +#define fw_addr(a, g) ( (a) ) + + + +//////////////////////////////////////////////////////////////////////////////////////////// +// SLEEP & WAIT +//////////////////////////////////////////////////////////////////////////////////////////// +// Constants to use with io_spin. +// Have seperate constants for IOO and NV since they are different images and have different grid clock frequencies. +// For IOF, we use a single image regardless of whether we are in 4:1 or 8:1 mode; for the code to function correctly, +// 1 us must be specified in cycles of the slower clock bewteen the two modes. +#define cycles_1us 201 +#define ui_per_cycle 128 + +// Wait by spinning (busy wait) +// Input parameter is number of PPE core clock cycles to wait. +// The PPE runs on the slow_clock (nest/8): +// IOO: C128 clock = 201 MHz = 4.975 ns / cycle +// IOO (NV): C128 clock = 195 MHz = 5.128 ns / cycle +// IOF (8:1): C64 clock = 250 MHz = 4.000 ns / cycle +// IOF (4:1): C32 clock = 300 MHz = 3.333 ns / cycle +static inline void io_spin(unsigned int cycles) +{ + // Divide cycles by 2 to account for the bdnz instruction we are using to spin taking 2 cycles to execute (page 18 of PPE manual). + unsigned int loop_cycles = (cycles >> 1); + unsigned int i = 0; + + for (i = 0; i < loop_cycles; i++) + { + // To prevent this loop from being optimized out, we place an empty assembly instruction in the loop. + // An example of the resulting assembly from run_servo_op() which calls io_spin(500): + // ffff0960: 39 20 01 f4 li r9,500 + // ffff0964: 7d 29 03 a6 mtctr r9 + // ffff0968: 42 00 00 00 bdnz ffff0968 <run_servo_op+0x54> + asm(""); // empty assembly instruction so this loop does not get optimized out + } +}//io_spin + +// Wrapper for io_spin in terms of UI +static inline void io_spin_ui(unsigned int ui) +{ + unsigned int cycles = (ui / ui_per_cycle); + io_spin(cycles); +} //io_spin_ui + +// Wrapper for io_spin in terms of mircoseconds +static inline void io_spin_us(unsigned int us) +{ + unsigned int cycles = (us * cycles_1us); + io_spin(cycles); +} //io_spin_us + + +//////////////////////////////////////////////////////////////////////////////////////////// +// HW I/O FUNCTIONS +//////////////////////////////////////////////////////////////////////////////////////////// +// reg_id options - Since put/get use the user-programmable format, the reg_id is just 0x00 or 0x20 for RX/TX +#define rx_group 0x00 +#define tx_group 0x20 + +// rmw options for put +#define read_modify_write 1 +#define fast_write 0 + +// constant for the lane field to indicate a broadcast put +#define bcast_all_lanes 31 + +// Local PPE Register Addresses +#define scom_ppe_work1_lcl_addr 0x0260 +#define scom_ppe_work2_lcl_addr 0x0270 +#define scom_ppe_flags_lcl_addr 0x0280 +#define scom_ppe_flags_set_lcl_addr 0x0290 +#define scom_ppe_flags_clr_lcl_addr 0x02A0 + +// SLS Message constants +#define sls_nop 0x00 +#define shadow_req 0x01 +#define shadow_done 0x02 +#define shadow_rpr_req 0x03 +#define shadow_rpr_done 0x04 +#define unshadow_req 0x05 +#define unshadow_done 0x06 +#define unshadow_rpr_req 0x07 +#define unshadow_rpr_done 0x08 +#define sls_exception 0x09 +#define sls_init_done 0x0A +#define sls_recal_req 0x0B +#define sls_recal_running 0x0C +#define sls_recal_done 0x0D +#define sls_recal_failed 0x0E +#define sls_recal_abort 0x0F +#define sls_exception2 0x10 +#define sls_eye_opt_done 0x18 +#define sls_init_done_ack 0x19 +#define sls_recal_ack 0x1B +#define sls_recal_abort_ack 0x1F + +// FW register map +#define fw_ctl_reg_addr 0x00 +#define fw_stop_thread_startbit 0x01 +#define fw_stop_thread_stopbit 0x01 +#define fw_stop_thread_mask 0x80 +#define fw_stop_thread_shift 15 + + +// Address Forming FUNCTIONS and types +// IOF: This struct is only 25B, but gets re-aligned to 32B. +// IOO: This struct is only 23B, but gets re-aligned to 24B. +typedef struct struct_gcr_addr +{ + // Input data + uint8_t bus_id; + uint8_t reg_id; + uint8_t lane; + + // Calculated values + uint32_t gcr_port_addr; + uint64_t gcr_write_packet; + uint64_t gcr_read_packet; +} t_gcr_addr; + +void set_gcr_addr(t_gcr_addr* gcr_addr, int bus_id, int reg_id, int lane); +void set_gcr_addr_bus_id(t_gcr_addr* gcr_addr, int bus_id); +void set_gcr_addr_reg_id(t_gcr_addr* gcr_addr, int reg_id); +void set_gcr_addr_lane(t_gcr_addr* gcr_addr, int lane); + +//#if defined(IOO) || defined(NV) +//static inline int get_gcr_addr_thread(t_gcr_addr *gcr_addr) {return 0;} +//#endif +static inline int get_gcr_addr_bus_id(t_gcr_addr* gcr_addr) +{ + return gcr_addr->bus_id; +} +static inline int get_gcr_addr_reg_id(t_gcr_addr* gcr_addr) +{ + return gcr_addr->reg_id; +} +static inline int get_gcr_addr_lane (t_gcr_addr* gcr_addr) +{ + return gcr_addr->lane; +} + + +// MMIO Port +void mmio_put(int instance, int addr, int data); +uint32_t mmio_get(int instance, int addr); + +// GCR Ports +void gcr_wr_raw(t_gcr_addr* gcr_addr, uint64_t packet); +void put_ptr_fast_int(t_gcr_addr* gcr_addr, uint64_t reg_addr, int shift_amt, int data); +void put_ptr_int (t_gcr_addr* gcr_addr, uint64_t reg_addr, uint64_t and_mask, int shift_amt, + int data); // always does read-modify-write +uint32_t get_ptr_int (t_gcr_addr* gcr_addr, uint64_t reg_addr, uint64_t and_mask, int shift_amt); + +// Inline functions the pre-shift constant inputs (compiler should dissolve these) +static inline void put_ptr_fast(t_gcr_addr* gcr_addr, uint64_t reg_addr, int endbit, int data) +{ + put_ptr_fast_int( + gcr_addr, + (reg_addr << (63 - 25)), // reg_addr absolute shift - precomputed by compiler + (4 + 15 - endbit), // shift_amt - precomputed by compiler + data + ); +} + +// When rmw=0, this is the same as calling put_ptr_fast. Using a macro since does some weird code duplication when inline. +#define put_ptr(gcr_addr, reg_addr, startbit, endbit, data, rmw) { \ + if (rmw) \ + put_ptr_int( \ + (gcr_addr), \ + ((uint64_t)(reg_addr) << (63 - 25)), \ + (~ ( (uint64_t)( ((1 << ((endbit) - (startbit) + 1)) - 1) << (4 + 15 - (endbit)) ) ) ) & 0x00000000000ffff0, \ + (4 + 15 - (endbit)), \ + (data) \ + ); \ + else \ + put_ptr_fast_int( \ + (gcr_addr), \ + ((uint64_t)(reg_addr) << (63 - 25)), \ + (4 + 15 - (endbit)), \ + (data) \ + ); \ + } +/*static inline void put_ptr(t_gcr_addr* gcr_addr, uint64_t reg_addr, int startbit, int endbit, int data, int rmw) { + put_ptr_int( + gcr_addr, + (reg_addr << (63 - 25)), // reg_addr absolute shift - precomputed by compiler + (~ ( (uint64_t)( ((1 << (endbit - startbit + 1)) - 1) << (4 + 15 - endbit) ) ) ) & 0x00000000000ffff0, // and_mask - precomputed by compiler + (4 + 15 - endbit), // shift_amt - precomputed by compiler + data + ); +}*/ +#define put_ptr_field(gcr_addr, reg, data, rmw) put_ptr(gcr_addr, reg##_addr, reg##_startbit, reg##_endbit, data, rmw) + +static inline uint32_t get_ptr(t_gcr_addr* gcr_addr, uint64_t reg_addr, int startbit, int endbit) +{ + return get_ptr_int ( + gcr_addr, + (reg_addr << (63 - 25)), // reg_addr absolute shift - precomputed by compiler + ((1 << (endbit - startbit + 1)) - 1) << (4 + 15 - endbit), // and_mask - precomputed by compiler + (4 + 15 - endbit) // shift_amt - precomputed by compiler + ); + +} +#define get_ptr_field(gcr_addr, reg) get_ptr(gcr_addr, reg##_addr, reg##_startbit, reg##_endbit) + +void put_ptr_fast_id(t_gcr_addr* gcr_addr, int reg_id, uint64_t reg_addr, int endbit, int data); +void put_ptr_id (t_gcr_addr* gcr_addr, int reg_id, uint64_t reg_addr, int startbit, int endbit, int data, int rmw); +uint32_t get_ptr_id (t_gcr_addr* gcr_addr, int reg_id, uint64_t reg_addr, int startbit, int endbit); + + +// Local Registers +void lcl_put(int reg_addr, int width, int data); +uint32_t lcl_get(int reg_addr, int width); +void set_fir(); + + +//////////////////////////////////////////////////////////////////////////////////////////// +// SERVO OP FUNCTIONS +//////////////////////////////////////////////////////////////////////////////////////////// +// Run a servo op and wait to complete; do not read/return result. Slow procedure, so not much advantage to inline. +void run_servo_op(t_gcr_addr* gcr_addr, unsigned int servo_op, bool recal); + +// Run a servo op and wait for result; returns two's complement integer. +// Does so little that makes sense to inline, however gcc chooses not to inline it (probably since it is called so much). +int run_servo_op_and_get_result(t_gcr_addr* gcr_addr, unsigned int servo_op, bool recal); + + +#endif //_IO_LIB_H_ diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_a_common.c b/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_a_common.c new file mode 100644 index 00000000..487e72d5 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_a_common.c @@ -0,0 +1,74 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_a_common.c $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2015,2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_a_common.C +/// @brief IO Common Functions. +///----------------------------------------------------------------------------- +/// *HWP HWP Owner : Chris Steffen <cwsteffen@us.ibm.com> +/// *HWP HWP Backup Owner : Gary Peterson <garyp@us.ibm.com> +/// *HWP FW Owner : Jamie Knight <rjknight@us.ibm.com> +/// *HWP Team : IO +/// *HWP Level : 3 +/// *HWP Consumed by : FSP:HB +///----------------------------------------------------------------------------- +/// +/// @verbatim +/// a Common Functions +// +/// @endverbatim +///---------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include "p9_a_common.h" + +//----------------------------------------------------------------------------- +// Function Declarations +//----------------------------------------------------------------------------- +void localPut( const uint32_t i_addr, const uint64_t i_data) +{ + + uint64_t volatile* gcrPortAddr = (uint64_t*)(0xC0000000 | i_addr); + + (*gcrPortAddr) = i_data; + + return; +} + +uint64_t localGet( const uint32_t i_addr ) +{ + uint64_t volatile* gcrPortAddr = (uint64_t*)(0xC0000000 | i_addr); + return ( *gcrPortAddr ); +} + +void setFir() +{ + uint64_t volatile* firAddr = (uint64_t*)(0xC0000240); + + ( *firAddr ) = 0x1; // Any write will trigger the FIR, regardless of data + + return; +} diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_a_common.h b/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_a_common.h new file mode 100644 index 00000000..5c93394d --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_a_common.h @@ -0,0 +1,124 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_a_common.h $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2015,2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_a_common.h +/// @brief Abus Common Functions. +///----------------------------------------------------------------------------- +/// *HWP HWP Owner : Chris Steffen <cwsteffen@us.ibm.com> +/// *HWP HWP Backup Owner : Gary Peterson <garyp@us.ibm.com> +/// *HWP FW Owner : Jamie Knight <rjknight@us.ibm.com> +/// *HWP Team : IO +/// *HWP Level : 3 +/// *HWP Consumed by : FSP:HB +///----------------------------------------------------------------------------- +/// +/// @verbatim +/// Abus Common Functions +/// +/// @endverbatim +///---------------------------------------------------------------------------- +#ifndef _NV_LIB_H_ +#define _NV_LIB_H_ +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <stdint.h> + +// Local PPE Register Addresses +#define WORK1_REG 0x0260 +#define WORK2_REG 0x0270 +#define FLAGS_REG 0x0280 +#define FLAGS_SET_REG 0x0290 +#define FLAGS_CLR_REG 0x02A0 + +// Local Registers +void localPut( const uint32_t i_addr, const uint64_t i_data); +uint64_t localGet( const uint32_t i_addr ); +void setFir (); + + +//////////////////////////////////////////////////////////////////////////////////////////// +// MATH FUNCTIONS +// Most of these are so simple they should remain inline. +// Some can even be converted to macros (if careful to avoid double evaluation). +//////////////////////////////////////////////////////////////////////////////////////////// + +// Absolute value function to replace stdlib::abs() +static inline int abs( const int v ) +{ + return ((v < 0) ? -v : v); +} + +// Min/Max functions. MIN/MAX macros also exist in pk.h +static inline int min( const int a, const int b ) +{ + return ((a < b) ? a : b); +} +static inline int max( const int a, const int b ) +{ + return ((a > b) ? a : b); +} + +//Convert a two's complement value to an integer, length is number of bits of input (two's complement) value +static inline int twosCompToInt( const int val, const int length) +{ + int ret_val = 0; + int max = 1 << ( length - 1 ); + + if ( val >= max ) + { + ret_val = val - ( 2 * max ); + } + else + { + ret_val = val; + } + + return ret_val; +} + +//Convert a signed-magnitude value to an integer, length is number of bits of input (signed-magnitude) value +static inline int signedMagToInt( const int val, const int length ) +{ + int mask = (1 << (length - 1)) - 1; + int ret_val = val & mask; + + if (val > ret_val) + { + ret_val = -ret_val; + } + + return ret_val; +} + +//Convert an integer to a signed-magnitude value, length is number of bits of output (signed-magnitude) value +static inline int intToSignedMag( const int val, const int length ) +{ + int mag = (val < 0) ? -val : val; //abs(val); + int sign = (val < 0) ? (1 << (length - 1)) : 0; + return (sign | mag); +} + +#endif //_ABUS_LIB_H_ diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_abus_main.c b/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_abus_main.c index 98d50ae3..498be791 100644 --- a/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_abus_main.c +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/p9_abus_main.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,8 +23,8 @@ /* */ /* IBM_PROLOG_END_TAG */ /// -/// @file p9_nv_main.c -/// @brief NV Low Power Mode. +/// @file p9_a_main.c +/// @brief Abus Image ///----------------------------------------------------------------------------- /// *HWP HWP Owner : Chris Steffen <cwsteffen@us.ibm.com> /// *HWP HWP Backup Owner : Gary Peterson <garyp@us.ibm.com> @@ -35,8 +35,8 @@ ///----------------------------------------------------------------------------- /// /// @verbatim -/// Handle Nv Power Management -// +/// Handles HW446279 +/// /// @endverbatim ///---------------------------------------------------------------------------- @@ -44,26 +44,233 @@ // Includes //----------------------------------------------------------------------------- #include "pk.h" +#include "io_lib.h" +#include "p9_a_common.h" #define INITIAL_TIMEBASE 0 #define HANG_PULSE_FREQ_HZ 31250000 // ioo -#define KERNEL_STACK_SIZE 512 +#define KERNEL_STACK_SIZE 512 uint8_t G_kernel_stack[KERNEL_STACK_SIZE]; +enum Bank +{ + BankA = 0x00, + BankB = 0x01 +}; + +void wait_ns(uint32_t i_ns); +void powerDownBank(t_gcr_addr* gcr_addr, uint32_t iBankPowerDown); +void disableBank(t_gcr_addr* gcr_addr, uint32_t iBankPowerDown); // The main function is called by the boot code -int main( int argc, char** argv ) +int main(int argc, char** argv) { - /* - // initializes kernel data (stack, threads, timebase, timers, etc.) pk_initialize( - (PkAddress)g_kernelStack, + (PkAddress)G_kernel_stack, KERNEL_STACK_SIZE, 0, // initial_timebase HANG_PULSE_FREQ_HZ); // timebase_frequency_hz - */ + + // Form gcr_addr structure + t_gcr_addr gcr_addr; + set_gcr_addr(&gcr_addr, 0, 0, 0); // RX lane 0 + + // Initialize Work Regs + localPut(WORK1_REG, 0x0000000000000000); + localPut(WORK2_REG, 0x1234567800000000); + + // Initialize GCR Address + set_gcr_addr_lane (&gcr_addr, 0x0 ); + set_gcr_addr_reg_id(&gcr_addr, rx_group); + + uint32_t currentRecalAbort = 0x0; + uint32_t count = 0x0; + uint32_t state = 0x0; + uint64_t work1Data = 0x0; + uint64_t work2Data = 0x0; + uint32_t workDoneCnt = 0x0; + + while(1) + { + // state 0x00 :: Idle, have not seen a recal abort (Or have not seen a recal abort in a while) + // state 0x01 :: Recal Abort is high for the first time. + // At this point if we see a second recal abort then we will enter the workaround + + // Poll for Issue + currentRecalAbort = get_ptr_field(&gcr_addr, rx_recal_abort_active); // DL + + // Enter here if we see the recal abort going high for the first time: + if ((currentRecalAbort == 1) && (state == 0x00)) + { + state = 0x01; + wait_ns(2000); // Wait for 2us + count = 0x0; + } + // If recal abort has been asserted twice within the time limit, enter the workaround: + else if ((currentRecalAbort == 1) && (state == 0x01)) + { + // Stop auto recal + put_ptr_field(&gcr_addr, rx_rc_enable_auto_recal, 0x0, read_modify_write); + + // Wait for servo ops to finish. + while(get_ptr_field(&gcr_addr, rx_servo_done) == 0x0); + + uint32_t bankPowerDown = BankA; + uint32_t loopCount = 0; + uint32_t bankARecalAbortCnt = 0; + uint32_t bankBRecalAbortCnt = 0; + bool badBankFound = false; + localPut(WORK2_REG, 0xDEADFFFF00000000); + + // Workaround Loop: + // - We will switch back and forth powering down lanes 0-10 or 13-23 until + // we see 2 recal aborts while having a specific bank powered down. + // - Once we see 2 recal aborts having a specific bank powered down, + // we know that the other lane has the 'bad' lane/lanes. + do + { + powerDownBank(&gcr_addr, bankPowerDown); + wait_ns(2000000); // Wait for 2ms + + for(count = 0; count < 10000; ++count) // Write(530.67ns), RMW(1101ns), Read(1132ns) + { + currentRecalAbort = get_ptr_field(&gcr_addr, rx_recal_abort_active); // DL + + if(currentRecalAbort) + { + if(bankPowerDown == BankA) + { + bankBRecalAbortCnt += 1; + } + else + { + bankARecalAbortCnt += 1; + } + } + + if((bankARecalAbortCnt > 1) || (bankBRecalAbortCnt > 1)) + { + badBankFound = true; + break; + } + } + + ++loopCount; + bankPowerDown = (bankPowerDown == BankA) ? BankB : BankA; + } + while(!badBankFound); + + // Power down the bank with the bad lane/lanes + powerDownBank(&gcr_addr, bankPowerDown); + + // Disable the bad bank so we don't run recal on those lanes + disableBank(&gcr_addr, bankPowerDown); + + // Enable auto recal + put_ptr_field(&gcr_addr, rx_rc_enable_auto_recal, 0x1, read_modify_write); + + if(workDoneCnt != 0xF) + { + workDoneCnt += 0x1; + } + + work1Data = (work1Data & 0x0FFFFFFF00000000) | (((uint64_t)workDoneCnt << 60) & 0xF000000000000000); + work1Data = (work1Data & 0xFFFF000000000000) | (((uint64_t)(mfspr(SPRN_DEC)) << 32) & 0x0000FFFF00000000); + work2Data = (((uint64_t)loopCount << 32) & 0xFFFFFFFF00000000); + localPut(WORK1_REG, work1Data); + localPut(WORK2_REG, work2Data); + + wait_ns(200000); // Wait for 200us + + currentRecalAbort = 0x0; + count = 0x0; + state = 0x0; + } + else if((count > 26500) && (state == 0x01) ) // 30ms + { + currentRecalAbort = 0x0; + state = 0x0; + count = 0x0; + + work1Data = (work1Data & 0xFFF0FFFF00000000) | (0x0001000000000000); + localPut(WORK1_REG, work1Data); + } + else if(state == 0x01) + { + ++count; + } + } return 0; } + + +/** + * @brief Wait for a certain amount of time. The user has to be aware that + * we can't use a value greater than the decrementer size. + * @param[in] i_ns Time to wait in ns + * @return void + **/ +void wait_ns(uint32_t i_ns) +{ + // Timebase clock is at 31.25Mhz + // 1/31.25Mhz = 32ns + const uint32_t stopValue = 0xFFFFFFFF - (i_ns / 32); + + // Clear all of ther decrementor interrupts + mtspr(SPRN_TSR, TSR_DIS); + + // Use external timebase clock + mtspr(SPRN_TCR, TCR_DS); + + // Write max value to the decrememntor so we don't underflow + mtspr(SPRN_DEC, 0xFFFFFFFF); + + // Stay in while loop until decrementer ticks are met + while(mfspr(SPRN_DEC) > stopValue); + + return; +} + +void powerDownBank(t_gcr_addr* gcr_addr, uint32_t iBankPowerDown) +{ + const uint32_t START_LANE = (iBankPowerDown == BankB) ? 0 : 13; + const uint32_t END_LANE = (iBankPowerDown == BankB) ? 11 : 24; + + // Power Down All Lanes + set_gcr_addr_lane(gcr_addr, 0x1F); + put_ptr_field(gcr_addr, rx_lane_ana_pdwn, 0x01, fast_write); + set_gcr_addr_lane(gcr_addr, 0x00); + + uint32_t lane = 0x0; + + // Power Up Specifc Lanes + for(lane = START_LANE; lane < END_LANE; ++lane) + { + set_gcr_addr_lane(gcr_addr, lane); + put_ptr(gcr_addr, rx_dac_cntl1_eo_pl_addr, rx_dac_cntl1_eo_pl_startbit, rx_dac_cntl1_eo_pl_endbit, 0x0000, fast_write); + } + + set_gcr_addr_lane(gcr_addr, 0); + return; +} + +void disableBank(t_gcr_addr* gcr_addr, uint32_t iBankPowerDown) +{ + const uint32_t START_LANE = (iBankPowerDown == BankA) ? 0 : 13; + const uint32_t END_LANE = (iBankPowerDown == BankA) ? 11 : 24; + + uint32_t lane = 0x0; + + // Disable certain lanes to ensure we don't run recal on these lanes + for(lane = START_LANE; lane < END_LANE; ++lane) + { + set_gcr_addr_lane(gcr_addr, lane); + put_ptr_field(gcr_addr, rx_lane_disabled, 0x01, fast_write); + } + + set_gcr_addr_lane(gcr_addr, 0); + return; +} diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_com_reg_const_pkg.h b/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_com_reg_const_pkg.h new file mode 100644 index 00000000..2cd74570 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_com_reg_const_pkg.h @@ -0,0 +1,3899 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_com_reg_const_pkg.h $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//- *!*************************************************************************** +//- *! FILENAME : ppe_reg_const_pkg.h +//- *! TITLE : PPE Register Constants Package Header +//- *! DESCRIPTION : Constants containing register info for use by PPE +//- *! +//- *! +//- *! OWNER NAME : John Rell III Email: jgrell@us.ibm.com +//- *! BACKUP NAME : Mike Spear Email: mspear@us.ibm.com +//- *! +//- *!*************************************************************************** +#define rx_bit_cntl1_e_pl_addr 0b001100000 +#define rx_bit_cntl2_e_pl_addr 0b001100001 +#define rx_bit_cntl2_eo_pl_addr 0b001001001 +#define rx_bit_cntl3_e_pl_addr 0b001100010 +#define rx_bit_cntl3_eo_pl_addr 0b001001010 +#define rx_bit_cntl4_eo_pl_addr 0b001001011 +#define rx_bit_cntl5_eo_pl_addr 0b001001100 +#define rx_bit_cntlx1_eo_pl_addr 0b001001000 +#define rx_bit_mode1_e_pl_addr 0b001011000 +#define rx_bit_mode1_eo_pl_addr 0b001000100 +#define rx_bit_mode2_e_pl_addr 0b001011001 +#define rx_bit_mode2_eo_pl_addr 0b001000101 +#define rx_bit_mode3_eo_pl_addr 0b001000110 +#define rx_bit_stat1_eo_pl_addr 0b001001101 +#define rx_bit_stat2_eo_pl_addr 0b001001110 +#define rx_bit_stat3_eo_pl_addr 0b001001111 +#define rx_ctl_cntl10_eo_pg_addr 0b100100100 +#define rx_ctl_cntl11_eo_pg_addr 0b100100101 +#define rx_ctl_cntl12_eo_pg_addr 0b100100110 +#define rx_ctl_cntl13_eo_pg_addr 0b100100111 +#define rx_ctl_cntl14_eo_pg_addr 0b100101000 +#define rx_ctl_cntl15_eo_pg_addr 0b100101001 +#define rx_ctl_cntl1_e_pg_addr 0b100111110 +#define rx_ctl_cntl1_eo_pg_addr 0b100011011 +#define rx_ctl_cntl2_eo_pg_addr 0b100011100 +#define rx_ctl_cntl3_eo_pg_addr 0b100011101 +#define rx_ctl_cntl4_e_pg_addr 0b100111111 +#define rx_ctl_cntl4_eo_pg_addr 0b100011110 +#define rx_ctl_cntl5_eo_pg_addr 0b100011111 +#define rx_ctl_cntl6_eo_pg_addr 0b100100000 +#define rx_ctl_cntl8_eo_pg_addr 0b100100010 +#define rx_ctl_cntl9_eo_pg_addr 0b100100011 +#define rx_ctl_cntlx11_e_pg_addr 0b101000110 +#define rx_ctl_cntlx7_eo_pg_addr 0b100100001 +#define rx_ctl_mode10_e_pg_addr 0b100111011 +#define rx_ctl_mode10_eo_pg_addr 0b100001011 +#define rx_ctl_mode11_e_pg_addr 0b100111100 +#define rx_ctl_mode11_eo_pg_addr 0b100001100 +#define rx_ctl_mode12_e_pg_addr 0b100111101 +#define rx_ctl_mode12_eo_pg_addr 0b100001101 +#define rx_ctl_mode13_eo_pg_addr 0b100001110 +#define rx_ctl_mode14_eo_pg_addr 0b100001111 +#define rx_ctl_mode15_eo_pg_addr 0b100010000 +#define rx_ctl_mode16_eo_pg_addr 0b100010001 +#define rx_ctl_mode17_eo_pg_addr 0b100010010 +#define rx_ctl_mode18_eo_pg_addr 0b100010011 +#define rx_ctl_mode19_eo_pg_addr 0b100010100 +#define rx_ctl_mode1_e_pg_addr 0b100110010 +#define rx_ctl_mode1_eo_pg_addr 0b100000010 +#define rx_ctl_mode20_eo_pg_addr 0b100010101 +#define rx_ctl_mode21_eo_pg_addr 0b100010110 +#define rx_ctl_mode22_eo_pg_addr 0b100010111 +#define rx_ctl_mode23_eo_pg_addr 0b100011000 +#define rx_ctl_mode24_eo_pg_addr 0b100011001 +#define rx_ctl_mode26_eo_pg_addr 0b100101101 +#define rx_ctl_mode27_eo_pg_addr 0b100101110 +#define rx_ctl_mode28_eo_pg_addr 0b100101111 +#define rx_ctl_mode29_eo_pg_addr 0b100011010 +#define rx_ctl_mode2_e_pg_addr 0b100110011 +#define rx_ctl_mode2_eo_pg_addr 0b100000011 +#define rx_ctl_mode3_e_pg_addr 0b100110100 +#define rx_ctl_mode3_eo_pg_addr 0b100000100 +#define rx_ctl_mode4_e_pg_addr 0b100110101 +#define rx_ctl_mode4_eo_pg_addr 0b100000101 +#define rx_ctl_mode5_e_pg_addr 0b100110110 +#define rx_ctl_mode5_eo_pg_addr 0b100000110 +#define rx_ctl_mode6_e_pg_addr 0b100110111 +#define rx_ctl_mode6_eo_pg_addr 0b100000111 +#define rx_ctl_mode7_e_pg_addr 0b100111000 +#define rx_ctl_mode7_eo_pg_addr 0b100001000 +#define rx_ctl_mode8_e_pg_addr 0b100111001 +#define rx_ctl_mode8_eo_pg_addr 0b100001001 +#define rx_ctl_mode9_e_pg_addr 0b100111010 +#define rx_ctl_mode9_eo_pg_addr 0b100001010 +#define rx_ctl_stat1_e_pg_addr 0b101000111 +#define rx_ctl_stat1_eo_pg_addr 0b100101010 +#define rx_ctl_stat2_e_pg_addr 0b101001000 +#define rx_ctl_stat2_eo_pg_addr 0b100101011 +#define rx_ctl_stat3_eo_pg_addr 0b100101100 +#define rx_ctl_stat4_e_pg_addr 0b101001010 +#define rx_ctl_stat5_e_pg_addr 0b101001011 +#define rx_ctl_stat6_e_pg_addr 0b101001100 +#define rx_ctl_statx8_e_pg_addr 0b101001101 +#define rx_dac_cntl1_e_pl_addr 0b000010000 +#define rx_dac_cntl1_eo_pl_addr 0b000000001 +#define rx_dac_cntl2_e_pl_addr 0b000010001 +#define rx_dac_cntl2_eo_pl_addr 0b000000010 +#define rx_dac_cntl3_e_pl_addr 0b000010010 +#define rx_dac_cntl3_eo_pl_addr 0b000000011 +#define rx_dac_cntl4_e_pl_addr 0b000010011 +#define rx_dac_cntl4_eo_pl_addr 0b000000100 +#define rx_dac_cntl5_e_pl_addr 0b000010100 +#define rx_dac_cntl5_eo_pl_addr 0b000000101 +#define rx_dac_cntl6_e_pl_addr 0b000010101 +#define rx_dac_cntl6_eo_pl_addr 0b000000110 +#define rx_dac_cntl7_e_pl_addr 0b000010110 +#define rx_dac_cntl7_eo_pl_addr 0b000000111 +#define rx_dac_cntl8_e_pl_addr 0b000010111 +#define rx_dac_cntl8_eo_pl_addr 0b000001000 +#define rx_dac_cntl9_e_pl_addr 0b000011000 +#define rx_data_dac_spare_mode_pl_addr 0b000000000 +#define rx_data_work_spare_mode_pl_addr 0b001110000 +#define rx_datasm_cntl1_e_pg_addr 0b101111101 +#define rx_datasm_cntl2_eo_pg_addr 0b101101111 +#define rx_datasm_cntlx1_eo_pg_addr 0b101110001 +#define rx_datasm_spare_mode_pg_addr 0b101110000 +#define rx_datasm_stat10_eo_pg_addr 0b101111011 +#define rx_datasm_stat11_eo_pg_addr 0b101111100 +#define rx_datasm_stat12_eo_pg_addr 0b101111110 +#define rx_datasm_stat13_e_pg_addr 0b101111111 +#define rx_datasm_stat1_eo_pg_addr 0b101110010 +#define rx_datasm_stat2_eo_pg_addr 0b101110011 +#define rx_datasm_stat3_eo_pg_addr 0b101110100 +#define rx_datasm_stat4_eo_pg_addr 0b101110101 +#define rx_datasm_stat5_eo_pg_addr 0b101110110 +#define rx_datasm_stat6_eo_pg_addr 0b101110111 +#define rx_datasm_stat7_eo_pg_addr 0b101111000 +#define rx_datasm_stat8_eo_pg_addr 0b101111001 +#define rx_datasm_stat9_eo_pg_addr 0b101111010 +#define rx_fir1_error_inject_pg_addr 0b101010011 +#define rx_fir1_mask_pg_addr 0b101010010 +#define rx_fir1_pg_addr 0b101010001 +#define rx_fir2_error_inject_pg_addr 0b101100010 +#define rx_fir2_mask_pg_addr 0b101100001 +#define rx_fir2_pg_addr 0b101100000 +#define rx_fir_error_inject_pb_addr 0b111110011 +#define rx_fir_error_inject_pl_addr 0b001000011 +#define rx_fir_mask_pb_addr 0b111110010 +#define rx_fir_mask_pl_addr 0b001000010 +#define rx_fir_msg_pb_addr 0b111111111 +#define rx_fir_pb_addr 0b111110001 +#define rx_fir_pl_addr 0b001000001 +#define rx_fir_reset_pb_addr 0b111110000 +#define rx_fir_training_mask_pg_addr 0b101010101 +#define rx_fir_training_pg_addr 0b101010100 +#define rx_glbsm_cntl2_eo_pg_addr 0b101011100 +#define rx_glbsm_cntl3_eo_pg_addr 0b101011101 +#define rx_glbsm_cntl4_eo_pg_addr 0b101011110 +#define rx_glbsm_cntlx1_eo_pg_addr 0b101010110 +#define rx_glbsm_mode1_eo_pg_addr 0b101011111 +#define rx_glbsm_spare_mode_pg_addr 0b101010000 +#define rx_glbsm_stat10_e_pg_addr 0b101101100 +#define rx_glbsm_stat11_e_pg_addr 0b101101101 +#define rx_glbsm_stat1_e_pg_addr 0b101100011 +#define rx_glbsm_stat1_eo_pg_addr 0b101010111 +#define rx_glbsm_stat2_e_pg_addr 0b101100100 +#define rx_glbsm_stat2_eo_pg_addr 0b101011000 +#define rx_glbsm_stat3_e_pg_addr 0b101100101 +#define rx_glbsm_stat3_eo_pg_addr 0b101011001 +#define rx_glbsm_stat4_e_pg_addr 0b101100110 +#define rx_glbsm_stat4_eo_pg_addr 0b101011010 +#define rx_glbsm_stat5_eo_pg_addr 0b101011011 +#define rx_glbsm_stat7_e_pg_addr 0b101101001 +#define rx_glbsm_stat8_e_pg_addr 0b101101010 +#define rx_glbsm_stat9_e_pg_addr 0b101101011 +#define rx_id1_pg_addr 0b100000001 +#define rx_id2_pg_addr 0b100110000 +#define rx_intr_msg_pb_addr 0b111111110 +#define rx_spare_mode_pg_addr 0b100000000 +#define rx_spare_mode_pl_addr 0b001000000 +#define rx_work_stat1_eo_pl_addr 0b001110001 +#define rx_work_stat2_eo_pl_addr 0b001110010 +#define rx_work_stat3_eo_pl_addr 0b001110011 +#define scom_mode_pb_addr 0b000100000 +#define scom_ppe_cntl_addr 0b000100000 +#define scom_ppe_flags_clr_reg_addr 0b000100101 +#define scom_ppe_flags_reg_addr 0b000100011 +#define scom_ppe_flags_set_reg_addr 0b000100100 +#define scom_ppe_ir_edr_addr 0b000010100 +#define scom_ppe_ir_sprg0_addr 0b000010010 +#define scom_ppe_mem_arb_csar_addr 0b000001101 +#define scom_ppe_mem_arb_csdr_addr 0b000001110 +#define scom_ppe_mem_arb_scr_addr 0b000001010 +#define scom_ppe_work_reg1_addr 0b000100001 +#define scom_ppe_work_reg2_addr 0b000100010 +#define scom_ppe_xcr_none_addr 0b000010000 +#define scom_ppe_xcr_sprg0_addr 0b000010001 +#define scom_ppe_xsr_iar_addr 0b000010101 +#define scom_ppe_xsr_sprg0_addr 0b000010011 +#define spare_mode_pb_addr 0b111100110 +#define tx_bit_mode1_e_pl_addr 0b010000111 +#define tx_bit_mode2_e_pl_addr 0b010001000 +#define tx_cntl1g_pl_addr 0b010000010 +#define tx_cntl3_eo_pl_addr 0b010001010 +#define tx_ctl_cntl10_eo_pg_addr 0b110011011 +#define tx_ctl_cntl2_e_pg_addr 0b110010011 +#define tx_ctl_cntl2_eo_pg_addr 0b110000101 +#define tx_ctl_cntl3_eo_pg_addr 0b110000110 +#define tx_ctl_cntl8_eo_pg_addr 0b110011001 +#define tx_ctl_cntl9_eo_pg_addr 0b110011010 +#define tx_ctl_cntlg1_eo_pg_addr 0b110000100 +#define tx_ctl_cntlg3_e_pg_addr 0b110010100 +#define tx_ctl_cntlg4_e_pg_addr 0b110010101 +#define tx_ctl_cntlg5_e_pg_addr 0b110010110 +#define tx_ctl_cntlg6_e_pg_addr 0b110010111 +#define tx_ctl_cntlg7_e_pg_addr 0b110011000 +#define tx_ctl_mode1_e_pg_addr 0b110010001 +#define tx_ctl_mode1_eo_pg_addr 0b110000010 +#define tx_ctl_mode2_e_pg_addr 0b110011101 +#define tx_ctl_mode2_eo_pg_addr 0b110000011 +#define tx_ctl_mode3_e_pg_addr 0b110011110 +#define tx_ctl_statg1_e_pg_addr 0b110011100 +#define tx_ctlsm_cntl1_eo_pg_addr 0b110100110 +#define tx_ctlsm_cntl2_eo_pg_addr 0b110100111 +#define tx_ctlsm_cntl3_eo_pg_addr 0b110101000 +#define tx_ctlsm_cntl4_eo_pg_addr 0b110101001 +#define tx_ctlsm_cntl5_eo_pg_addr 0b110101010 +#define tx_ctlsm_cntl6_eo_pg_addr 0b110101011 +#define tx_ctlsm_cntl7_eo_pg_addr 0b110101100 +#define tx_ctlsm_cntlg1_e_pg_addr 0b110110000 +#define tx_ctlsm_mode1_eo_pg_addr 0b110100101 +#define tx_ctlsm_spare_mode_pg_addr 0b110100100 +#define tx_ctlsm_stat1_e_pg_addr 0b110110001 +#define tx_ctlsm_stat1_eo_pg_addr 0b110101101 +#define tx_fir_error_inject_pg_addr 0b110100011 +#define tx_fir_error_inject_pl_addr 0b010000110 +#define tx_fir_mask_pg_addr 0b110100001 +#define tx_fir_mask_pl_addr 0b010000101 +#define tx_fir_pg_addr 0b110100000 +#define tx_fir_pl_addr 0b010000100 +#define tx_fir_reset_pg_addr 0b110100010 +#define tx_id1_pg_addr 0b110000001 +#define tx_id2_pg_addr 0b110010000 +#define tx_impcal2_pb_addr 0b111100111 +#define tx_impcal_nval_pb_addr 0b111100001 +#define tx_impcal_p_4x_pb_addr 0b111100011 +#define tx_impcal_pb_addr 0b111100000 +#define tx_impcal_pval_pb_addr 0b111100010 +#define tx_impcal_swo1_pb_addr 0b111100100 +#define tx_impcal_swo2_pb_addr 0b111100101 +#define tx_mode1_pl_addr 0b010000000 +#define tx_mode2_pl_addr 0b010000001 +#define tx_spare_mode_pg_addr 0b110000000 +#define tx_stat1_pl_addr 0b010000011 + + +#define chan_fail_mask_addr 0b000100000 +#define chan_fail_mask_startbit 15 +#define chan_fail_mask_width 8 +#define chan_fail_mask_endbit 22 +#define chan_fail_mask_shift -7 +#define chan_fail_mask_mask 0xfe00000000000000 + + +#define enable_gcr_ofl_buff_addr 0b000100000 +#define enable_gcr_ofl_buff_startbit 1 +#define enable_gcr_ofl_buff_width 1 +#define enable_gcr_ofl_buff_endbit 1 +#define enable_gcr_ofl_buff_shift 14 +#define enable_gcr_ofl_buff_mask 0x4000 + + +#define gcr_buffer_enabled_addr 0b000100000 +#define gcr_buffer_enabled_startbit 11 +#define gcr_buffer_enabled_width 1 +#define gcr_buffer_enabled_endbit 11 +#define gcr_buffer_enabled_shift 4 +#define gcr_buffer_enabled_mask 0x10 + + +#define gcr_hang_det_sel_addr 0b000100000 +#define gcr_hang_det_sel_startbit 8 +#define gcr_hang_det_sel_width 3 +#define gcr_hang_det_sel_endbit 10 +#define gcr_hang_det_sel_shift 5 +#define gcr_hang_det_sel_mask 0xe0 + + +#define gcr_hang_error_inj_addr 0b000100000 +#define gcr_hang_error_inj_startbit 13 +#define gcr_hang_error_inj_width 1 +#define gcr_hang_error_inj_endbit 13 +#define gcr_hang_error_inj_shift 2 +#define gcr_hang_error_inj_mask 0x4 + + +#define gcr_hang_error_mask_addr 0b000100000 +#define gcr_hang_error_mask_startbit 12 +#define gcr_hang_error_mask_width 1 +#define gcr_hang_error_mask_endbit 12 +#define gcr_hang_error_mask_shift 3 +#define gcr_hang_error_mask_mask 0x8 + + +#define gcr_test_mode_addr 0b000100000 +#define gcr_test_mode_startbit 0 +#define gcr_test_mode_width 1 +#define gcr_test_mode_endbit 0 +#define gcr_test_mode_shift 15 +#define gcr_test_mode_mask 0x8000 + + +#define ioreset_hard_bus0_addr 0b000100000 +#define ioreset_hard_bus0_startbit 2 +#define ioreset_hard_bus0_width 1 +#define ioreset_hard_bus0_endbit 2 +#define ioreset_hard_bus0_shift 13 +#define ioreset_hard_bus0_mask 0x2000 + + +#define mmio_pg_reg_access_addr 0b000100000 +#define mmio_pg_reg_access_startbit 3 +#define mmio_pg_reg_access_width 1 +#define mmio_pg_reg_access_endbit 3 +#define mmio_pg_reg_access_shift 12 +#define mmio_pg_reg_access_mask 0x1000 + + +#define pb_spare_mode_0_addr 0b111100110 +#define pb_spare_mode_0_startbit 0 +#define pb_spare_mode_0_width 1 +#define pb_spare_mode_0_endbit 0 +#define pb_spare_mode_0_shift 15 +#define pb_spare_mode_0_mask 0x8000 + + +#define pb_spare_mode_1_addr 0b111100110 +#define pb_spare_mode_1_startbit 1 +#define pb_spare_mode_1_width 1 +#define pb_spare_mode_1_endbit 1 +#define pb_spare_mode_1_shift 14 +#define pb_spare_mode_1_mask 0x4000 + + +#define pb_spare_mode_2_addr 0b111100110 +#define pb_spare_mode_2_startbit 2 +#define pb_spare_mode_2_width 1 +#define pb_spare_mode_2_endbit 2 +#define pb_spare_mode_2_shift 13 +#define pb_spare_mode_2_mask 0x2000 + + +#define pb_spare_mode_3_addr 0b111100110 +#define pb_spare_mode_3_startbit 3 +#define pb_spare_mode_3_width 1 +#define pb_spare_mode_3_endbit 3 +#define pb_spare_mode_3_shift 12 +#define pb_spare_mode_3_mask 0x1000 + + +#define pb_spare_mode_4_addr 0b111100110 +#define pb_spare_mode_4_startbit 4 +#define pb_spare_mode_4_width 1 +#define pb_spare_mode_4_endbit 4 +#define pb_spare_mode_4_shift 11 +#define pb_spare_mode_4_mask 0x800 + + +#define pb_spare_mode_5_addr 0b111100110 +#define pb_spare_mode_5_startbit 5 +#define pb_spare_mode_5_width 1 +#define pb_spare_mode_5_endbit 5 +#define pb_spare_mode_5_shift 10 +#define pb_spare_mode_5_mask 0x400 + + +#define pb_spare_mode_6_addr 0b111100110 +#define pb_spare_mode_6_startbit 6 +#define pb_spare_mode_6_width 1 +#define pb_spare_mode_6_endbit 6 +#define pb_spare_mode_6_shift 9 +#define pb_spare_mode_6_mask 0x200 + + +#define pb_spare_mode_7_addr 0b111100110 +#define pb_spare_mode_7_startbit 7 +#define pb_spare_mode_7_width 1 +#define pb_spare_mode_7_endbit 7 +#define pb_spare_mode_7_shift 8 +#define pb_spare_mode_7_mask 0x100 + + +#define ppe_gcr_mode_addr 0b000100000 +#define ppe_gcr_mode_startbit 14 +#define ppe_gcr_mode_width 1 +#define ppe_gcr_mode_endbit 14 +#define ppe_gcr_mode_shift 1 +#define ppe_gcr_mode_mask 0x2 + + +#define rx_a_ap_addr 0b001110010 +#define rx_a_ap_startbit 4 +#define rx_a_ap_width 8 +#define rx_a_ap_endbit 11 +#define rx_a_ap_shift 4 +#define rx_a_ap_mask 0xff0 + + +#define rx_a_bad_dfe_conv_addr 0b001110010 +#define rx_a_bad_dfe_conv_startbit 0 +#define rx_a_bad_dfe_conv_width 1 +#define rx_a_bad_dfe_conv_endbit 0 +#define rx_a_bad_dfe_conv_shift 15 +#define rx_a_bad_dfe_conv_mask 0x8000 + + +#define rx_a_bist_en_addr 0b100000010 +#define rx_a_bist_en_startbit 9 +#define rx_a_bist_en_width 1 +#define rx_a_bist_en_endbit 9 +#define rx_a_bist_en_shift 6 +#define rx_a_bist_en_mask 0x40 + + +#define rx_a_controls_addr 0b000000010 +#define rx_a_controls_startbit 0 +#define rx_a_controls_width 6 +#define rx_a_controls_endbit 5 +#define rx_a_controls_shift 10 +#define rx_a_controls_mask 0xfc00 + + +#define rx_a_ctle_gain_addr 0b000000110 +#define rx_a_ctle_gain_startbit 5 +#define rx_a_ctle_gain_width 4 +#define rx_a_ctle_gain_endbit 8 +#define rx_a_ctle_gain_shift 7 +#define rx_a_ctle_gain_mask 0x780 + + +#define rx_a_even_integ_fine_gain_addr 0b000000101 +#define rx_a_even_integ_fine_gain_startbit 4 +#define rx_a_even_integ_fine_gain_width 5 +#define rx_a_even_integ_fine_gain_endbit 8 +#define rx_a_even_integ_fine_gain_shift 7 +#define rx_a_even_integ_fine_gain_mask 0xf80 + + +#define rx_a_h1ap_at_limit_addr 0b001110010 +#define rx_a_h1ap_at_limit_startbit 2 +#define rx_a_h1ap_at_limit_width 1 +#define rx_a_h1ap_at_limit_endbit 2 +#define rx_a_h1ap_at_limit_shift 13 +#define rx_a_h1ap_at_limit_mask 0x2000 + + +#define rx_a_h1e_val_addr 0b000000111 +#define rx_a_h1e_val_startbit 0 +#define rx_a_h1e_val_width 7 +#define rx_a_h1e_val_endbit 6 +#define rx_a_h1e_val_shift 9 +#define rx_a_h1e_val_mask 0xfe00 + + +#define rx_a_h1o_val_addr 0b000000111 +#define rx_a_h1o_val_startbit 8 +#define rx_a_h1o_val_width 7 +#define rx_a_h1o_val_endbit 14 +#define rx_a_h1o_val_shift 1 +#define rx_a_h1o_val_mask 0xfe + + +#define rx_a_integ_coarse_gain_addr 0b000000101 +#define rx_a_integ_coarse_gain_startbit 0 +#define rx_a_integ_coarse_gain_width 4 +#define rx_a_integ_coarse_gain_endbit 3 +#define rx_a_integ_coarse_gain_shift 12 +#define rx_a_integ_coarse_gain_mask 0xf000 + + +#define rx_a_odd_integ_fine_gain_addr 0b000000101 +#define rx_a_odd_integ_fine_gain_startbit 9 +#define rx_a_odd_integ_fine_gain_width 5 +#define rx_a_odd_integ_fine_gain_endbit 13 +#define rx_a_odd_integ_fine_gain_shift 2 +#define rx_a_odd_integ_fine_gain_mask 0x7c + + +#define rx_a_offset_e0_addr 0b000000011 +#define rx_a_offset_e0_startbit 0 +#define rx_a_offset_e0_width 7 +#define rx_a_offset_e0_endbit 6 +#define rx_a_offset_e0_shift 9 +#define rx_a_offset_e0_mask 0xfe00 + + +#define rx_a_offset_e1_addr 0b000000011 +#define rx_a_offset_e1_startbit 8 +#define rx_a_offset_e1_width 7 +#define rx_a_offset_e1_endbit 14 +#define rx_a_offset_e1_shift 1 +#define rx_a_offset_e1_mask 0xfe + + +#define rx_a_offset_o0_addr 0b000000100 +#define rx_a_offset_o0_startbit 0 +#define rx_a_offset_o0_width 7 +#define rx_a_offset_o0_endbit 6 +#define rx_a_offset_o0_shift 9 +#define rx_a_offset_o0_mask 0xfe00 + + +#define rx_a_offset_o1_addr 0b000000100 +#define rx_a_offset_o1_startbit 8 +#define rx_a_offset_o1_width 7 +#define rx_a_offset_o1_endbit 14 +#define rx_a_offset_o1_shift 1 +#define rx_a_offset_o1_mask 0xfe + + +#define rx_a_path_off_even_addr 0b001110011 +#define rx_a_path_off_even_startbit 0 +#define rx_a_path_off_even_width 6 +#define rx_a_path_off_even_endbit 5 +#define rx_a_path_off_even_shift 10 +#define rx_a_path_off_even_mask 0xfc00 + + +#define rx_a_path_off_odd_addr 0b001110011 +#define rx_a_path_off_odd_startbit 6 +#define rx_a_path_off_odd_width 6 +#define rx_a_path_off_odd_endbit 11 +#define rx_a_path_off_odd_shift 4 +#define rx_a_path_off_odd_mask 0x3f0 + + +#define rx_a_pr_dfe_clkadj_addr 0b001001111 +#define rx_a_pr_dfe_clkadj_startbit 12 +#define rx_a_pr_dfe_clkadj_width 4 +#define rx_a_pr_dfe_clkadj_endbit 15 +#define rx_a_pr_dfe_clkadj_shift 0 +#define rx_a_pr_dfe_clkadj_mask 0xf + + +#define rx_abort_check_timeout_sel_addr 0b100001000 +#define rx_abort_check_timeout_sel_startbit 0 +#define rx_abort_check_timeout_sel_width 4 +#define rx_abort_check_timeout_sel_endbit 3 +#define rx_abort_check_timeout_sel_shift 12 +#define rx_abort_check_timeout_sel_mask 0xf000 + + +#define rx_amax_high_addr 0b100010010 +#define rx_amax_high_startbit 0 +#define rx_amax_high_width 8 +#define rx_amax_high_endbit 7 +#define rx_amax_high_shift 8 +#define rx_amax_high_mask 0xff00 + + +#define rx_amax_low_addr 0b100010010 +#define rx_amax_low_startbit 8 +#define rx_amax_low_width 8 +#define rx_amax_low_endbit 15 +#define rx_amax_low_shift 0 +#define rx_amax_low_mask 0xff + + +#define rx_amin_cfg_addr 0b100001100 +#define rx_amin_cfg_startbit 9 +#define rx_amin_cfg_width 3 +#define rx_amin_cfg_endbit 11 +#define rx_amin_cfg_shift 4 +#define rx_amin_cfg_mask 0x70 + + +#define rx_amin_timeout_addr 0b100010000 +#define rx_amin_timeout_startbit 12 +#define rx_amin_timeout_width 4 +#define rx_amin_timeout_endbit 15 +#define rx_amin_timeout_shift 0 +#define rx_amin_timeout_mask 0xf + + +#define rx_amp0_filter_mask_addr 0b100010011 +#define rx_amp0_filter_mask_startbit 0 +#define rx_amp0_filter_mask_width 8 +#define rx_amp0_filter_mask_endbit 7 +#define rx_amp0_filter_mask_shift 8 +#define rx_amp0_filter_mask_mask 0xff00 + + +#define rx_amp1_filter_mask_addr 0b100010011 +#define rx_amp1_filter_mask_startbit 8 +#define rx_amp1_filter_mask_width 8 +#define rx_amp1_filter_mask_endbit 15 +#define rx_amp1_filter_mask_shift 0 +#define rx_amp1_filter_mask_mask 0xff + + +#define rx_amp_cfg_addr 0b100001011 +#define rx_amp_cfg_startbit 12 +#define rx_amp_cfg_width 4 +#define rx_amp_cfg_endbit 15 +#define rx_amp_cfg_shift 0 +#define rx_amp_cfg_mask 0xf + + +#define rx_amp_gain_cnt_max_addr 0b100000111 +#define rx_amp_gain_cnt_max_startbit 8 +#define rx_amp_gain_cnt_max_width 4 +#define rx_amp_gain_cnt_max_endbit 11 +#define rx_amp_gain_cnt_max_shift 4 +#define rx_amp_gain_cnt_max_mask 0xf0 + + +#define rx_amp_init_cfg_addr 0b100001011 +#define rx_amp_init_cfg_startbit 0 +#define rx_amp_init_cfg_width 3 +#define rx_amp_init_cfg_endbit 2 +#define rx_amp_init_cfg_shift 13 +#define rx_amp_init_cfg_mask 0xe000 + + +#define rx_amp_init_timeout_addr 0b100001111 +#define rx_amp_init_timeout_startbit 0 +#define rx_amp_init_timeout_width 4 +#define rx_amp_init_timeout_endbit 3 +#define rx_amp_init_timeout_shift 12 +#define rx_amp_init_timeout_mask 0xf000 + + +#define rx_amp_recal_cfg_addr 0b100001011 +#define rx_amp_recal_cfg_startbit 3 +#define rx_amp_recal_cfg_width 3 +#define rx_amp_recal_cfg_endbit 5 +#define rx_amp_recal_cfg_shift 10 +#define rx_amp_recal_cfg_mask 0x1c00 + + +#define rx_amp_recal_timeout_addr 0b100001111 +#define rx_amp_recal_timeout_startbit 4 +#define rx_amp_recal_timeout_width 4 +#define rx_amp_recal_timeout_endbit 7 +#define rx_amp_recal_timeout_shift 8 +#define rx_amp_recal_timeout_mask 0xf00 + + +#define rx_amp_start_val_addr 0b100010100 +#define rx_amp_start_val_startbit 8 +#define rx_amp_start_val_width 8 +#define rx_amp_start_val_endbit 15 +#define rx_amp_start_val_shift 0 +#define rx_amp_start_val_mask 0xff + + +#define rx_amp_timeout_addr 0b100010001 +#define rx_amp_timeout_startbit 0 +#define rx_amp_timeout_width 4 +#define rx_amp_timeout_endbit 3 +#define rx_amp_timeout_shift 12 +#define rx_amp_timeout_mask 0xf000 + + +#define rx_amp_val_addr 0b000001000 +#define rx_amp_val_startbit 0 +#define rx_amp_val_width 8 +#define rx_amp_val_endbit 7 +#define rx_amp_val_shift 8 +#define rx_amp_val_mask 0xff00 + + +#define rx_ap110_ap010_delta_max_addr 0b100010101 +#define rx_ap110_ap010_delta_max_startbit 4 +#define rx_ap110_ap010_delta_max_width 4 +#define rx_ap110_ap010_delta_max_endbit 7 +#define rx_ap110_ap010_delta_max_shift 8 +#define rx_ap110_ap010_delta_max_mask 0xf00 + + +#define rx_apx111_high_addr 0b100011010 +#define rx_apx111_high_startbit 0 +#define rx_apx111_high_width 8 +#define rx_apx111_high_endbit 7 +#define rx_apx111_high_shift 8 +#define rx_apx111_high_mask 0xff00 + + +#define rx_apx111_low_addr 0b100011010 +#define rx_apx111_low_startbit 8 +#define rx_apx111_low_width 8 +#define rx_apx111_low_endbit 15 +#define rx_apx111_low_shift 0 +#define rx_apx111_low_mask 0xff + + +#define rx_ber_cfg_addr 0b001000110 +#define rx_ber_cfg_startbit 0 +#define rx_ber_cfg_width 3 +#define rx_ber_cfg_endbit 2 +#define rx_ber_cfg_shift 13 +#define rx_ber_cfg_mask 0xe000 + + +#define rx_ber_clr_count_on_read_en_addr 0b100011011 +#define rx_ber_clr_count_on_read_en_startbit 11 +#define rx_ber_clr_count_on_read_en_width 1 +#define rx_ber_clr_count_on_read_en_endbit 11 +#define rx_ber_clr_count_on_read_en_shift 4 +#define rx_ber_clr_count_on_read_en_mask 0x10 + + +#define rx_ber_clr_timer_on_read_en_addr 0b100011011 +#define rx_ber_clr_timer_on_read_en_startbit 12 +#define rx_ber_clr_timer_on_read_en_width 1 +#define rx_ber_clr_timer_on_read_en_endbit 12 +#define rx_ber_clr_timer_on_read_en_shift 3 +#define rx_ber_clr_timer_on_read_en_mask 0x8 + + +#define rx_ber_count_addr 0b101110010 +#define rx_ber_count_startbit 0 +#define rx_ber_count_width 11 +#define rx_ber_count_endbit 10 +#define rx_ber_count_shift 5 +#define rx_ber_count_mask 0xffe0 + + +#define rx_ber_count_clr_addr 0b101110001 +#define rx_ber_count_clr_startbit 1 +#define rx_ber_count_clr_width 1 +#define rx_ber_count_clr_endbit 1 +#define rx_ber_count_clr_shift 14 +#define rx_ber_count_clr_mask 0x4000 + + +#define rx_ber_count_freeze_en_addr 0b100011011 +#define rx_ber_count_freeze_en_startbit 2 +#define rx_ber_count_freeze_en_width 1 +#define rx_ber_count_freeze_en_endbit 2 +#define rx_ber_count_freeze_en_shift 13 +#define rx_ber_count_freeze_en_mask 0x2000 + + +#define rx_ber_count_frozen_by_err_cnt_addr 0b101110010 +#define rx_ber_count_frozen_by_err_cnt_startbit 12 +#define rx_ber_count_frozen_by_err_cnt_width 1 +#define rx_ber_count_frozen_by_err_cnt_endbit 12 +#define rx_ber_count_frozen_by_err_cnt_shift 3 +#define rx_ber_count_frozen_by_err_cnt_mask 0x8 + + +#define rx_ber_count_frozen_by_timer_addr 0b101110010 +#define rx_ber_count_frozen_by_timer_startbit 13 +#define rx_ber_count_frozen_by_timer_width 1 +#define rx_ber_count_frozen_by_timer_endbit 13 +#define rx_ber_count_frozen_by_timer_shift 2 +#define rx_ber_count_frozen_by_timer_mask 0x4 + + +#define rx_ber_count_saturated_addr 0b101110010 +#define rx_ber_count_saturated_startbit 11 +#define rx_ber_count_saturated_width 1 +#define rx_ber_count_saturated_endbit 11 +#define rx_ber_count_saturated_shift 4 +#define rx_ber_count_saturated_mask 0x10 + + +#define rx_ber_count_sel_addr 0b100011011 +#define rx_ber_count_sel_startbit 3 +#define rx_ber_count_sel_width 4 +#define rx_ber_count_sel_endbit 6 +#define rx_ber_count_sel_shift 9 +#define rx_ber_count_sel_mask 0x1e00 + + +#define rx_ber_dpipe_mux_sel_addr 0b001000100 +#define rx_ber_dpipe_mux_sel_startbit 1 +#define rx_ber_dpipe_mux_sel_width 1 +#define rx_ber_dpipe_mux_sel_endbit 1 +#define rx_ber_dpipe_mux_sel_shift 14 +#define rx_ber_dpipe_mux_sel_mask 0x4000 + + +#define rx_ber_en_addr 0b100011011 +#define rx_ber_en_startbit 0 +#define rx_ber_en_width 1 +#define rx_ber_en_endbit 0 +#define rx_ber_en_shift 15 +#define rx_ber_en_mask 0x8000 + + +#define rx_ber_reset_addr 0b101110001 +#define rx_ber_reset_startbit 6 +#define rx_ber_reset_width 1 +#define rx_ber_reset_endbit 6 +#define rx_ber_reset_shift 9 +#define rx_ber_reset_mask 0x200 + + +#define rx_ber_timeout_addr 0b100010001 +#define rx_ber_timeout_startbit 8 +#define rx_ber_timeout_width 4 +#define rx_ber_timeout_endbit 11 +#define rx_ber_timeout_shift 4 +#define rx_ber_timeout_mask 0xf0 + + +#define rx_ber_timer_clr_addr 0b101110001 +#define rx_ber_timer_clr_startbit 2 +#define rx_ber_timer_clr_width 1 +#define rx_ber_timer_clr_endbit 2 +#define rx_ber_timer_clr_shift 13 +#define rx_ber_timer_clr_mask 0x2000 + + +#define rx_ber_timer_freeze_en_addr 0b100011011 +#define rx_ber_timer_freeze_en_startbit 1 +#define rx_ber_timer_freeze_en_width 1 +#define rx_ber_timer_freeze_en_endbit 1 +#define rx_ber_timer_freeze_en_shift 14 +#define rx_ber_timer_freeze_en_mask 0x4000 + + +#define rx_ber_timer_saturated_addr 0b101110010 +#define rx_ber_timer_saturated_startbit 14 +#define rx_ber_timer_saturated_width 1 +#define rx_ber_timer_saturated_endbit 14 +#define rx_ber_timer_saturated_shift 1 +#define rx_ber_timer_saturated_mask 0x2 + + +#define rx_ber_timer_sel_addr 0b100011011 +#define rx_ber_timer_sel_startbit 8 +#define rx_ber_timer_sel_width 3 +#define rx_ber_timer_sel_endbit 10 +#define rx_ber_timer_sel_shift 5 +#define rx_ber_timer_sel_mask 0xe0 + + +#define rx_ber_timer_value_0_15_addr 0b101110011 +#define rx_ber_timer_value_0_15_startbit 0 +#define rx_ber_timer_value_0_15_width 16 +#define rx_ber_timer_value_0_15_endbit 15 +#define rx_ber_timer_value_0_15_shift 0 +#define rx_ber_timer_value_0_15_mask 0xffff + + +#define rx_ber_timer_value_16_31_addr 0b101110100 +#define rx_ber_timer_value_16_31_startbit 0 +#define rx_ber_timer_value_16_31_width 16 +#define rx_ber_timer_value_16_31_endbit 15 +#define rx_ber_timer_value_16_31_shift 0 +#define rx_ber_timer_value_16_31_mask 0xffff + + +#define rx_bist_bus_data_mode_addr 0b100100100 +#define rx_bist_bus_data_mode_startbit 4 +#define rx_bist_bus_data_mode_width 1 +#define rx_bist_bus_data_mode_endbit 4 +#define rx_bist_bus_data_mode_shift 11 +#define rx_bist_bus_data_mode_mask 0x800 + + +#define rx_bist_cupll_lock_check_en_addr 0b100100011 +#define rx_bist_cupll_lock_check_en_startbit 5 +#define rx_bist_cupll_lock_check_en_width 1 +#define rx_bist_cupll_lock_check_en_endbit 5 +#define rx_bist_cupll_lock_check_en_shift 10 +#define rx_bist_cupll_lock_check_en_mask 0x400 + + +#define rx_bist_done_addr 0b100101011 +#define rx_bist_done_startbit 1 +#define rx_bist_done_width 1 +#define rx_bist_done_endbit 1 +#define rx_bist_done_shift 14 +#define rx_bist_done_mask 0x4000 + + +#define rx_bist_en_addr 0b100100011 +#define rx_bist_en_startbit 0 +#define rx_bist_en_width 1 +#define rx_bist_en_endbit 0 +#define rx_bist_en_shift 15 +#define rx_bist_en_mask 0x8000 + + +#define rx_bist_ext_start_mode_addr 0b100100011 +#define rx_bist_ext_start_mode_startbit 1 +#define rx_bist_ext_start_mode_width 1 +#define rx_bist_ext_start_mode_endbit 1 +#define rx_bist_ext_start_mode_shift 14 +#define rx_bist_ext_start_mode_mask 0x4000 + + +#define rx_bist_eye_a_width_addr 0b100101011 +#define rx_bist_eye_a_width_startbit 4 +#define rx_bist_eye_a_width_width 6 +#define rx_bist_eye_a_width_endbit 9 +#define rx_bist_eye_a_width_shift 6 +#define rx_bist_eye_a_width_mask 0xfc0 + + +#define rx_bist_eye_b_width_addr 0b100101011 +#define rx_bist_eye_b_width_startbit 10 +#define rx_bist_eye_b_width_width 6 +#define rx_bist_eye_b_width_endbit 15 +#define rx_bist_eye_b_width_shift 0 +#define rx_bist_eye_b_width_mask 0x3f + + +#define rx_bist_init_disable_addr 0b100100011 +#define rx_bist_init_disable_startbit 2 +#define rx_bist_init_disable_width 3 +#define rx_bist_init_disable_endbit 4 +#define rx_bist_init_disable_shift 11 +#define rx_bist_init_disable_mask 0x3800 + + +#define rx_bist_init_done_addr 0b100101011 +#define rx_bist_init_done_startbit 0 +#define rx_bist_init_done_width 1 +#define rx_bist_init_done_endbit 0 +#define rx_bist_init_done_shift 15 +#define rx_bist_init_done_mask 0x8000 + + +#define rx_bist_min_eye_width_addr 0b100000010 +#define rx_bist_min_eye_width_startbit 3 +#define rx_bist_min_eye_width_width 6 +#define rx_bist_min_eye_width_endbit 8 +#define rx_bist_min_eye_width_shift 7 +#define rx_bist_min_eye_width_mask 0x1f80 + + +#define rx_bist_no_edge_det_addr 0b100101011 +#define rx_bist_no_edge_det_startbit 3 +#define rx_bist_no_edge_det_width 1 +#define rx_bist_no_edge_det_endbit 3 +#define rx_bist_no_edge_det_shift 12 +#define rx_bist_no_edge_det_mask 0x1000 + + +#define rx_bist_prbs_prop_time_addr 0b100100100 +#define rx_bist_prbs_prop_time_startbit 5 +#define rx_bist_prbs_prop_time_width 4 +#define rx_bist_prbs_prop_time_endbit 8 +#define rx_bist_prbs_prop_time_shift 7 +#define rx_bist_prbs_prop_time_mask 0x780 + + +#define rx_bist_prbs_test_time_addr 0b100100100 +#define rx_bist_prbs_test_time_startbit 0 +#define rx_bist_prbs_test_time_width 4 +#define rx_bist_prbs_test_time_endbit 3 +#define rx_bist_prbs_test_time_shift 12 +#define rx_bist_prbs_test_time_mask 0xf000 + + +#define rx_bist_store_eyes_bank_sel_addr 0b100100011 +#define rx_bist_store_eyes_bank_sel_startbit 12 +#define rx_bist_store_eyes_bank_sel_width 2 +#define rx_bist_store_eyes_bank_sel_endbit 13 +#define rx_bist_store_eyes_bank_sel_shift 2 +#define rx_bist_store_eyes_bank_sel_mask 0xc + + +#define rx_bist_store_eyes_lane_sel_addr 0b100100011 +#define rx_bist_store_eyes_lane_sel_startbit 6 +#define rx_bist_store_eyes_lane_sel_width 6 +#define rx_bist_store_eyes_lane_sel_endbit 11 +#define rx_bist_store_eyes_lane_sel_shift 4 +#define rx_bist_store_eyes_lane_sel_mask 0x3f0 + + +#define rx_bus_id_addr 0b100000001 +#define rx_bus_id_startbit 0 +#define rx_bus_id_width 6 +#define rx_bus_id_endbit 5 +#define rx_bus_id_shift 10 +#define rx_bus_id_mask 0xfc00 + + +#define rx_cal_lane_pg_phy_gcrmsg_addr 0b100100001 +#define rx_cal_lane_pg_phy_gcrmsg_startbit 8 +#define rx_cal_lane_pg_phy_gcrmsg_width 5 +#define rx_cal_lane_pg_phy_gcrmsg_endbit 12 +#define rx_cal_lane_pg_phy_gcrmsg_shift 3 +#define rx_cal_lane_pg_phy_gcrmsg_mask 0xf8 + + +#define rx_cal_lane_sel_addr 0b001001000 +#define rx_cal_lane_sel_startbit 0 +#define rx_cal_lane_sel_width 1 +#define rx_cal_lane_sel_endbit 0 +#define rx_cal_lane_sel_shift 15 +#define rx_cal_lane_sel_mask 0x8000 + + +#define rx_clr_par_errs_addr 0b101010110 +#define rx_clr_par_errs_startbit 14 +#define rx_clr_par_errs_width 1 +#define rx_clr_par_errs_endbit 14 +#define rx_clr_par_errs_shift 1 +#define rx_clr_par_errs_mask 0x2 + + +#define rx_clr_recal_cnt_addr 0b101011110 +#define rx_clr_recal_cnt_startbit 0 +#define rx_clr_recal_cnt_width 1 +#define rx_clr_recal_cnt_endbit 0 +#define rx_clr_recal_cnt_shift 15 +#define rx_clr_recal_cnt_mask 0x8000 + + +#define rx_cm_cfg_addr 0b100001100 +#define rx_cm_cfg_startbit 6 +#define rx_cm_cfg_width 3 +#define rx_cm_cfg_endbit 8 +#define rx_cm_cfg_shift 7 +#define rx_cm_cfg_mask 0x380 + + +#define rx_cm_cntl_addr 0b000000010 +#define rx_cm_cntl_startbit 6 +#define rx_cm_cntl_width 3 +#define rx_cm_cntl_endbit 8 +#define rx_cm_cntl_shift 7 +#define rx_cm_cntl_mask 0x380 + + +#define rx_cm_offset_val_addr 0b100001110 +#define rx_cm_offset_val_startbit 1 +#define rx_cm_offset_val_width 7 +#define rx_cm_offset_val_endbit 7 +#define rx_cm_offset_val_shift 8 +#define rx_cm_offset_val_mask 0x7f00 + + +#define rx_cm_timeout_addr 0b100010000 +#define rx_cm_timeout_startbit 8 +#define rx_cm_timeout_width 4 +#define rx_cm_timeout_endbit 11 +#define rx_cm_timeout_shift 4 +#define rx_cm_timeout_mask 0xf0 + + +#define rx_cnt_single_lane_recal_addr 0b101011100 +#define rx_cnt_single_lane_recal_startbit 1 +#define rx_cnt_single_lane_recal_width 1 +#define rx_cnt_single_lane_recal_endbit 1 +#define rx_cnt_single_lane_recal_shift 14 +#define rx_cnt_single_lane_recal_mask 0x4000 + + +#define rx_ctl_datasm_clkdist_pdwn_addr 0b101110000 +#define rx_ctl_datasm_clkdist_pdwn_startbit 12 +#define rx_ctl_datasm_clkdist_pdwn_width 1 +#define rx_ctl_datasm_clkdist_pdwn_endbit 12 +#define rx_ctl_datasm_clkdist_pdwn_shift 3 +#define rx_ctl_datasm_clkdist_pdwn_mask 0x8 + + +#define rx_ctle_gain_max_addr 0b100010100 +#define rx_ctle_gain_max_startbit 0 +#define rx_ctle_gain_max_width 4 +#define rx_ctle_gain_max_endbit 3 +#define rx_ctle_gain_max_shift 12 +#define rx_ctle_gain_max_mask 0xf000 + + +#define rx_ctle_update_mode_addr 0b100011001 +#define rx_ctle_update_mode_startbit 2 +#define rx_ctle_update_mode_width 1 +#define rx_ctle_update_mode_endbit 2 +#define rx_ctle_update_mode_shift 13 +#define rx_ctle_update_mode_mask 0x2000 + + +#define rx_current_recal_init_lane_addr 0b101011011 +#define rx_current_recal_init_lane_startbit 2 +#define rx_current_recal_init_lane_width 5 +#define rx_current_recal_init_lane_endbit 6 +#define rx_current_recal_init_lane_shift 9 +#define rx_current_recal_init_lane_mask 0x3e00 + + +#define rx_dac_bo_cfg_addr 0b100001101 +#define rx_dac_bo_cfg_startbit 4 +#define rx_dac_bo_cfg_width 3 +#define rx_dac_bo_cfg_endbit 6 +#define rx_dac_bo_cfg_shift 9 +#define rx_dac_bo_cfg_mask 0xe00 + + +#define rx_dactest_Hlmt_addr 0b100100110 +#define rx_dactest_Hlmt_startbit 0 +#define rx_dactest_Hlmt_width 9 +#define rx_dactest_Hlmt_endbit 8 +#define rx_dactest_Hlmt_shift 7 +#define rx_dactest_Hlmt_mask 0xff80 + + +#define rx_dactest_Llmt_addr 0b100100101 +#define rx_dactest_Llmt_startbit 0 +#define rx_dactest_Llmt_width 9 +#define rx_dactest_Llmt_endbit 8 +#define rx_dactest_Llmt_shift 7 +#define rx_dactest_Llmt_mask 0xff80 + + +#define rx_dactest_diff_addr 0b101011001 +#define rx_dactest_diff_startbit 3 +#define rx_dactest_diff_width 9 +#define rx_dactest_diff_endbit 11 +#define rx_dactest_diff_shift 4 +#define rx_dactest_diff_mask 0x1ff0 + + +#define rx_dactest_iseq_addr 0b101011001 +#define rx_dactest_iseq_startbit 2 +#define rx_dactest_iseq_width 1 +#define rx_dactest_iseq_endbit 2 +#define rx_dactest_iseq_shift 13 +#define rx_dactest_iseq_mask 0x2000 + + +#define rx_dactest_isgt_addr 0b101011001 +#define rx_dactest_isgt_startbit 0 +#define rx_dactest_isgt_width 1 +#define rx_dactest_isgt_endbit 0 +#define rx_dactest_isgt_shift 15 +#define rx_dactest_isgt_mask 0x8000 + + +#define rx_dactest_islt_addr 0b101011001 +#define rx_dactest_islt_startbit 1 +#define rx_dactest_islt_width 1 +#define rx_dactest_islt_endbit 1 +#define rx_dactest_islt_shift 14 +#define rx_dactest_islt_mask 0x4000 + + +#define rx_dactest_reset_addr 0b100100101 +#define rx_dactest_reset_startbit 9 +#define rx_dactest_reset_width 1 +#define rx_dactest_reset_endbit 9 +#define rx_dactest_reset_shift 6 +#define rx_dactest_reset_mask 0x40 + + +#define rx_dactest_start_addr 0b100100101 +#define rx_dactest_start_startbit 10 +#define rx_dactest_start_width 1 +#define rx_dactest_start_endbit 10 +#define rx_dactest_start_shift 5 +#define rx_dactest_start_mask 0x20 + + +#define rx_data_pipe_0_15_addr 0b101110101 +#define rx_data_pipe_0_15_startbit 0 +#define rx_data_pipe_0_15_width 16 +#define rx_data_pipe_0_15_endbit 15 +#define rx_data_pipe_0_15_shift 0 +#define rx_data_pipe_0_15_mask 0xffff + + +#define rx_data_pipe_16_31_addr 0b101110110 +#define rx_data_pipe_16_31_startbit 0 +#define rx_data_pipe_16_31_width 16 +#define rx_data_pipe_16_31_endbit 15 +#define rx_data_pipe_16_31_shift 0 +#define rx_data_pipe_16_31_mask 0xffff + + +#define rx_data_pipe_capture_addr 0b101110001 +#define rx_data_pipe_capture_startbit 4 +#define rx_data_pipe_capture_width 1 +#define rx_data_pipe_capture_endbit 4 +#define rx_data_pipe_capture_shift 11 +#define rx_data_pipe_capture_mask 0x800 + + +#define rx_data_pipe_clr_on_read_mode_addr 0b100000011 +#define rx_data_pipe_clr_on_read_mode_startbit 11 +#define rx_data_pipe_clr_on_read_mode_width 1 +#define rx_data_pipe_clr_on_read_mode_endbit 11 +#define rx_data_pipe_clr_on_read_mode_shift 4 +#define rx_data_pipe_clr_on_read_mode_mask 0x10 + + +#define rx_dc_enable_cm_coarse_cal_addr 0b100101111 +#define rx_dc_enable_cm_coarse_cal_startbit 0 +#define rx_dc_enable_cm_coarse_cal_width 1 +#define rx_dc_enable_cm_coarse_cal_endbit 0 +#define rx_dc_enable_cm_coarse_cal_shift 15 +#define rx_dc_enable_cm_coarse_cal_mask 0x8000 + + +#define rx_dc_enable_cm_fine_cal_addr 0b100101111 +#define rx_dc_enable_cm_fine_cal_startbit 1 +#define rx_dc_enable_cm_fine_cal_width 1 +#define rx_dc_enable_cm_fine_cal_endbit 1 +#define rx_dc_enable_cm_fine_cal_shift 14 +#define rx_dc_enable_cm_fine_cal_mask 0x4000 + + +#define rx_dc_enable_ctle_1st_latch_offset_cal_addr 0b100101111 +#define rx_dc_enable_ctle_1st_latch_offset_cal_startbit 2 +#define rx_dc_enable_ctle_1st_latch_offset_cal_width 1 +#define rx_dc_enable_ctle_1st_latch_offset_cal_endbit 2 +#define rx_dc_enable_ctle_1st_latch_offset_cal_shift 13 +#define rx_dc_enable_ctle_1st_latch_offset_cal_mask 0x2000 + + +#define rx_dc_enable_ctle_2nd_latch_offset_cal_addr 0b100101111 +#define rx_dc_enable_ctle_2nd_latch_offset_cal_startbit 3 +#define rx_dc_enable_ctle_2nd_latch_offset_cal_width 1 +#define rx_dc_enable_ctle_2nd_latch_offset_cal_endbit 3 +#define rx_dc_enable_ctle_2nd_latch_offset_cal_shift 12 +#define rx_dc_enable_ctle_2nd_latch_offset_cal_mask 0x1000 + + +#define rx_dc_enable_integ_latch_offset_cal_addr 0b100101111 +#define rx_dc_enable_integ_latch_offset_cal_startbit 4 +#define rx_dc_enable_integ_latch_offset_cal_width 1 +#define rx_dc_enable_integ_latch_offset_cal_endbit 4 +#define rx_dc_enable_integ_latch_offset_cal_shift 11 +#define rx_dc_enable_integ_latch_offset_cal_mask 0x800 + + +#define rx_ddc_cfg_addr 0b001000110 +#define rx_ddc_cfg_startbit 5 +#define rx_ddc_cfg_width 2 +#define rx_ddc_cfg_endbit 6 +#define rx_ddc_cfg_shift 9 +#define rx_ddc_cfg_mask 0x600 + + +#define rx_dfe_ca_cfg_addr 0b100000011 +#define rx_dfe_ca_cfg_startbit 0 +#define rx_dfe_ca_cfg_width 2 +#define rx_dfe_ca_cfg_endbit 1 +#define rx_dfe_ca_cfg_shift 14 +#define rx_dfe_ca_cfg_mask 0xc000 + + +#define rx_dfe_converged_cnt_max_addr 0b100010101 +#define rx_dfe_converged_cnt_max_startbit 0 +#define rx_dfe_converged_cnt_max_width 4 +#define rx_dfe_converged_cnt_max_endbit 3 +#define rx_dfe_converged_cnt_max_shift 12 +#define rx_dfe_converged_cnt_max_mask 0xf000 + + +#define rx_disable_h1_clear_addr 0b100001101 +#define rx_disable_h1_clear_startbit 11 +#define rx_disable_h1_clear_width 1 +#define rx_disable_h1_clear_endbit 11 +#define rx_disable_h1_clear_shift 4 +#define rx_disable_h1_clear_mask 0x10 + + +#define rx_eo_converged_end_count_addr 0b100000111 +#define rx_eo_converged_end_count_startbit 0 +#define rx_eo_converged_end_count_width 4 +#define rx_eo_converged_end_count_endbit 3 +#define rx_eo_converged_end_count_shift 12 +#define rx_eo_converged_end_count_mask 0xf000 + + +#define rx_eo_enable_VGA_amax_mode_addr 0b100101101 +#define rx_eo_enable_VGA_amax_mode_startbit 2 +#define rx_eo_enable_VGA_amax_mode_width 1 +#define rx_eo_enable_VGA_amax_mode_endbit 2 +#define rx_eo_enable_VGA_amax_mode_shift 13 +#define rx_eo_enable_VGA_amax_mode_mask 0x2000 + + +#define rx_eo_enable_cm_coarse_cal_addr 0b100010110 +#define rx_eo_enable_cm_coarse_cal_startbit 7 +#define rx_eo_enable_cm_coarse_cal_width 1 +#define rx_eo_enable_cm_coarse_cal_endbit 7 +#define rx_eo_enable_cm_coarse_cal_shift 8 +#define rx_eo_enable_cm_coarse_cal_mask 0x100 + + +#define rx_eo_enable_cm_fine_cal_addr 0b100010110 +#define rx_eo_enable_cm_fine_cal_startbit 8 +#define rx_eo_enable_cm_fine_cal_width 1 +#define rx_eo_enable_cm_fine_cal_endbit 8 +#define rx_eo_enable_cm_fine_cal_shift 7 +#define rx_eo_enable_cm_fine_cal_mask 0x80 + + +#define rx_eo_enable_ctle_1st_latch_offset_cal_addr 0b100101101 +#define rx_eo_enable_ctle_1st_latch_offset_cal_startbit 0 +#define rx_eo_enable_ctle_1st_latch_offset_cal_width 1 +#define rx_eo_enable_ctle_1st_latch_offset_cal_endbit 0 +#define rx_eo_enable_ctle_1st_latch_offset_cal_shift 15 +#define rx_eo_enable_ctle_1st_latch_offset_cal_mask 0x8000 + + +#define rx_eo_enable_ctle_2nd_latch_offset_cal_addr 0b100101101 +#define rx_eo_enable_ctle_2nd_latch_offset_cal_startbit 1 +#define rx_eo_enable_ctle_2nd_latch_offset_cal_width 1 +#define rx_eo_enable_ctle_2nd_latch_offset_cal_endbit 1 +#define rx_eo_enable_ctle_2nd_latch_offset_cal_shift 14 +#define rx_eo_enable_ctle_2nd_latch_offset_cal_mask 0x4000 + + +#define rx_eo_enable_ctle_coarse_cal_addr 0b100010110 +#define rx_eo_enable_ctle_coarse_cal_startbit 1 +#define rx_eo_enable_ctle_coarse_cal_width 1 +#define rx_eo_enable_ctle_coarse_cal_endbit 1 +#define rx_eo_enable_ctle_coarse_cal_shift 14 +#define rx_eo_enable_ctle_coarse_cal_mask 0x4000 + + +#define rx_eo_enable_dac_h1_cal_addr 0b100010110 +#define rx_eo_enable_dac_h1_cal_startbit 2 +#define rx_eo_enable_dac_h1_cal_width 1 +#define rx_eo_enable_dac_h1_cal_endbit 2 +#define rx_eo_enable_dac_h1_cal_shift 13 +#define rx_eo_enable_dac_h1_cal_mask 0x2000 + + +#define rx_eo_enable_ddc_addr 0b100010110 +#define rx_eo_enable_ddc_startbit 6 +#define rx_eo_enable_ddc_width 1 +#define rx_eo_enable_ddc_endbit 6 +#define rx_eo_enable_ddc_shift 9 +#define rx_eo_enable_ddc_mask 0x200 + + +#define rx_eo_enable_dfe_h1_cal_addr 0b100010110 +#define rx_eo_enable_dfe_h1_cal_startbit 4 +#define rx_eo_enable_dfe_h1_cal_width 1 +#define rx_eo_enable_dfe_h1_cal_endbit 4 +#define rx_eo_enable_dfe_h1_cal_shift 11 +#define rx_eo_enable_dfe_h1_cal_mask 0x800 + + +#define rx_eo_enable_h1ap_tweak_addr 0b100010110 +#define rx_eo_enable_h1ap_tweak_startbit 5 +#define rx_eo_enable_h1ap_tweak_width 1 +#define rx_eo_enable_h1ap_tweak_endbit 5 +#define rx_eo_enable_h1ap_tweak_shift 10 +#define rx_eo_enable_h1ap_tweak_mask 0x400 + + +#define rx_eo_enable_integ_latch_offset_cal_addr 0b100010110 +#define rx_eo_enable_integ_latch_offset_cal_startbit 0 +#define rx_eo_enable_integ_latch_offset_cal_width 1 +#define rx_eo_enable_integ_latch_offset_cal_endbit 0 +#define rx_eo_enable_integ_latch_offset_cal_shift 15 +#define rx_eo_enable_integ_latch_offset_cal_mask 0x8000 + + +#define rx_eo_enable_vga_cal_addr 0b100010110 +#define rx_eo_enable_vga_cal_startbit 3 +#define rx_eo_enable_vga_cal_width 1 +#define rx_eo_enable_vga_cal_endbit 3 +#define rx_eo_enable_vga_cal_shift 12 +#define rx_eo_enable_vga_cal_mask 0x1000 + + +#define rx_eye_opt_state_addr 0b101010111 +#define rx_eye_opt_state_startbit 0 +#define rx_eye_opt_state_width 12 +#define rx_eye_opt_state_endbit 11 +#define rx_eye_opt_state_shift 4 +#define rx_eye_opt_state_mask 0xfff0 + + +#define rx_fifo_dly_cfg_addr 0b001000110 +#define rx_fifo_dly_cfg_startbit 3 +#define rx_fifo_dly_cfg_width 2 +#define rx_fifo_dly_cfg_endbit 4 +#define rx_fifo_dly_cfg_shift 11 +#define rx_fifo_dly_cfg_mask 0x1800 + + +#define rx_filter_mode_addr 0b100001101 +#define rx_filter_mode_startbit 7 +#define rx_filter_mode_width 2 +#define rx_filter_mode_endbit 8 +#define rx_filter_mode_shift 7 +#define rx_filter_mode_mask 0x180 + + +#define rx_fir_msg_addr 0b111111111 +#define rx_fir_msg_startbit 0 +#define rx_fir_msg_width 8 +#define rx_fir_msg_endbit 7 +#define rx_fir_msg_shift 8 +#define rx_fir_msg_mask 0xff00 + + +#define rx_fir_reset_addr 0b101010110 +#define rx_fir_reset_startbit 15 +#define rx_fir_reset_width 1 +#define rx_fir_reset_endbit 15 +#define rx_fir_reset_shift 0 +#define rx_fir_reset_mask 0x1 + + +#define rx_h1ap_cfg_addr 0b100011001 +#define rx_h1ap_cfg_startbit 0 +#define rx_h1ap_cfg_width 2 +#define rx_h1ap_cfg_endbit 1 +#define rx_h1ap_cfg_shift 14 +#define rx_h1ap_cfg_mask 0xc000 + + +#define rx_hist_min_eye_height_addr 0b100101000 +#define rx_hist_min_eye_height_startbit 6 +#define rx_hist_min_eye_height_width 8 +#define rx_hist_min_eye_height_endbit 13 +#define rx_hist_min_eye_height_shift 2 +#define rx_hist_min_eye_height_mask 0x3fc + + +#define rx_hist_min_eye_height_lane_addr 0b100101000 +#define rx_hist_min_eye_height_lane_startbit 1 +#define rx_hist_min_eye_height_lane_width 5 +#define rx_hist_min_eye_height_lane_endbit 5 +#define rx_hist_min_eye_height_lane_shift 10 +#define rx_hist_min_eye_height_lane_mask 0x7c00 + + +#define rx_hist_min_eye_height_mode_addr 0b100000111 +#define rx_hist_min_eye_height_mode_startbit 6 +#define rx_hist_min_eye_height_mode_width 2 +#define rx_hist_min_eye_height_mode_endbit 7 +#define rx_hist_min_eye_height_mode_shift 8 +#define rx_hist_min_eye_height_mode_mask 0x300 + + +#define rx_hist_min_eye_height_valid_addr 0b100101000 +#define rx_hist_min_eye_height_valid_startbit 0 +#define rx_hist_min_eye_height_valid_width 1 +#define rx_hist_min_eye_height_valid_endbit 0 +#define rx_hist_min_eye_height_valid_shift 15 +#define rx_hist_min_eye_height_valid_mask 0x8000 + + +#define rx_hist_min_eye_width_addr 0b100100111 +#define rx_hist_min_eye_width_startbit 6 +#define rx_hist_min_eye_width_width 8 +#define rx_hist_min_eye_width_endbit 13 +#define rx_hist_min_eye_width_shift 2 +#define rx_hist_min_eye_width_mask 0x3fc + + +#define rx_hist_min_eye_width_lane_addr 0b100100111 +#define rx_hist_min_eye_width_lane_startbit 1 +#define rx_hist_min_eye_width_lane_width 5 +#define rx_hist_min_eye_width_lane_endbit 5 +#define rx_hist_min_eye_width_lane_shift 10 +#define rx_hist_min_eye_width_lane_mask 0x7c00 + + +#define rx_hist_min_eye_width_mode_addr 0b100000111 +#define rx_hist_min_eye_width_mode_startbit 4 +#define rx_hist_min_eye_width_mode_width 2 +#define rx_hist_min_eye_width_mode_endbit 5 +#define rx_hist_min_eye_width_mode_shift 10 +#define rx_hist_min_eye_width_mode_mask 0xc00 + + +#define rx_hist_min_eye_width_valid_addr 0b100100111 +#define rx_hist_min_eye_width_valid_startbit 0 +#define rx_hist_min_eye_width_valid_width 1 +#define rx_hist_min_eye_width_valid_endbit 0 +#define rx_hist_min_eye_width_valid_shift 15 +#define rx_hist_min_eye_width_valid_mask 0x8000 + + +#define rx_int_current_state_addr 0b100011101 +#define rx_int_current_state_startbit 4 +#define rx_int_current_state_width 12 +#define rx_int_current_state_endbit 15 +#define rx_int_current_state_shift 0 +#define rx_int_current_state_mask 0xfff + + +#define rx_int_enable_enc_addr 0b100011110 +#define rx_int_enable_enc_startbit 0 +#define rx_int_enable_enc_width 4 +#define rx_int_enable_enc_endbit 3 +#define rx_int_enable_enc_shift 12 +#define rx_int_enable_enc_mask 0xf000 + + +#define rx_int_goto_state_addr 0b100011111 +#define rx_int_goto_state_startbit 4 +#define rx_int_goto_state_width 12 +#define rx_int_goto_state_endbit 15 +#define rx_int_goto_state_shift 0 +#define rx_int_goto_state_mask 0xfff + + +#define rx_int_mode_addr 0b100011101 +#define rx_int_mode_startbit 0 +#define rx_int_mode_width 4 +#define rx_int_mode_endbit 3 +#define rx_int_mode_shift 12 +#define rx_int_mode_mask 0xf000 + + +#define rx_int_next_state_addr 0b100011110 +#define rx_int_next_state_startbit 4 +#define rx_int_next_state_width 12 +#define rx_int_next_state_endbit 15 +#define rx_int_next_state_shift 0 +#define rx_int_next_state_mask 0xfff + + +#define rx_int_req_addr 0b101011010 +#define rx_int_req_startbit 0 +#define rx_int_req_width 16 +#define rx_int_req_endbit 15 +#define rx_int_req_shift 0 +#define rx_int_req_mask 0xffff + + +#define rx_int_return_addr 0b101011110 +#define rx_int_return_startbit 1 +#define rx_int_return_width 1 +#define rx_int_return_endbit 1 +#define rx_int_return_shift 14 +#define rx_int_return_mask 0x4000 + + +#define rx_int_return_state_addr 0b100100000 +#define rx_int_return_state_startbit 4 +#define rx_int_return_state_width 12 +#define rx_int_return_state_endbit 15 +#define rx_int_return_state_shift 0 +#define rx_int_return_state_mask 0xfff + + +#define rx_intr_msg_addr 0b111111110 +#define rx_intr_msg_startbit 0 +#define rx_intr_msg_width 16 +#define rx_intr_msg_endbit 15 +#define rx_intr_msg_shift 0 +#define rx_intr_msg_mask 0xffff + +#define rx_dac_cntl1_eo_pl_addr 0b000000001 +#define rx_dac_cntl1_eo_pl_startbit 0 +#define rx_dac_cntl1_eo_pl_width 16 +#define rx_dac_cntl1_eo_pl_endbit 15 +#define rx_dac_cntl1_eo_pl_shift 0 +#define rx_dac_cntl1_eo_pl_mask 0xffff + + +#define rx_lane_ana_pdwn_addr 0b000000001 +#define rx_lane_ana_pdwn_startbit 6 +#define rx_lane_ana_pdwn_width 1 +#define rx_lane_ana_pdwn_endbit 6 +#define rx_lane_ana_pdwn_shift 9 +#define rx_lane_ana_pdwn_mask 0x200 + + +#define rx_lane_currently_initializing_addr 0b101011011 +#define rx_lane_currently_initializing_startbit 0 +#define rx_lane_currently_initializing_width 1 +#define rx_lane_currently_initializing_endbit 0 +#define rx_lane_currently_initializing_shift 15 +#define rx_lane_currently_initializing_mask 0x8000 + + +#define rx_lane_currently_recalibrating_addr 0b101011011 +#define rx_lane_currently_recalibrating_startbit 1 +#define rx_lane_currently_recalibrating_width 1 +#define rx_lane_currently_recalibrating_endbit 1 +#define rx_lane_currently_recalibrating_shift 14 +#define rx_lane_currently_recalibrating_mask 0x4000 + + +#define rx_lane_dig_pdwn_addr 0b001000100 +#define rx_lane_dig_pdwn_startbit 0 +#define rx_lane_dig_pdwn_width 1 +#define rx_lane_dig_pdwn_endbit 0 +#define rx_lane_dig_pdwn_shift 15 +#define rx_lane_dig_pdwn_mask 0x8000 + + +#define rx_loff_amp_en_addr 0b100001101 +#define rx_loff_amp_en_startbit 15 +#define rx_loff_amp_en_width 1 +#define rx_loff_amp_en_endbit 15 +#define rx_loff_amp_en_shift 0 +#define rx_loff_amp_en_mask 0x1 + + +#define rx_manual_recal_abort_addr 0b101011110 +#define rx_manual_recal_abort_startbit 2 +#define rx_manual_recal_abort_width 1 +#define rx_manual_recal_abort_endbit 2 +#define rx_manual_recal_abort_shift 13 +#define rx_manual_recal_abort_mask 0x2000 + + +#define rx_manual_recal_continue_addr 0b101011110 +#define rx_manual_recal_continue_startbit 3 +#define rx_manual_recal_continue_width 1 +#define rx_manual_recal_continue_endbit 3 +#define rx_manual_recal_continue_shift 12 +#define rx_manual_recal_continue_mask 0x1000 + + +#define rx_manual_recal_done_addr 0b101011011 +#define rx_manual_recal_done_startbit 7 +#define rx_manual_recal_done_width 1 +#define rx_manual_recal_done_endbit 7 +#define rx_manual_recal_done_shift 8 +#define rx_manual_recal_done_mask 0x100 + + +#define rx_manual_recal_lane_addr 0b101011101 +#define rx_manual_recal_lane_startbit 3 +#define rx_manual_recal_lane_width 5 +#define rx_manual_recal_lane_endbit 7 +#define rx_manual_recal_lane_shift 8 +#define rx_manual_recal_lane_mask 0x1f00 + + +#define rx_manual_recal_request_addr 0b101011101 +#define rx_manual_recal_request_startbit 0 +#define rx_manual_recal_request_width 1 +#define rx_manual_recal_request_endbit 0 +#define rx_manual_recal_request_shift 15 +#define rx_manual_recal_request_mask 0x8000 + + +#define rx_min_eye_height_addr 0b100001010 +#define rx_min_eye_height_startbit 8 +#define rx_min_eye_height_width 8 +#define rx_min_eye_height_endbit 15 +#define rx_min_eye_height_shift 0 +#define rx_min_eye_height_mask 0xff + + +#define rx_min_eye_width_addr 0b100001010 +#define rx_min_eye_width_startbit 2 +#define rx_min_eye_width_width 6 +#define rx_min_eye_width_endbit 7 +#define rx_min_eye_width_shift 8 +#define rx_min_eye_width_mask 0x3f00 + + +#define rx_misc_cfg_addr 0b100001101 +#define rx_misc_cfg_startbit 9 +#define rx_misc_cfg_width 2 +#define rx_misc_cfg_endbit 10 +#define rx_misc_cfg_shift 5 +#define rx_misc_cfg_mask 0x60 + + +#define rx_off_init_cfg_addr 0b100001100 +#define rx_off_init_cfg_startbit 0 +#define rx_off_init_cfg_width 3 +#define rx_off_init_cfg_endbit 2 +#define rx_off_init_cfg_shift 13 +#define rx_off_init_cfg_mask 0xe000 + + +#define rx_off_init_timeout_addr 0b100010000 +#define rx_off_init_timeout_startbit 0 +#define rx_off_init_timeout_width 4 +#define rx_off_init_timeout_endbit 3 +#define rx_off_init_timeout_shift 12 +#define rx_off_init_timeout_mask 0xf000 + + +#define rx_off_recal_cfg_addr 0b100001100 +#define rx_off_recal_cfg_startbit 3 +#define rx_off_recal_cfg_width 3 +#define rx_off_recal_cfg_endbit 5 +#define rx_off_recal_cfg_shift 10 +#define rx_off_recal_cfg_mask 0x1c00 + + +#define rx_off_recal_timeout_addr 0b100010000 +#define rx_off_recal_timeout_startbit 4 +#define rx_off_recal_timeout_width 4 +#define rx_off_recal_timeout_endbit 7 +#define rx_off_recal_timeout_shift 8 +#define rx_off_recal_timeout_mask 0xf00 + + +#define rx_pb_clr_par_errs_addr 0b111110000 +#define rx_pb_clr_par_errs_startbit 14 +#define rx_pb_clr_par_errs_width 1 +#define rx_pb_clr_par_errs_endbit 14 +#define rx_pb_clr_par_errs_shift 1 +#define rx_pb_clr_par_errs_mask 0x2 + + +#define rx_pb_fir_errs_addr 0b111110001 +#define rx_pb_fir_errs_startbit 0 +#define rx_pb_fir_errs_width 10 +#define rx_pb_fir_errs_endbit 9 +#define rx_pb_fir_errs_shift 6 +#define rx_pb_fir_errs_mask 0xffc0 + + +#define rx_pb_fir_errs_inj_addr 0b111110011 +#define rx_pb_fir_errs_inj_startbit 0 +#define rx_pb_fir_errs_inj_width 10 +#define rx_pb_fir_errs_inj_endbit 9 +#define rx_pb_fir_errs_inj_shift 6 +#define rx_pb_fir_errs_inj_mask 0xffc0 + + +#define rx_pb_fir_errs_mask_addr 0b111110010 +#define rx_pb_fir_errs_mask_startbit 0 +#define rx_pb_fir_errs_mask_width 10 +#define rx_pb_fir_errs_mask_endbit 9 +#define rx_pb_fir_errs_mask_shift 6 +#define rx_pb_fir_errs_mask_mask 0xffc0 + + +#define rx_pb_fir_reset_addr 0b111110000 +#define rx_pb_fir_reset_startbit 15 +#define rx_pb_fir_reset_width 1 +#define rx_pb_fir_reset_endbit 15 +#define rx_pb_fir_reset_shift 0 +#define rx_pb_fir_reset_mask 0x1 + + +#define rx_peak_init_cfg_addr 0b100001011 +#define rx_peak_init_cfg_startbit 6 +#define rx_peak_init_cfg_width 3 +#define rx_peak_init_cfg_endbit 8 +#define rx_peak_init_cfg_shift 7 +#define rx_peak_init_cfg_mask 0x380 + + +#define rx_peak_init_timeout_addr 0b100001111 +#define rx_peak_init_timeout_startbit 8 +#define rx_peak_init_timeout_width 4 +#define rx_peak_init_timeout_endbit 11 +#define rx_peak_init_timeout_shift 4 +#define rx_peak_init_timeout_mask 0xf0 + + +#define rx_peak_recal_cfg_addr 0b100001011 +#define rx_peak_recal_cfg_startbit 9 +#define rx_peak_recal_cfg_width 3 +#define rx_peak_recal_cfg_endbit 11 +#define rx_peak_recal_cfg_shift 4 +#define rx_peak_recal_cfg_mask 0x70 + + +#define rx_peak_recal_timeout_addr 0b100001111 +#define rx_peak_recal_timeout_startbit 12 +#define rx_peak_recal_timeout_width 4 +#define rx_peak_recal_timeout_endbit 15 +#define rx_peak_recal_timeout_shift 0 +#define rx_peak_recal_timeout_mask 0xf + + +#define rx_pervasive_capt_addr 0b100100011 +#define rx_pervasive_capt_startbit 14 +#define rx_pervasive_capt_width 1 +#define rx_pervasive_capt_endbit 14 +#define rx_pervasive_capt_shift 1 +#define rx_pervasive_capt_mask 0x2 + + +#define rx_pg_datasm_spare_mode_0_addr 0b101110000 +#define rx_pg_datasm_spare_mode_0_startbit 0 +#define rx_pg_datasm_spare_mode_0_width 1 +#define rx_pg_datasm_spare_mode_0_endbit 0 +#define rx_pg_datasm_spare_mode_0_shift 15 +#define rx_pg_datasm_spare_mode_0_mask 0x8000 + + +#define rx_pg_datasm_spare_mode_1_addr 0b101110000 +#define rx_pg_datasm_spare_mode_1_startbit 1 +#define rx_pg_datasm_spare_mode_1_width 1 +#define rx_pg_datasm_spare_mode_1_endbit 1 +#define rx_pg_datasm_spare_mode_1_shift 14 +#define rx_pg_datasm_spare_mode_1_mask 0x4000 + + +#define rx_pg_datasm_spare_mode_2_addr 0b101110000 +#define rx_pg_datasm_spare_mode_2_startbit 2 +#define rx_pg_datasm_spare_mode_2_width 1 +#define rx_pg_datasm_spare_mode_2_endbit 2 +#define rx_pg_datasm_spare_mode_2_shift 13 +#define rx_pg_datasm_spare_mode_2_mask 0x2000 + + +#define rx_pg_datasm_spare_mode_3_addr 0b101110000 +#define rx_pg_datasm_spare_mode_3_startbit 3 +#define rx_pg_datasm_spare_mode_3_width 1 +#define rx_pg_datasm_spare_mode_3_endbit 3 +#define rx_pg_datasm_spare_mode_3_shift 12 +#define rx_pg_datasm_spare_mode_3_mask 0x1000 + + +#define rx_pg_datasm_spare_mode_4_addr 0b101110000 +#define rx_pg_datasm_spare_mode_4_startbit 4 +#define rx_pg_datasm_spare_mode_4_width 1 +#define rx_pg_datasm_spare_mode_4_endbit 4 +#define rx_pg_datasm_spare_mode_4_shift 11 +#define rx_pg_datasm_spare_mode_4_mask 0x800 + + +#define rx_pg_datasm_spare_mode_5_addr 0b101110000 +#define rx_pg_datasm_spare_mode_5_startbit 5 +#define rx_pg_datasm_spare_mode_5_width 1 +#define rx_pg_datasm_spare_mode_5_endbit 5 +#define rx_pg_datasm_spare_mode_5_shift 10 +#define rx_pg_datasm_spare_mode_5_mask 0x400 + + +#define rx_pg_datasm_spare_mode_6_addr 0b101110000 +#define rx_pg_datasm_spare_mode_6_startbit 6 +#define rx_pg_datasm_spare_mode_6_width 1 +#define rx_pg_datasm_spare_mode_6_endbit 6 +#define rx_pg_datasm_spare_mode_6_shift 9 +#define rx_pg_datasm_spare_mode_6_mask 0x200 + + +#define rx_pg_datasm_spare_mode_7_addr 0b101110000 +#define rx_pg_datasm_spare_mode_7_startbit 7 +#define rx_pg_datasm_spare_mode_7_width 1 +#define rx_pg_datasm_spare_mode_7_endbit 7 +#define rx_pg_datasm_spare_mode_7_shift 8 +#define rx_pg_datasm_spare_mode_7_mask 0x100 + + +#define rx_pg_fir1_err_inj_addr 0b101010011 +#define rx_pg_fir1_err_inj_startbit 0 +#define rx_pg_fir1_err_inj_width 15 +#define rx_pg_fir1_err_inj_endbit 14 +#define rx_pg_fir1_err_inj_shift 1 +#define rx_pg_fir1_err_inj_mask 0xfffe + + +#define rx_pg_fir1_errs_mask_addr 0b101010010 +#define rx_pg_fir1_errs_mask_startbit 0 +#define rx_pg_fir1_errs_mask_width 15 +#define rx_pg_fir1_errs_mask_endbit 14 +#define rx_pg_fir1_errs_mask_shift 1 +#define rx_pg_fir1_errs_mask_mask 0xfffe + + +#define rx_pg_fir_err_bist_init_state_addr 0b101010001 +#define rx_pg_fir_err_bist_init_state_startbit 10 +#define rx_pg_fir_err_bist_init_state_width 1 +#define rx_pg_fir_err_bist_init_state_endbit 10 +#define rx_pg_fir_err_bist_init_state_shift 5 +#define rx_pg_fir_err_bist_init_state_mask 0x20 + + +#define rx_pg_fir_err_bist_main_state_addr 0b101010001 +#define rx_pg_fir_err_bist_main_state_startbit 9 +#define rx_pg_fir_err_bist_main_state_width 1 +#define rx_pg_fir_err_bist_main_state_endbit 9 +#define rx_pg_fir_err_bist_main_state_shift 6 +#define rx_pg_fir_err_bist_main_state_mask 0x40 + + +#define rx_pg_fir_err_datasm_regrw_addr 0b101010001 +#define rx_pg_fir_err_datasm_regrw_startbit 7 +#define rx_pg_fir_err_datasm_regrw_width 1 +#define rx_pg_fir_err_datasm_regrw_endbit 7 +#define rx_pg_fir_err_datasm_regrw_shift 8 +#define rx_pg_fir_err_datasm_regrw_mask 0x100 + + +#define rx_pg_fir_err_datasm_regs_addr 0b101010001 +#define rx_pg_fir_err_datasm_regs_startbit 6 +#define rx_pg_fir_err_datasm_regs_width 1 +#define rx_pg_fir_err_datasm_regs_endbit 6 +#define rx_pg_fir_err_datasm_regs_shift 9 +#define rx_pg_fir_err_datasm_regs_mask 0x200 + + +#define rx_pg_fir_err_eyeopt_sm_addr 0b101010001 +#define rx_pg_fir_err_eyeopt_sm_startbit 8 +#define rx_pg_fir_err_eyeopt_sm_width 1 +#define rx_pg_fir_err_eyeopt_sm_endbit 8 +#define rx_pg_fir_err_eyeopt_sm_shift 7 +#define rx_pg_fir_err_eyeopt_sm_mask 0x80 + + +#define rx_pg_fir_err_gcr_buff_addr 0b101010001 +#define rx_pg_fir_err_gcr_buff_startbit 1 +#define rx_pg_fir_err_gcr_buff_width 1 +#define rx_pg_fir_err_gcr_buff_endbit 1 +#define rx_pg_fir_err_gcr_buff_shift 14 +#define rx_pg_fir_err_gcr_buff_mask 0x4000 + + +#define rx_pg_fir_err_gcrs_ld_sm_addr 0b101010001 +#define rx_pg_fir_err_gcrs_ld_sm_startbit 2 +#define rx_pg_fir_err_gcrs_ld_sm_width 1 +#define rx_pg_fir_err_gcrs_ld_sm_endbit 2 +#define rx_pg_fir_err_gcrs_ld_sm_shift 13 +#define rx_pg_fir_err_gcrs_ld_sm_mask 0x2000 + + +#define rx_pg_fir_err_gcrs_unld_sm_addr 0b101010001 +#define rx_pg_fir_err_gcrs_unld_sm_startbit 3 +#define rx_pg_fir_err_gcrs_unld_sm_width 1 +#define rx_pg_fir_err_gcrs_unld_sm_endbit 3 +#define rx_pg_fir_err_gcrs_unld_sm_shift 12 +#define rx_pg_fir_err_gcrs_unld_sm_mask 0x1000 + + +#define rx_pg_fir_err_glbsm_regrw_addr 0b101010001 +#define rx_pg_fir_err_glbsm_regrw_startbit 5 +#define rx_pg_fir_err_glbsm_regrw_width 1 +#define rx_pg_fir_err_glbsm_regrw_endbit 5 +#define rx_pg_fir_err_glbsm_regrw_shift 10 +#define rx_pg_fir_err_glbsm_regrw_mask 0x400 + + +#define rx_pg_fir_err_glbsm_regs_addr 0b101010001 +#define rx_pg_fir_err_glbsm_regs_startbit 4 +#define rx_pg_fir_err_glbsm_regs_width 1 +#define rx_pg_fir_err_glbsm_regs_endbit 4 +#define rx_pg_fir_err_glbsm_regs_shift 11 +#define rx_pg_fir_err_glbsm_regs_mask 0x800 + + +#define rx_pg_fir_err_pg_regs_addr 0b101010001 +#define rx_pg_fir_err_pg_regs_startbit 0 +#define rx_pg_fir_err_pg_regs_width 1 +#define rx_pg_fir_err_pg_regs_endbit 0 +#define rx_pg_fir_err_pg_regs_shift 15 +#define rx_pg_fir_err_pg_regs_mask 0x8000 + + +#define rx_pg_fir_err_rx_servo_sm_addr 0b101010001 +#define rx_pg_fir_err_rx_servo_sm_startbit 11 +#define rx_pg_fir_err_rx_servo_sm_width 1 +#define rx_pg_fir_err_rx_servo_sm_endbit 11 +#define rx_pg_fir_err_rx_servo_sm_shift 4 +#define rx_pg_fir_err_rx_servo_sm_mask 0x10 + + +#define rx_pg_fir_err_work_regs_addr 0b101010001 +#define rx_pg_fir_err_work_regs_startbit 12 +#define rx_pg_fir_err_work_regs_width 1 +#define rx_pg_fir_err_work_regs_endbit 12 +#define rx_pg_fir_err_work_regs_shift 3 +#define rx_pg_fir_err_work_regs_mask 0x8 + + +#define rx_pg_glbsm_spare_mode_0_addr 0b101010000 +#define rx_pg_glbsm_spare_mode_0_startbit 0 +#define rx_pg_glbsm_spare_mode_0_width 1 +#define rx_pg_glbsm_spare_mode_0_endbit 0 +#define rx_pg_glbsm_spare_mode_0_shift 15 +#define rx_pg_glbsm_spare_mode_0_mask 0x8000 + + +#define rx_pg_glbsm_spare_mode_1_addr 0b101010000 +#define rx_pg_glbsm_spare_mode_1_startbit 1 +#define rx_pg_glbsm_spare_mode_1_width 1 +#define rx_pg_glbsm_spare_mode_1_endbit 1 +#define rx_pg_glbsm_spare_mode_1_shift 14 +#define rx_pg_glbsm_spare_mode_1_mask 0x4000 + + +#define rx_pg_glbsm_spare_mode_2_addr 0b101010000 +#define rx_pg_glbsm_spare_mode_2_startbit 2 +#define rx_pg_glbsm_spare_mode_2_width 1 +#define rx_pg_glbsm_spare_mode_2_endbit 2 +#define rx_pg_glbsm_spare_mode_2_shift 13 +#define rx_pg_glbsm_spare_mode_2_mask 0x2000 + + +#define rx_pg_glbsm_spare_mode_3_addr 0b101010000 +#define rx_pg_glbsm_spare_mode_3_startbit 3 +#define rx_pg_glbsm_spare_mode_3_width 1 +#define rx_pg_glbsm_spare_mode_3_endbit 3 +#define rx_pg_glbsm_spare_mode_3_shift 12 +#define rx_pg_glbsm_spare_mode_3_mask 0x1000 + + +#define rx_pg_glbsm_spare_mode_4_addr 0b101010000 +#define rx_pg_glbsm_spare_mode_4_startbit 4 +#define rx_pg_glbsm_spare_mode_4_width 1 +#define rx_pg_glbsm_spare_mode_4_endbit 4 +#define rx_pg_glbsm_spare_mode_4_shift 11 +#define rx_pg_glbsm_spare_mode_4_mask 0x800 + + +#define rx_pg_glbsm_spare_mode_5_addr 0b101010000 +#define rx_pg_glbsm_spare_mode_5_startbit 5 +#define rx_pg_glbsm_spare_mode_5_width 1 +#define rx_pg_glbsm_spare_mode_5_endbit 5 +#define rx_pg_glbsm_spare_mode_5_shift 10 +#define rx_pg_glbsm_spare_mode_5_mask 0x400 + + +#define rx_pg_glbsm_spare_mode_6_addr 0b101010000 +#define rx_pg_glbsm_spare_mode_6_startbit 6 +#define rx_pg_glbsm_spare_mode_6_width 1 +#define rx_pg_glbsm_spare_mode_6_endbit 6 +#define rx_pg_glbsm_spare_mode_6_shift 9 +#define rx_pg_glbsm_spare_mode_6_mask 0x200 + + +#define rx_pg_glbsm_spare_mode_7_addr 0b101010000 +#define rx_pg_glbsm_spare_mode_7_startbit 7 +#define rx_pg_glbsm_spare_mode_7_width 1 +#define rx_pg_glbsm_spare_mode_7_endbit 7 +#define rx_pg_glbsm_spare_mode_7_shift 8 +#define rx_pg_glbsm_spare_mode_7_mask 0x100 + + +#define rx_pg_spare_mode_0_addr 0b100000000 +#define rx_pg_spare_mode_0_startbit 0 +#define rx_pg_spare_mode_0_width 1 +#define rx_pg_spare_mode_0_endbit 0 +#define rx_pg_spare_mode_0_shift 15 +#define rx_pg_spare_mode_0_mask 0x8000 + + +#define rx_pg_spare_mode_1_addr 0b100000000 +#define rx_pg_spare_mode_1_startbit 1 +#define rx_pg_spare_mode_1_width 1 +#define rx_pg_spare_mode_1_endbit 1 +#define rx_pg_spare_mode_1_shift 14 +#define rx_pg_spare_mode_1_mask 0x4000 + + +#define rx_pg_spare_mode_2_addr 0b100000000 +#define rx_pg_spare_mode_2_startbit 2 +#define rx_pg_spare_mode_2_width 1 +#define rx_pg_spare_mode_2_endbit 2 +#define rx_pg_spare_mode_2_shift 13 +#define rx_pg_spare_mode_2_mask 0x2000 + + +#define rx_pg_spare_mode_3_addr 0b100000000 +#define rx_pg_spare_mode_3_startbit 3 +#define rx_pg_spare_mode_3_width 1 +#define rx_pg_spare_mode_3_endbit 3 +#define rx_pg_spare_mode_3_shift 12 +#define rx_pg_spare_mode_3_mask 0x1000 + + +#define rx_pg_spare_mode_4_addr 0b100000000 +#define rx_pg_spare_mode_4_startbit 4 +#define rx_pg_spare_mode_4_width 1 +#define rx_pg_spare_mode_4_endbit 4 +#define rx_pg_spare_mode_4_shift 11 +#define rx_pg_spare_mode_4_mask 0x800 + + +#define rx_pl_data_dac_spare_mode_0_addr 0b000000000 +#define rx_pl_data_dac_spare_mode_0_startbit 0 +#define rx_pl_data_dac_spare_mode_0_width 1 +#define rx_pl_data_dac_spare_mode_0_endbit 0 +#define rx_pl_data_dac_spare_mode_0_shift 15 +#define rx_pl_data_dac_spare_mode_0_mask 0x8000 + + +#define rx_pl_data_dac_spare_mode_1_addr 0b000000000 +#define rx_pl_data_dac_spare_mode_1_startbit 1 +#define rx_pl_data_dac_spare_mode_1_width 1 +#define rx_pl_data_dac_spare_mode_1_endbit 1 +#define rx_pl_data_dac_spare_mode_1_shift 14 +#define rx_pl_data_dac_spare_mode_1_mask 0x4000 + + +#define rx_pl_data_dac_spare_mode_2_addr 0b000000000 +#define rx_pl_data_dac_spare_mode_2_startbit 2 +#define rx_pl_data_dac_spare_mode_2_width 1 +#define rx_pl_data_dac_spare_mode_2_endbit 2 +#define rx_pl_data_dac_spare_mode_2_shift 13 +#define rx_pl_data_dac_spare_mode_2_mask 0x2000 + + +#define rx_pl_data_dac_spare_mode_3_addr 0b000000000 +#define rx_pl_data_dac_spare_mode_3_startbit 3 +#define rx_pl_data_dac_spare_mode_3_width 1 +#define rx_pl_data_dac_spare_mode_3_endbit 3 +#define rx_pl_data_dac_spare_mode_3_shift 12 +#define rx_pl_data_dac_spare_mode_3_mask 0x1000 + + +#define rx_pl_data_dac_spare_mode_4_addr 0b000000000 +#define rx_pl_data_dac_spare_mode_4_startbit 4 +#define rx_pl_data_dac_spare_mode_4_width 1 +#define rx_pl_data_dac_spare_mode_4_endbit 4 +#define rx_pl_data_dac_spare_mode_4_shift 11 +#define rx_pl_data_dac_spare_mode_4_mask 0x800 + + +#define rx_pl_data_dac_spare_mode_5_addr 0b000000000 +#define rx_pl_data_dac_spare_mode_5_startbit 5 +#define rx_pl_data_dac_spare_mode_5_width 1 +#define rx_pl_data_dac_spare_mode_5_endbit 5 +#define rx_pl_data_dac_spare_mode_5_shift 10 +#define rx_pl_data_dac_spare_mode_5_mask 0x400 + + +#define rx_pl_data_dac_spare_mode_6_addr 0b000000000 +#define rx_pl_data_dac_spare_mode_6_startbit 6 +#define rx_pl_data_dac_spare_mode_6_width 1 +#define rx_pl_data_dac_spare_mode_6_endbit 6 +#define rx_pl_data_dac_spare_mode_6_shift 9 +#define rx_pl_data_dac_spare_mode_6_mask 0x200 + + +#define rx_pl_data_dac_spare_mode_7_addr 0b000000000 +#define rx_pl_data_dac_spare_mode_7_startbit 7 +#define rx_pl_data_dac_spare_mode_7_width 1 +#define rx_pl_data_dac_spare_mode_7_endbit 7 +#define rx_pl_data_dac_spare_mode_7_shift 8 +#define rx_pl_data_dac_spare_mode_7_mask 0x100 + + +#define rx_pl_data_work_spare_mode_0_addr 0b001110000 +#define rx_pl_data_work_spare_mode_0_startbit 0 +#define rx_pl_data_work_spare_mode_0_width 1 +#define rx_pl_data_work_spare_mode_0_endbit 0 +#define rx_pl_data_work_spare_mode_0_shift 15 +#define rx_pl_data_work_spare_mode_0_mask 0x8000 + + +#define rx_pl_data_work_spare_mode_1_addr 0b001110000 +#define rx_pl_data_work_spare_mode_1_startbit 1 +#define rx_pl_data_work_spare_mode_1_width 1 +#define rx_pl_data_work_spare_mode_1_endbit 1 +#define rx_pl_data_work_spare_mode_1_shift 14 +#define rx_pl_data_work_spare_mode_1_mask 0x4000 + + +#define rx_pl_data_work_spare_mode_2_addr 0b001110000 +#define rx_pl_data_work_spare_mode_2_startbit 2 +#define rx_pl_data_work_spare_mode_2_width 1 +#define rx_pl_data_work_spare_mode_2_endbit 2 +#define rx_pl_data_work_spare_mode_2_shift 13 +#define rx_pl_data_work_spare_mode_2_mask 0x2000 + + +#define rx_pl_data_work_spare_mode_3_addr 0b001110000 +#define rx_pl_data_work_spare_mode_3_startbit 3 +#define rx_pl_data_work_spare_mode_3_width 1 +#define rx_pl_data_work_spare_mode_3_endbit 3 +#define rx_pl_data_work_spare_mode_3_shift 12 +#define rx_pl_data_work_spare_mode_3_mask 0x1000 + + +#define rx_pl_data_work_spare_mode_4_addr 0b001110000 +#define rx_pl_data_work_spare_mode_4_startbit 4 +#define rx_pl_data_work_spare_mode_4_width 1 +#define rx_pl_data_work_spare_mode_4_endbit 4 +#define rx_pl_data_work_spare_mode_4_shift 11 +#define rx_pl_data_work_spare_mode_4_mask 0x800 + + +#define rx_pl_data_work_spare_mode_5_addr 0b001110000 +#define rx_pl_data_work_spare_mode_5_startbit 5 +#define rx_pl_data_work_spare_mode_5_width 1 +#define rx_pl_data_work_spare_mode_5_endbit 5 +#define rx_pl_data_work_spare_mode_5_shift 10 +#define rx_pl_data_work_spare_mode_5_mask 0x400 + + +#define rx_pl_data_work_spare_mode_6_addr 0b001110000 +#define rx_pl_data_work_spare_mode_6_startbit 6 +#define rx_pl_data_work_spare_mode_6_width 1 +#define rx_pl_data_work_spare_mode_6_endbit 6 +#define rx_pl_data_work_spare_mode_6_shift 9 +#define rx_pl_data_work_spare_mode_6_mask 0x200 + + +#define rx_pl_data_work_spare_mode_7_addr 0b001110000 +#define rx_pl_data_work_spare_mode_7_startbit 7 +#define rx_pl_data_work_spare_mode_7_width 1 +#define rx_pl_data_work_spare_mode_7_endbit 7 +#define rx_pl_data_work_spare_mode_7_shift 8 +#define rx_pl_data_work_spare_mode_7_mask 0x100 + + +#define rx_pl_fir_err_addr 0b101010001 +#define rx_pl_fir_err_startbit 14 +#define rx_pl_fir_err_width 1 +#define rx_pl_fir_err_endbit 14 +#define rx_pl_fir_err_shift 1 +#define rx_pl_fir_err_mask 0x2 + + +#define rx_pl_fir_err_inj_addr 0b001000011 +#define rx_pl_fir_err_inj_startbit 0 +#define rx_pl_fir_err_inj_width 3 +#define rx_pl_fir_err_inj_endbit 2 +#define rx_pl_fir_err_inj_shift 13 +#define rx_pl_fir_err_inj_mask 0xe000 + + +#define rx_pl_fir_errs_addr 0b001000001 +#define rx_pl_fir_errs_startbit 0 +#define rx_pl_fir_errs_width 3 +#define rx_pl_fir_errs_endbit 2 +#define rx_pl_fir_errs_shift 13 +#define rx_pl_fir_errs_mask 0xe000 + + +#define rx_pl_fir_errs_mask_addr 0b001000010 +#define rx_pl_fir_errs_mask_startbit 0 +#define rx_pl_fir_errs_mask_width 3 +#define rx_pl_fir_errs_mask_endbit 2 +#define rx_pl_fir_errs_mask_shift 13 +#define rx_pl_fir_errs_mask_mask 0xe000 + + +#define rx_pl_spare_mode_0_addr 0b001000000 +#define rx_pl_spare_mode_0_startbit 0 +#define rx_pl_spare_mode_0_width 1 +#define rx_pl_spare_mode_0_endbit 0 +#define rx_pl_spare_mode_0_shift 15 +#define rx_pl_spare_mode_0_mask 0x8000 + + +#define rx_pl_spare_mode_1_addr 0b001000000 +#define rx_pl_spare_mode_1_startbit 1 +#define rx_pl_spare_mode_1_width 1 +#define rx_pl_spare_mode_1_endbit 1 +#define rx_pl_spare_mode_1_shift 14 +#define rx_pl_spare_mode_1_mask 0x4000 + + +#define rx_pl_spare_mode_2_addr 0b001000000 +#define rx_pl_spare_mode_2_startbit 2 +#define rx_pl_spare_mode_2_width 1 +#define rx_pl_spare_mode_2_endbit 2 +#define rx_pl_spare_mode_2_shift 13 +#define rx_pl_spare_mode_2_mask 0x2000 + + +#define rx_pl_spare_mode_3_addr 0b001000000 +#define rx_pl_spare_mode_3_startbit 3 +#define rx_pl_spare_mode_3_width 1 +#define rx_pl_spare_mode_3_endbit 3 +#define rx_pl_spare_mode_3_shift 12 +#define rx_pl_spare_mode_3_mask 0x1000 + + +#define rx_pl_spare_mode_4_addr 0b001000000 +#define rx_pl_spare_mode_4_startbit 4 +#define rx_pl_spare_mode_4_width 1 +#define rx_pl_spare_mode_4_endbit 4 +#define rx_pl_spare_mode_4_shift 11 +#define rx_pl_spare_mode_4_mask 0x800 + + +#define rx_pl_spare_mode_5_addr 0b001000000 +#define rx_pl_spare_mode_5_startbit 5 +#define rx_pl_spare_mode_5_width 1 +#define rx_pl_spare_mode_5_endbit 5 +#define rx_pl_spare_mode_5_shift 10 +#define rx_pl_spare_mode_5_mask 0x400 + + +#define rx_pl_spare_mode_6_addr 0b001000000 +#define rx_pl_spare_mode_6_startbit 6 +#define rx_pl_spare_mode_6_width 1 +#define rx_pl_spare_mode_6_endbit 6 +#define rx_pl_spare_mode_6_shift 9 +#define rx_pl_spare_mode_6_mask 0x200 + + +#define rx_pl_spare_mode_7_addr 0b001000000 +#define rx_pl_spare_mode_7_startbit 7 +#define rx_pl_spare_mode_7_width 1 +#define rx_pl_spare_mode_7_endbit 7 +#define rx_pl_spare_mode_7_shift 8 +#define rx_pl_spare_mode_7_mask 0x100 + + +#define rx_polling_timeout_sel_addr 0b100001000 +#define rx_polling_timeout_sel_startbit 4 +#define rx_polling_timeout_sel_width 4 +#define rx_polling_timeout_sel_endbit 7 +#define rx_polling_timeout_sel_shift 8 +#define rx_polling_timeout_sel_mask 0xf00 + + +#define rx_pr_bit_lock_done_addr 0b001001010 +#define rx_pr_bit_lock_done_startbit 12 +#define rx_pr_bit_lock_done_width 1 +#define rx_pr_bit_lock_done_endbit 12 +#define rx_pr_bit_lock_done_shift 3 +#define rx_pr_bit_lock_done_mask 0x8 + + +#define rx_pr_bump_sl_1step_addr 0b001001100 +#define rx_pr_bump_sl_1step_startbit 0 +#define rx_pr_bump_sl_1step_width 1 +#define rx_pr_bump_sl_1step_endbit 0 +#define rx_pr_bump_sl_1step_shift 15 +#define rx_pr_bump_sl_1step_mask 0x8000 + + +#define rx_pr_bump_sl_1ui_addr 0b001001001 +#define rx_pr_bump_sl_1ui_startbit 9 +#define rx_pr_bump_sl_1ui_width 1 +#define rx_pr_bump_sl_1ui_endbit 9 +#define rx_pr_bump_sl_1ui_shift 6 +#define rx_pr_bump_sl_1ui_mask 0x40 + + +#define rx_pr_bump_sl_1ui_done_addr 0b001001110 +#define rx_pr_bump_sl_1ui_done_startbit 8 +#define rx_pr_bump_sl_1ui_done_width 1 +#define rx_pr_bump_sl_1ui_done_endbit 8 +#define rx_pr_bump_sl_1ui_done_shift 7 +#define rx_pr_bump_sl_1ui_done_mask 0x80 + + +#define rx_pr_bump_sr_1step_addr 0b001001100 +#define rx_pr_bump_sr_1step_startbit 1 +#define rx_pr_bump_sr_1step_width 1 +#define rx_pr_bump_sr_1step_endbit 1 +#define rx_pr_bump_sr_1step_shift 14 +#define rx_pr_bump_sr_1step_mask 0x4000 + + +#define rx_pr_bump_sr_1ui_addr 0b001001001 +#define rx_pr_bump_sr_1ui_startbit 10 +#define rx_pr_bump_sr_1ui_width 1 +#define rx_pr_bump_sr_1ui_endbit 10 +#define rx_pr_bump_sr_1ui_shift 5 +#define rx_pr_bump_sr_1ui_mask 0x20 + + +#define rx_pr_bump_sr_1ui_done_addr 0b001001110 +#define rx_pr_bump_sr_1ui_done_startbit 9 +#define rx_pr_bump_sr_1ui_done_width 1 +#define rx_pr_bump_sr_1ui_done_endbit 9 +#define rx_pr_bump_sr_1ui_done_shift 6 +#define rx_pr_bump_sr_1ui_done_mask 0x40 + + +#define rx_pr_bump_to_edge_a_addr 0b001001001 +#define rx_pr_bump_to_edge_a_startbit 7 +#define rx_pr_bump_to_edge_a_width 1 +#define rx_pr_bump_to_edge_a_endbit 7 +#define rx_pr_bump_to_edge_a_shift 8 +#define rx_pr_bump_to_edge_a_mask 0x100 + + +#define rx_pr_data_a_offset_addr 0b001001010 +#define rx_pr_data_a_offset_startbit 0 +#define rx_pr_data_a_offset_width 6 +#define rx_pr_data_a_offset_endbit 5 +#define rx_pr_data_a_offset_shift 10 +#define rx_pr_data_a_offset_mask 0xfc00 + + +#define rx_pr_data_offset_disable_a_addr 0b001001001 +#define rx_pr_data_offset_disable_a_startbit 11 +#define rx_pr_data_offset_disable_a_width 1 +#define rx_pr_data_offset_disable_a_endbit 11 +#define rx_pr_data_offset_disable_a_shift 4 +#define rx_pr_data_offset_disable_a_mask 0x10 + + +#define rx_pr_ddc_a_addr 0b001001001 +#define rx_pr_ddc_a_startbit 5 +#define rx_pr_ddc_a_width 1 +#define rx_pr_ddc_a_endbit 5 +#define rx_pr_ddc_a_shift 10 +#define rx_pr_ddc_a_mask 0x400 + + +#define rx_pr_ddc_done_addr 0b001001110 +#define rx_pr_ddc_done_startbit 5 +#define rx_pr_ddc_done_width 1 +#define rx_pr_ddc_done_endbit 5 +#define rx_pr_ddc_done_shift 10 +#define rx_pr_ddc_done_mask 0x400 + + +#define rx_pr_ddc_failed_addr 0b001001110 +#define rx_pr_ddc_failed_startbit 6 +#define rx_pr_ddc_failed_width 1 +#define rx_pr_ddc_failed_endbit 6 +#define rx_pr_ddc_failed_shift 9 +#define rx_pr_ddc_failed_mask 0x200 + + +#define rx_pr_edge_track_cntl_addr 0b001001001 +#define rx_pr_edge_track_cntl_startbit 0 +#define rx_pr_edge_track_cntl_width 2 +#define rx_pr_edge_track_cntl_endbit 1 +#define rx_pr_edge_track_cntl_shift 14 +#define rx_pr_edge_track_cntl_mask 0xc000 + + +#define rx_pr_invalid_lock_bump_size_addr 0b001001010 +#define rx_pr_invalid_lock_bump_size_startbit 14 +#define rx_pr_invalid_lock_bump_size_width 2 +#define rx_pr_invalid_lock_bump_size_endbit 15 +#define rx_pr_invalid_lock_bump_size_shift 0 +#define rx_pr_invalid_lock_bump_size_mask 0x3 + + +#define rx_pr_invalid_lock_filter_en_addr 0b001001010 +#define rx_pr_invalid_lock_filter_en_startbit 13 +#define rx_pr_invalid_lock_filter_en_width 1 +#define rx_pr_invalid_lock_filter_en_endbit 13 +#define rx_pr_invalid_lock_filter_en_shift 2 +#define rx_pr_invalid_lock_filter_en_mask 0x4 + + +#define rx_pr_left_edge_a_addr 0b001001111 +#define rx_pr_left_edge_a_startbit 0 +#define rx_pr_left_edge_a_width 6 +#define rx_pr_left_edge_a_endbit 5 +#define rx_pr_left_edge_a_shift 10 +#define rx_pr_left_edge_a_mask 0xfc00 + + +#define rx_pr_phase_step_addr 0b001000101 +#define rx_pr_phase_step_startbit 12 +#define rx_pr_phase_step_width 4 +#define rx_pr_phase_step_endbit 15 +#define rx_pr_phase_step_shift 0 +#define rx_pr_phase_step_mask 0xf + + +#define rx_pr_right_edge_a_addr 0b001001111 +#define rx_pr_right_edge_a_startbit 6 +#define rx_pr_right_edge_a_width 6 +#define rx_pr_right_edge_a_endbit 11 +#define rx_pr_right_edge_a_shift 4 +#define rx_pr_right_edge_a_mask 0x3f0 + + +#define rx_pr_trace_ddc_sm_addr 0b001001011 +#define rx_pr_trace_ddc_sm_startbit 1 +#define rx_pr_trace_ddc_sm_width 5 +#define rx_pr_trace_ddc_sm_endbit 5 +#define rx_pr_trace_ddc_sm_shift 10 +#define rx_pr_trace_ddc_sm_mask 0x7c00 + + +#define rx_pr_trace_ddc_stop_addr 0b001001011 +#define rx_pr_trace_ddc_stop_startbit 0 +#define rx_pr_trace_ddc_stop_width 1 +#define rx_pr_trace_ddc_stop_endbit 0 +#define rx_pr_trace_ddc_stop_shift 15 +#define rx_pr_trace_ddc_stop_mask 0x8000 + + +#define rx_pr_trace_stopped_addr 0b001001110 +#define rx_pr_trace_stopped_startbit 10 +#define rx_pr_trace_stopped_width 1 +#define rx_pr_trace_stopped_endbit 10 +#define rx_pr_trace_stopped_shift 5 +#define rx_pr_trace_stopped_mask 0x20 + + +#define rx_pr_trace_wobble_sm_addr 0b001001011 +#define rx_pr_trace_wobble_sm_startbit 7 +#define rx_pr_trace_wobble_sm_width 3 +#define rx_pr_trace_wobble_sm_endbit 9 +#define rx_pr_trace_wobble_sm_shift 6 +#define rx_pr_trace_wobble_sm_mask 0x1c0 + + +#define rx_pr_trace_wobble_stop_addr 0b001001011 +#define rx_pr_trace_wobble_stop_startbit 6 +#define rx_pr_trace_wobble_stop_width 1 +#define rx_pr_trace_wobble_stop_endbit 6 +#define rx_pr_trace_wobble_stop_shift 9 +#define rx_pr_trace_wobble_stop_mask 0x200 + + +#define rx_pr_use_dfe_clock_a_addr 0b001001001 +#define rx_pr_use_dfe_clock_a_startbit 13 +#define rx_pr_use_dfe_clock_a_width 1 +#define rx_pr_use_dfe_clock_a_endbit 13 +#define rx_pr_use_dfe_clock_a_shift 2 +#define rx_pr_use_dfe_clock_a_mask 0x4 + + +#define rx_pr_wobble_a_addr 0b001001001 +#define rx_pr_wobble_a_startbit 2 +#define rx_pr_wobble_a_width 1 +#define rx_pr_wobble_a_endbit 2 +#define rx_pr_wobble_a_shift 13 +#define rx_pr_wobble_a_mask 0x2000 + + +#define rx_pr_wobble_a_ip_addr 0b001001110 +#define rx_pr_wobble_a_ip_startbit 2 +#define rx_pr_wobble_a_ip_width 1 +#define rx_pr_wobble_a_ip_endbit 2 +#define rx_pr_wobble_a_ip_shift 13 +#define rx_pr_wobble_a_ip_mask 0x2000 + + +#define rx_prbs_test_data_addr 0b000000001 +#define rx_prbs_test_data_startbit 7 +#define rx_prbs_test_data_width 3 +#define rx_prbs_test_data_endbit 9 +#define rx_prbs_test_data_shift 6 +#define rx_prbs_test_data_mask 0x1c0 + + +#define rx_prvcpt_change_det_addr 0b101111000 +#define rx_prvcpt_change_det_startbit 15 +#define rx_prvcpt_change_det_width 1 +#define rx_prvcpt_change_det_endbit 15 +#define rx_prvcpt_change_det_shift 0 +#define rx_prvcpt_change_det_mask 0x1 + + +#define rx_psave_mode_active_addr 0b001001101 +#define rx_psave_mode_active_startbit 8 +#define rx_psave_mode_active_width 1 +#define rx_psave_mode_active_endbit 8 +#define rx_psave_mode_active_shift 7 +#define rx_psave_mode_active_mask 0x80 + + +#define rx_rc_enable_VGA_amax_mode_addr 0b100101110 +#define rx_rc_enable_VGA_amax_mode_startbit 2 +#define rx_rc_enable_VGA_amax_mode_width 1 +#define rx_rc_enable_VGA_amax_mode_endbit 2 +#define rx_rc_enable_VGA_amax_mode_shift 13 +#define rx_rc_enable_VGA_amax_mode_mask 0x2000 + + +#define rx_rc_enable_cm_coarse_cal_addr 0b100010111 +#define rx_rc_enable_cm_coarse_cal_startbit 7 +#define rx_rc_enable_cm_coarse_cal_width 1 +#define rx_rc_enable_cm_coarse_cal_endbit 7 +#define rx_rc_enable_cm_coarse_cal_shift 8 +#define rx_rc_enable_cm_coarse_cal_mask 0x100 + + +#define rx_rc_enable_cm_fine_cal_addr 0b100010111 +#define rx_rc_enable_cm_fine_cal_startbit 8 +#define rx_rc_enable_cm_fine_cal_width 1 +#define rx_rc_enable_cm_fine_cal_endbit 8 +#define rx_rc_enable_cm_fine_cal_shift 7 +#define rx_rc_enable_cm_fine_cal_mask 0x80 + + +#define rx_rc_enable_ctle_1st_latch_offset_cal_addr 0b100101110 +#define rx_rc_enable_ctle_1st_latch_offset_cal_startbit 0 +#define rx_rc_enable_ctle_1st_latch_offset_cal_width 1 +#define rx_rc_enable_ctle_1st_latch_offset_cal_endbit 0 +#define rx_rc_enable_ctle_1st_latch_offset_cal_shift 15 +#define rx_rc_enable_ctle_1st_latch_offset_cal_mask 0x8000 + + +#define rx_rc_enable_ctle_2nd_latch_offset_cal_addr 0b100101110 +#define rx_rc_enable_ctle_2nd_latch_offset_cal_startbit 1 +#define rx_rc_enable_ctle_2nd_latch_offset_cal_width 1 +#define rx_rc_enable_ctle_2nd_latch_offset_cal_endbit 1 +#define rx_rc_enable_ctle_2nd_latch_offset_cal_shift 14 +#define rx_rc_enable_ctle_2nd_latch_offset_cal_mask 0x4000 + + +#define rx_rc_enable_ctle_coarse_cal_addr 0b100010111 +#define rx_rc_enable_ctle_coarse_cal_startbit 1 +#define rx_rc_enable_ctle_coarse_cal_width 1 +#define rx_rc_enable_ctle_coarse_cal_endbit 1 +#define rx_rc_enable_ctle_coarse_cal_shift 14 +#define rx_rc_enable_ctle_coarse_cal_mask 0x4000 + + +#define rx_rc_enable_dac_h1_cal_addr 0b100010111 +#define rx_rc_enable_dac_h1_cal_startbit 2 +#define rx_rc_enable_dac_h1_cal_width 1 +#define rx_rc_enable_dac_h1_cal_endbit 2 +#define rx_rc_enable_dac_h1_cal_shift 13 +#define rx_rc_enable_dac_h1_cal_mask 0x2000 + + +#define rx_rc_enable_ddc_addr 0b100010111 +#define rx_rc_enable_ddc_startbit 6 +#define rx_rc_enable_ddc_width 1 +#define rx_rc_enable_ddc_endbit 6 +#define rx_rc_enable_ddc_shift 9 +#define rx_rc_enable_ddc_mask 0x200 + + +#define rx_rc_enable_dfe_h1_cal_addr 0b100010111 +#define rx_rc_enable_dfe_h1_cal_startbit 4 +#define rx_rc_enable_dfe_h1_cal_width 1 +#define rx_rc_enable_dfe_h1_cal_endbit 4 +#define rx_rc_enable_dfe_h1_cal_shift 11 +#define rx_rc_enable_dfe_h1_cal_mask 0x800 + + +#define rx_rc_enable_h1ap_tweak_addr 0b100010111 +#define rx_rc_enable_h1ap_tweak_startbit 5 +#define rx_rc_enable_h1ap_tweak_width 1 +#define rx_rc_enable_h1ap_tweak_endbit 5 +#define rx_rc_enable_h1ap_tweak_shift 10 +#define rx_rc_enable_h1ap_tweak_mask 0x400 + + +#define rx_rc_enable_integ_latch_offset_cal_addr 0b100010111 +#define rx_rc_enable_integ_latch_offset_cal_startbit 0 +#define rx_rc_enable_integ_latch_offset_cal_width 1 +#define rx_rc_enable_integ_latch_offset_cal_endbit 0 +#define rx_rc_enable_integ_latch_offset_cal_shift 15 +#define rx_rc_enable_integ_latch_offset_cal_mask 0x8000 + + +#define rx_rc_enable_vga_cal_addr 0b100010111 +#define rx_rc_enable_vga_cal_startbit 3 +#define rx_rc_enable_vga_cal_width 1 +#define rx_rc_enable_vga_cal_endbit 3 +#define rx_rc_enable_vga_cal_shift 12 +#define rx_rc_enable_vga_cal_mask 0x1000 + + +#define rx_recal_cnt_addr 0b101011000 +#define rx_recal_cnt_startbit 0 +#define rx_recal_cnt_width 16 +#define rx_recal_cnt_endbit 15 +#define rx_recal_cnt_shift 0 +#define rx_recal_cnt_mask 0xffff + + +#define rx_recal_lane_to_monitor_addr 0b101011100 +#define rx_recal_lane_to_monitor_startbit 2 +#define rx_recal_lane_to_monitor_width 5 +#define rx_recal_lane_to_monitor_endbit 6 +#define rx_recal_lane_to_monitor_shift 9 +#define rx_recal_lane_to_monitor_mask 0x3e00 + + +#define rx_reset_servo_status_addr 0b101110001 +#define rx_reset_servo_status_startbit 5 +#define rx_reset_servo_status_width 1 +#define rx_reset_servo_status_endbit 5 +#define rx_reset_servo_status_shift 10 +#define rx_reset_servo_status_mask 0x400 + + +#define rx_scan_n_0_15_addr 0b101111100 +#define rx_scan_n_0_15_startbit 0 +#define rx_scan_n_0_15_width 16 +#define rx_scan_n_0_15_endbit 15 +#define rx_scan_n_0_15_shift 0 +#define rx_scan_n_0_15_mask 0xffff + + +#define rx_scan_n_16_23_addr 0b101111011 +#define rx_scan_n_16_23_startbit 8 +#define rx_scan_n_16_23_width 8 +#define rx_scan_n_16_23_endbit 15 +#define rx_scan_n_16_23_shift 0 +#define rx_scan_n_16_23_mask 0xff + + +#define rx_scan_p_0_15_addr 0b101111001 +#define rx_scan_p_0_15_startbit 0 +#define rx_scan_p_0_15_width 16 +#define rx_scan_p_0_15_endbit 15 +#define rx_scan_p_0_15_shift 0 +#define rx_scan_p_0_15_mask 0xffff + + +#define rx_scan_p_16_23_addr 0b101111010 +#define rx_scan_p_16_23_startbit 0 +#define rx_scan_p_16_23_width 9 +#define rx_scan_p_16_23_endbit 8 +#define rx_scan_p_16_23_shift 7 +#define rx_scan_p_16_23_mask 0xff80 + + +#define rx_scope_capture_addr 0b101110001 +#define rx_scope_capture_startbit 3 +#define rx_scope_capture_width 1 +#define rx_scope_capture_endbit 3 +#define rx_scope_capture_shift 12 +#define rx_scope_capture_mask 0x1000 + + +#define rx_scope_control_addr 0b100000011 +#define rx_scope_control_startbit 2 +#define rx_scope_control_width 4 +#define rx_scope_control_endbit 5 +#define rx_scope_control_shift 10 +#define rx_scope_control_mask 0x3c00 + + +#define rx_servo_chg_cfg_addr 0b100001101 +#define rx_servo_chg_cfg_startbit 0 +#define rx_servo_chg_cfg_width 4 +#define rx_servo_chg_cfg_endbit 3 +#define rx_servo_chg_cfg_shift 12 +#define rx_servo_chg_cfg_mask 0xf000 + + +#define rx_servo_chg_cnt_addr 0b101111000 +#define rx_servo_chg_cnt_startbit 0 +#define rx_servo_chg_cnt_width 4 +#define rx_servo_chg_cnt_endbit 3 +#define rx_servo_chg_cnt_shift 12 +#define rx_servo_chg_cnt_mask 0xf000 + + +#define rx_servo_config_addr 0b101110000 +#define rx_servo_config_startbit 8 +#define rx_servo_config_width 4 +#define rx_servo_config_endbit 11 +#define rx_servo_config_shift 4 +#define rx_servo_config_mask 0xf0 + + +#define rx_servo_done_addr 0b100100010 +#define rx_servo_done_startbit 15 +#define rx_servo_done_width 1 +#define rx_servo_done_endbit 15 +#define rx_servo_done_shift 0 +#define rx_servo_done_mask 0x1 + + +#define rx_servo_op_addr 0b100100010 +#define rx_servo_op_startbit 0 +#define rx_servo_op_width 15 +#define rx_servo_op_endbit 14 +#define rx_servo_op_shift 1 +#define rx_servo_op_mask 0xfffe + + +#define rx_servo_result_addr 0b100101010 +#define rx_servo_result_startbit 0 +#define rx_servo_result_width 8 +#define rx_servo_result_endbit 7 +#define rx_servo_result_shift 8 +#define rx_servo_result_mask 0xff00 + + +#define rx_servo_status_addr 0b101110111 +#define rx_servo_status_startbit 0 +#define rx_servo_status_width 16 +#define rx_servo_status_endbit 15 +#define rx_servo_status_shift 0 +#define rx_servo_status_mask 0xffff + + +#define rx_servo_thresh1_addr 0b100001110 +#define rx_servo_thresh1_startbit 8 +#define rx_servo_thresh1_width 4 +#define rx_servo_thresh1_endbit 11 +#define rx_servo_thresh1_shift 4 +#define rx_servo_thresh1_mask 0xf0 + + +#define rx_servo_thresh2_addr 0b100001110 +#define rx_servo_thresh2_startbit 12 +#define rx_servo_thresh2_width 4 +#define rx_servo_thresh2_endbit 15 +#define rx_servo_thresh2_shift 0 +#define rx_servo_thresh2_mask 0xf + + +#define rx_spare4_timeout_addr 0b100010001 +#define rx_spare4_timeout_startbit 12 +#define rx_spare4_timeout_width 4 +#define rx_spare4_timeout_endbit 15 +#define rx_spare4_timeout_shift 0 +#define rx_spare4_timeout_mask 0xf + + +#define rx_tracking_timeout_sel_addr 0b100000110 +#define rx_tracking_timeout_sel_startbit 8 +#define rx_tracking_timeout_sel_width 4 +#define rx_tracking_timeout_sel_endbit 11 +#define rx_tracking_timeout_sel_shift 4 +#define rx_tracking_timeout_sel_mask 0xf0 + + +#define rx_trc_mode_addr 0b100011100 +#define rx_trc_mode_startbit 0 +#define rx_trc_mode_width 4 +#define rx_trc_mode_endbit 3 +#define rx_trc_mode_shift 12 +#define rx_trc_mode_mask 0xf000 + + +#define rx_user_filter_mask_addr 0b100011001 +#define rx_user_filter_mask_startbit 8 +#define rx_user_filter_mask_width 8 +#define rx_user_filter_mask_endbit 15 +#define rx_user_filter_mask_shift 0 +#define rx_user_filter_mask_mask 0xff + + +#define rx_userdef_cfg_addr 0b100001100 +#define rx_userdef_cfg_startbit 12 +#define rx_userdef_cfg_width 4 +#define rx_userdef_cfg_endbit 15 +#define rx_userdef_cfg_shift 0 +#define rx_userdef_cfg_mask 0xf + + +#define rx_userdef_timeout_addr 0b100010001 +#define rx_userdef_timeout_startbit 4 +#define rx_userdef_timeout_width 4 +#define rx_userdef_timeout_endbit 7 +#define rx_userdef_timeout_shift 8 +#define rx_userdef_timeout_mask 0xf00 + + +#define rx_voff_cfg_addr 0b100001101 +#define rx_voff_cfg_startbit 12 +#define rx_voff_cfg_width 3 +#define rx_voff_cfg_endbit 14 +#define rx_voff_cfg_shift 1 +#define rx_voff_cfg_mask 0xe + + +#define scom_mode_pb_spares1_addr 0b000100000 +#define scom_mode_pb_spares1_startbit 4 +#define scom_mode_pb_spares1_width 4 +#define scom_mode_pb_spares1_endbit 7 +#define scom_mode_pb_spares1_shift 8 +#define scom_mode_pb_spares1_mask 0xf00 + + +#define scom_mode_pb_spares2_addr 0b000100000 +#define scom_mode_pb_spares2_startbit 23 +#define scom_mode_pb_spares2_width 8 +#define scom_mode_pb_spares2_endbit 30 +#define scom_mode_pb_spares2_shift -15 +#define scom_mode_pb_spares2_mask 0x1fe000000000000 + + +#define scom_ppe_arb_ecc_inject_err_addr 0b000100000 +#define scom_ppe_arb_ecc_inject_err_startbit 3 +#define scom_ppe_arb_ecc_inject_err_width 1 +#define scom_ppe_arb_ecc_inject_err_endbit 3 +#define scom_ppe_arb_ecc_inject_err_shift 12 +#define scom_ppe_arb_ecc_inject_err_mask 0x1000 + + +#define scom_ppe_flags_addr 0b000100011 +#define scom_ppe_flags_startbit 0 +#define scom_ppe_flags_width 16 +#define scom_ppe_flags_endbit 15 +#define scom_ppe_flags_shift 0 +#define scom_ppe_flags_mask 0xffff + + +#define scom_ppe_flags_clr_addr 0b000100101 +#define scom_ppe_flags_clr_startbit 0 +#define scom_ppe_flags_clr_width 16 +#define scom_ppe_flags_clr_endbit 15 +#define scom_ppe_flags_clr_shift 0 +#define scom_ppe_flags_clr_mask 0xffff + + +#define scom_ppe_flags_set_addr 0b000100100 +#define scom_ppe_flags_set_startbit 0 +#define scom_ppe_flags_set_width 16 +#define scom_ppe_flags_set_endbit 15 +#define scom_ppe_flags_set_shift 0 +#define scom_ppe_flags_set_mask 0xffff + + +#define scom_ppe_interrupt_addr 0b000100000 +#define scom_ppe_interrupt_startbit 2 +#define scom_ppe_interrupt_width 1 +#define scom_ppe_interrupt_endbit 2 +#define scom_ppe_interrupt_shift 13 +#define scom_ppe_interrupt_mask 0x2000 + + +#define scom_ppe_ioreset_addr 0b000100000 +#define scom_ppe_ioreset_startbit 0 +#define scom_ppe_ioreset_width 1 +#define scom_ppe_ioreset_endbit 0 +#define scom_ppe_ioreset_shift 15 +#define scom_ppe_ioreset_mask 0x8000 + + +#define scom_ppe_ir_edr_0_63_addr 0b000010100 +#define scom_ppe_ir_edr_0_63_startbit 0 +#define scom_ppe_ir_edr_0_63_width 64 +#define scom_ppe_ir_edr_0_63_endbit 63 +#define scom_ppe_ir_edr_0_63_shift -48 +#define scom_ppe_ir_edr_0_63_mask 0xffffffffffff0000 + + +#define scom_ppe_ir_sprg0_0_63_addr 0b000010010 +#define scom_ppe_ir_sprg0_0_63_startbit 0 +#define scom_ppe_ir_sprg0_0_63_width 64 +#define scom_ppe_ir_sprg0_0_63_endbit 63 +#define scom_ppe_ir_sprg0_0_63_shift -48 +#define scom_ppe_ir_sprg0_0_63_mask 0xffffffffffff0000 + + +#define scom_ppe_mem_arb_csar_0_63_addr 0b000001101 +#define scom_ppe_mem_arb_csar_0_63_startbit 0 +#define scom_ppe_mem_arb_csar_0_63_width 64 +#define scom_ppe_mem_arb_csar_0_63_endbit 63 +#define scom_ppe_mem_arb_csar_0_63_shift -48 +#define scom_ppe_mem_arb_csar_0_63_mask 0xffffffffffff0000 + + +#define scom_ppe_mem_arb_csdr_0_63_addr 0b000001110 +#define scom_ppe_mem_arb_csdr_0_63_startbit 0 +#define scom_ppe_mem_arb_csdr_0_63_width 64 +#define scom_ppe_mem_arb_csdr_0_63_endbit 63 +#define scom_ppe_mem_arb_csdr_0_63_shift -48 +#define scom_ppe_mem_arb_csdr_0_63_mask 0xffffffffffff0000 + + +#define scom_ppe_mem_arb_scr_0_63_addr 0b000001010 +#define scom_ppe_mem_arb_scr_0_63_startbit 0 +#define scom_ppe_mem_arb_scr_0_63_width 64 +#define scom_ppe_mem_arb_scr_0_63_endbit 63 +#define scom_ppe_mem_arb_scr_0_63_shift -48 +#define scom_ppe_mem_arb_scr_0_63_mask 0xffffffffffff0000 + + +#define scom_ppe_pdwn_addr 0b000100000 +#define scom_ppe_pdwn_startbit 1 +#define scom_ppe_pdwn_width 1 +#define scom_ppe_pdwn_endbit 1 +#define scom_ppe_pdwn_shift 14 +#define scom_ppe_pdwn_mask 0x4000 + + +#define scom_ppe_spares_addr 0b000100000 +#define scom_ppe_spares_startbit 4 +#define scom_ppe_spares_width 12 +#define scom_ppe_spares_endbit 15 +#define scom_ppe_spares_shift 0 +#define scom_ppe_spares_mask 0xfff + + +#define scom_ppe_work1_addr 0b000100001 +#define scom_ppe_work1_startbit 0 +#define scom_ppe_work1_width 32 +#define scom_ppe_work1_endbit 31 +#define scom_ppe_work1_shift -16 +#define scom_ppe_work1_mask 0xffff000000000000 + + +#define scom_ppe_work2_addr 0b000100010 +#define scom_ppe_work2_startbit 0 +#define scom_ppe_work2_width 32 +#define scom_ppe_work2_endbit 31 +#define scom_ppe_work2_shift -16 +#define scom_ppe_work2_mask 0xffff000000000000 + + +#define scom_ppe_xcr_none_0_63_addr 0b000010000 +#define scom_ppe_xcr_none_0_63_startbit 0 +#define scom_ppe_xcr_none_0_63_width 64 +#define scom_ppe_xcr_none_0_63_endbit 63 +#define scom_ppe_xcr_none_0_63_shift -48 +#define scom_ppe_xcr_none_0_63_mask 0xffffffffffff0000 + + +#define scom_ppe_xcr_sprg0_0_63_addr 0b000010001 +#define scom_ppe_xcr_sprg0_0_63_startbit 0 +#define scom_ppe_xcr_sprg0_0_63_width 64 +#define scom_ppe_xcr_sprg0_0_63_endbit 63 +#define scom_ppe_xcr_sprg0_0_63_shift -48 +#define scom_ppe_xcr_sprg0_0_63_mask 0xffffffffffff0000 + + +#define scom_ppe_xsr_iar_0_63_addr 0b000010101 +#define scom_ppe_xsr_iar_0_63_startbit 0 +#define scom_ppe_xsr_iar_0_63_width 64 +#define scom_ppe_xsr_iar_0_63_endbit 63 +#define scom_ppe_xsr_iar_0_63_shift -48 +#define scom_ppe_xsr_iar_0_63_mask 0xffffffffffff0000 + + +#define scom_ppe_xsr_sprg0_0_63_addr 0b000010011 +#define scom_ppe_xsr_sprg0_0_63_startbit 0 +#define scom_ppe_xsr_sprg0_0_63_width 64 +#define scom_ppe_xsr_sprg0_0_63_endbit 63 +#define scom_ppe_xsr_sprg0_0_63_shift -48 +#define scom_ppe_xsr_sprg0_0_63_mask 0xffffffffffff0000 + + +#define tx_bist_done_addr 0b110101101 +#define tx_bist_done_startbit 2 +#define tx_bist_done_width 1 +#define tx_bist_done_endbit 2 +#define tx_bist_done_shift 13 +#define tx_bist_done_mask 0x2000 + + +#define tx_bist_en_addr 0b110000010 +#define tx_bist_en_startbit 3 +#define tx_bist_en_width 1 +#define tx_bist_en_endbit 3 +#define tx_bist_en_shift 12 +#define tx_bist_en_mask 0x1000 + + +#define tx_bus_id_addr 0b110000001 +#define tx_bus_id_startbit 0 +#define tx_bus_id_width 6 +#define tx_bus_id_endbit 5 +#define tx_bus_id_shift 10 +#define tx_bus_id_mask 0xfc00 + + +#define tx_clr_par_errs_addr 0b110100010 +#define tx_clr_par_errs_startbit 14 +#define tx_clr_par_errs_width 1 +#define tx_clr_par_errs_endbit 14 +#define tx_clr_par_errs_shift 1 +#define tx_clr_par_errs_mask 0x2 + + +#define tx_clr_unload_clk_disable_addr 0b010000010 +#define tx_clr_unload_clk_disable_startbit 13 +#define tx_clr_unload_clk_disable_width 1 +#define tx_clr_unload_clk_disable_endbit 13 +#define tx_clr_unload_clk_disable_shift 2 +#define tx_clr_unload_clk_disable_mask 0x4 + + +#define tx_drv_data_pattern_gcrmsg_addr 0b110000100 +#define tx_drv_data_pattern_gcrmsg_startbit 2 +#define tx_drv_data_pattern_gcrmsg_width 4 +#define tx_drv_data_pattern_gcrmsg_endbit 5 +#define tx_drv_data_pattern_gcrmsg_shift 10 +#define tx_drv_data_pattern_gcrmsg_mask 0x3c00 + + +#define tx_err_inj_A_enable_addr 0b010000000 +#define tx_err_inj_A_enable_startbit 7 +#define tx_err_inj_A_enable_width 1 +#define tx_err_inj_A_enable_endbit 7 +#define tx_err_inj_A_enable_shift 8 +#define tx_err_inj_A_enable_mask 0x100 + + +#define tx_err_inj_B_enable_addr 0b010000000 +#define tx_err_inj_B_enable_startbit 8 +#define tx_err_inj_B_enable_width 1 +#define tx_err_inj_B_enable_endbit 8 +#define tx_err_inj_B_enable_shift 7 +#define tx_err_inj_B_enable_mask 0x80 + + +#define tx_err_inj_a_ber_sel_addr 0b110000101 +#define tx_err_inj_a_ber_sel_startbit 7 +#define tx_err_inj_a_ber_sel_width 6 +#define tx_err_inj_a_ber_sel_endbit 12 +#define tx_err_inj_a_ber_sel_shift 3 +#define tx_err_inj_a_ber_sel_mask 0x1f8 + + +#define tx_err_inj_a_coarse_sel_addr 0b110000101 +#define tx_err_inj_a_coarse_sel_startbit 3 +#define tx_err_inj_a_coarse_sel_width 4 +#define tx_err_inj_a_coarse_sel_endbit 6 +#define tx_err_inj_a_coarse_sel_shift 9 +#define tx_err_inj_a_coarse_sel_mask 0x1e00 + + +#define tx_err_inj_a_fine_sel_addr 0b110000101 +#define tx_err_inj_a_fine_sel_startbit 0 +#define tx_err_inj_a_fine_sel_width 3 +#define tx_err_inj_a_fine_sel_endbit 2 +#define tx_err_inj_a_fine_sel_shift 13 +#define tx_err_inj_a_fine_sel_mask 0xe000 + + +#define tx_err_inj_b_ber_sel_addr 0b110000110 +#define tx_err_inj_b_ber_sel_startbit 7 +#define tx_err_inj_b_ber_sel_width 6 +#define tx_err_inj_b_ber_sel_endbit 12 +#define tx_err_inj_b_ber_sel_shift 3 +#define tx_err_inj_b_ber_sel_mask 0x1f8 + + +#define tx_err_inj_b_coarse_sel_addr 0b110000110 +#define tx_err_inj_b_coarse_sel_startbit 3 +#define tx_err_inj_b_coarse_sel_width 4 +#define tx_err_inj_b_coarse_sel_endbit 6 +#define tx_err_inj_b_coarse_sel_shift 9 +#define tx_err_inj_b_coarse_sel_mask 0x1e00 + + +#define tx_err_inj_b_fine_sel_addr 0b110000110 +#define tx_err_inj_b_fine_sel_startbit 0 +#define tx_err_inj_b_fine_sel_width 3 +#define tx_err_inj_b_fine_sel_endbit 2 +#define tx_err_inj_b_fine_sel_shift 13 +#define tx_err_inj_b_fine_sel_mask 0xe000 + + +#define tx_err_inj_clock_enable_addr 0b110000101 +#define tx_err_inj_clock_enable_startbit 14 +#define tx_err_inj_clock_enable_width 1 +#define tx_err_inj_clock_enable_endbit 14 +#define tx_err_inj_clock_enable_shift 1 +#define tx_err_inj_clock_enable_mask 0x2 + + +#define tx_err_inj_enable_addr 0b110000101 +#define tx_err_inj_enable_startbit 13 +#define tx_err_inj_enable_width 1 +#define tx_err_inj_enable_endbit 13 +#define tx_err_inj_enable_shift 2 +#define tx_err_inj_enable_mask 0x4 + + +#define tx_err_inject_addr 0b010000010 +#define tx_err_inject_startbit 0 +#define tx_err_inject_width 5 +#define tx_err_inject_endbit 4 +#define tx_err_inject_shift 11 +#define tx_err_inject_mask 0xf800 + + +#define tx_exbist_mode_addr 0b110000010 +#define tx_exbist_mode_startbit 4 +#define tx_exbist_mode_width 1 +#define tx_exbist_mode_endbit 4 +#define tx_exbist_mode_shift 11 +#define tx_exbist_mode_mask 0x800 + + +#define tx_ffe_boost_en_addr 0b110100101 +#define tx_ffe_boost_en_startbit 11 +#define tx_ffe_boost_en_width 1 +#define tx_ffe_boost_en_endbit 11 +#define tx_ffe_boost_en_shift 4 +#define tx_ffe_boost_en_mask 0x10 + + +#define tx_fifo_init_addr 0b010000010 +#define tx_fifo_init_startbit 5 +#define tx_fifo_init_width 1 +#define tx_fifo_init_endbit 5 +#define tx_fifo_init_shift 10 +#define tx_fifo_init_mask 0x400 + + +#define tx_fifo_l2u_dly_addr 0b010000001 +#define tx_fifo_l2u_dly_startbit 0 +#define tx_fifo_l2u_dly_width 3 +#define tx_fifo_l2u_dly_endbit 2 +#define tx_fifo_l2u_dly_shift 13 +#define tx_fifo_l2u_dly_mask 0xe000 + + +#define tx_fir_reset_addr 0b110100010 +#define tx_fir_reset_startbit 15 +#define tx_fir_reset_width 1 +#define tx_fir_reset_endbit 15 +#define tx_fir_reset_shift 0 +#define tx_fir_reset_mask 0x1 + + +#define tx_lane_bist_actvity_det_addr 0b010000011 +#define tx_lane_bist_actvity_det_startbit 1 +#define tx_lane_bist_actvity_det_width 1 +#define tx_lane_bist_actvity_det_endbit 1 +#define tx_lane_bist_actvity_det_shift 14 +#define tx_lane_bist_actvity_det_mask 0x4000 + + +#define tx_lane_bist_err_addr 0b010000011 +#define tx_lane_bist_err_startbit 0 +#define tx_lane_bist_err_width 1 +#define tx_lane_bist_err_endbit 0 +#define tx_lane_bist_err_shift 15 +#define tx_lane_bist_err_mask 0x8000 + + +#define tx_lane_invert_addr 0b010000000 +#define tx_lane_invert_startbit 1 +#define tx_lane_invert_width 1 +#define tx_lane_invert_endbit 1 +#define tx_lane_invert_shift 14 +#define tx_lane_invert_mask 0x4000 + + +#define tx_lane_pdwn_addr 0b010000000 +#define tx_lane_pdwn_startbit 0 +#define tx_lane_pdwn_width 1 +#define tx_lane_pdwn_endbit 0 +#define tx_lane_pdwn_shift 15 +#define tx_lane_pdwn_mask 0x8000 + + +#define tx_lane_quiesce_addr 0b010000000 +#define tx_lane_quiesce_startbit 2 +#define tx_lane_quiesce_width 2 +#define tx_lane_quiesce_endbit 3 +#define tx_lane_quiesce_shift 12 +#define tx_lane_quiesce_mask 0x3000 + + +#define tx_marginpd_sel_addr 0b110101010 +#define tx_marginpd_sel_startbit 8 +#define tx_marginpd_sel_width 8 +#define tx_marginpd_sel_endbit 15 +#define tx_marginpd_sel_shift 0 +#define tx_marginpd_sel_mask 0xff + + +#define tx_marginpu_sel_addr 0b110101010 +#define tx_marginpu_sel_startbit 0 +#define tx_marginpu_sel_width 8 +#define tx_marginpu_sel_endbit 7 +#define tx_marginpu_sel_shift 8 +#define tx_marginpu_sel_mask 0xff00 + + +#define tx_nseg_marginpd_en_addr 0b110101001 +#define tx_nseg_marginpd_en_startbit 8 +#define tx_nseg_marginpd_en_width 8 +#define tx_nseg_marginpd_en_endbit 15 +#define tx_nseg_marginpd_en_shift 0 +#define tx_nseg_marginpd_en_mask 0xff + + +#define tx_nseg_marginpu_en_addr 0b110101001 +#define tx_nseg_marginpu_en_startbit 0 +#define tx_nseg_marginpu_en_width 8 +#define tx_nseg_marginpu_en_endbit 7 +#define tx_nseg_marginpu_en_shift 8 +#define tx_nseg_marginpu_en_mask 0xff00 + + +#define tx_nseg_pre_en_addr 0b110100111 +#define tx_nseg_pre_en_startbit 3 +#define tx_nseg_pre_en_width 5 +#define tx_nseg_pre_en_endbit 7 +#define tx_nseg_pre_en_shift 8 +#define tx_nseg_pre_en_mask 0x1f00 + + +#define tx_nseg_pre_sel_addr 0b110100111 +#define tx_nseg_pre_sel_startbit 8 +#define tx_nseg_pre_sel_width 5 +#define tx_nseg_pre_sel_endbit 12 +#define tx_nseg_pre_sel_shift 3 +#define tx_nseg_pre_sel_mask 0xf8 + + +#define tx_pg_ctl_sm_spare_mode_0_addr 0b110100100 +#define tx_pg_ctl_sm_spare_mode_0_startbit 0 +#define tx_pg_ctl_sm_spare_mode_0_width 1 +#define tx_pg_ctl_sm_spare_mode_0_endbit 0 +#define tx_pg_ctl_sm_spare_mode_0_shift 15 +#define tx_pg_ctl_sm_spare_mode_0_mask 0x8000 + + +#define tx_pg_ctl_sm_spare_mode_1_addr 0b110100100 +#define tx_pg_ctl_sm_spare_mode_1_startbit 1 +#define tx_pg_ctl_sm_spare_mode_1_width 1 +#define tx_pg_ctl_sm_spare_mode_1_endbit 1 +#define tx_pg_ctl_sm_spare_mode_1_shift 14 +#define tx_pg_ctl_sm_spare_mode_1_mask 0x4000 + + +#define tx_pg_ctl_sm_spare_mode_2_addr 0b110100100 +#define tx_pg_ctl_sm_spare_mode_2_startbit 2 +#define tx_pg_ctl_sm_spare_mode_2_width 1 +#define tx_pg_ctl_sm_spare_mode_2_endbit 2 +#define tx_pg_ctl_sm_spare_mode_2_shift 13 +#define tx_pg_ctl_sm_spare_mode_2_mask 0x2000 + + +#define tx_pg_ctl_sm_spare_mode_3_addr 0b110100100 +#define tx_pg_ctl_sm_spare_mode_3_startbit 3 +#define tx_pg_ctl_sm_spare_mode_3_width 1 +#define tx_pg_ctl_sm_spare_mode_3_endbit 3 +#define tx_pg_ctl_sm_spare_mode_3_shift 12 +#define tx_pg_ctl_sm_spare_mode_3_mask 0x1000 + + +#define tx_pg_ctl_sm_spare_mode_4_addr 0b110100100 +#define tx_pg_ctl_sm_spare_mode_4_startbit 4 +#define tx_pg_ctl_sm_spare_mode_4_width 1 +#define tx_pg_ctl_sm_spare_mode_4_endbit 4 +#define tx_pg_ctl_sm_spare_mode_4_shift 11 +#define tx_pg_ctl_sm_spare_mode_4_mask 0x800 + + +#define tx_pg_ctl_sm_spare_mode_5_addr 0b110100100 +#define tx_pg_ctl_sm_spare_mode_5_startbit 5 +#define tx_pg_ctl_sm_spare_mode_5_width 1 +#define tx_pg_ctl_sm_spare_mode_5_endbit 5 +#define tx_pg_ctl_sm_spare_mode_5_shift 10 +#define tx_pg_ctl_sm_spare_mode_5_mask 0x400 + + +#define tx_pg_ctl_sm_spare_mode_6_addr 0b110100100 +#define tx_pg_ctl_sm_spare_mode_6_startbit 6 +#define tx_pg_ctl_sm_spare_mode_6_width 1 +#define tx_pg_ctl_sm_spare_mode_6_endbit 6 +#define tx_pg_ctl_sm_spare_mode_6_shift 9 +#define tx_pg_ctl_sm_spare_mode_6_mask 0x200 + + +#define tx_pg_ctl_sm_spare_mode_7_addr 0b110100100 +#define tx_pg_ctl_sm_spare_mode_7_startbit 7 +#define tx_pg_ctl_sm_spare_mode_7_width 1 +#define tx_pg_ctl_sm_spare_mode_7_endbit 7 +#define tx_pg_ctl_sm_spare_mode_7_shift 8 +#define tx_pg_ctl_sm_spare_mode_7_mask 0x100 + + +#define tx_pg_fir_err_ctl_regs_addr 0b110100000 +#define tx_pg_fir_err_ctl_regs_startbit 4 +#define tx_pg_fir_err_ctl_regs_width 1 +#define tx_pg_fir_err_ctl_regs_endbit 4 +#define tx_pg_fir_err_ctl_regs_shift 11 +#define tx_pg_fir_err_ctl_regs_mask 0x800 + + +#define tx_pg_fir_err_gcr_buff_addr 0b110100000 +#define tx_pg_fir_err_gcr_buff_startbit 1 +#define tx_pg_fir_err_gcr_buff_width 1 +#define tx_pg_fir_err_gcr_buff_endbit 1 +#define tx_pg_fir_err_gcr_buff_shift 14 +#define tx_pg_fir_err_gcr_buff_mask 0x4000 + + +#define tx_pg_fir_err_gcrs_ld_sm_addr 0b110100000 +#define tx_pg_fir_err_gcrs_ld_sm_startbit 2 +#define tx_pg_fir_err_gcrs_ld_sm_width 1 +#define tx_pg_fir_err_gcrs_ld_sm_endbit 2 +#define tx_pg_fir_err_gcrs_ld_sm_shift 13 +#define tx_pg_fir_err_gcrs_ld_sm_mask 0x2000 + + +#define tx_pg_fir_err_gcrs_unld_sm_addr 0b110100000 +#define tx_pg_fir_err_gcrs_unld_sm_startbit 3 +#define tx_pg_fir_err_gcrs_unld_sm_width 1 +#define tx_pg_fir_err_gcrs_unld_sm_endbit 3 +#define tx_pg_fir_err_gcrs_unld_sm_shift 12 +#define tx_pg_fir_err_gcrs_unld_sm_mask 0x1000 + + +#define tx_pg_fir_err_inj_addr 0b110100011 +#define tx_pg_fir_err_inj_startbit 0 +#define tx_pg_fir_err_inj_width 5 +#define tx_pg_fir_err_inj_endbit 4 +#define tx_pg_fir_err_inj_shift 11 +#define tx_pg_fir_err_inj_mask 0xf800 + + +#define tx_pg_fir_err_tx_sm_regs_addr 0b110100000 +#define tx_pg_fir_err_tx_sm_regs_startbit 0 +#define tx_pg_fir_err_tx_sm_regs_width 1 +#define tx_pg_fir_err_tx_sm_regs_endbit 0 +#define tx_pg_fir_err_tx_sm_regs_shift 15 +#define tx_pg_fir_err_tx_sm_regs_mask 0x8000 + + +#define tx_pg_fir_errs_mask_addr 0b110100001 +#define tx_pg_fir_errs_mask_startbit 0 +#define tx_pg_fir_errs_mask_width 5 +#define tx_pg_fir_errs_mask_endbit 4 +#define tx_pg_fir_errs_mask_shift 11 +#define tx_pg_fir_errs_mask_mask 0xf800 + + +#define tx_pg_spare_mode_0_addr 0b110000000 +#define tx_pg_spare_mode_0_startbit 0 +#define tx_pg_spare_mode_0_width 1 +#define tx_pg_spare_mode_0_endbit 0 +#define tx_pg_spare_mode_0_shift 15 +#define tx_pg_spare_mode_0_mask 0x8000 + + +#define tx_pg_spare_mode_1_addr 0b110000000 +#define tx_pg_spare_mode_1_startbit 1 +#define tx_pg_spare_mode_1_width 1 +#define tx_pg_spare_mode_1_endbit 1 +#define tx_pg_spare_mode_1_shift 14 +#define tx_pg_spare_mode_1_mask 0x4000 + + +#define tx_pg_spare_mode_2_addr 0b110000000 +#define tx_pg_spare_mode_2_startbit 2 +#define tx_pg_spare_mode_2_width 1 +#define tx_pg_spare_mode_2_endbit 2 +#define tx_pg_spare_mode_2_shift 13 +#define tx_pg_spare_mode_2_mask 0x2000 + + +#define tx_pg_spare_mode_3_addr 0b110000000 +#define tx_pg_spare_mode_3_startbit 3 +#define tx_pg_spare_mode_3_width 1 +#define tx_pg_spare_mode_3_endbit 3 +#define tx_pg_spare_mode_3_shift 12 +#define tx_pg_spare_mode_3_mask 0x1000 + + +#define tx_pg_spare_mode_4_addr 0b110000000 +#define tx_pg_spare_mode_4_startbit 4 +#define tx_pg_spare_mode_4_width 1 +#define tx_pg_spare_mode_4_endbit 4 +#define tx_pg_spare_mode_4_shift 11 +#define tx_pg_spare_mode_4_mask 0x800 + + +#define tx_pg_spare_mode_5_addr 0b110000000 +#define tx_pg_spare_mode_5_startbit 5 +#define tx_pg_spare_mode_5_width 1 +#define tx_pg_spare_mode_5_endbit 5 +#define tx_pg_spare_mode_5_shift 10 +#define tx_pg_spare_mode_5_mask 0x400 + + +#define tx_pg_spare_mode_6_addr 0b110000000 +#define tx_pg_spare_mode_6_startbit 6 +#define tx_pg_spare_mode_6_width 1 +#define tx_pg_spare_mode_6_endbit 6 +#define tx_pg_spare_mode_6_shift 9 +#define tx_pg_spare_mode_6_mask 0x200 + + +#define tx_pg_spare_mode_7_addr 0b110000000 +#define tx_pg_spare_mode_7_startbit 7 +#define tx_pg_spare_mode_7_width 1 +#define tx_pg_spare_mode_7_endbit 7 +#define tx_pg_spare_mode_7_shift 8 +#define tx_pg_spare_mode_7_mask 0x100 + + +#define tx_pg_spare_mode_8_9_addr 0b110000000 +#define tx_pg_spare_mode_8_9_startbit 8 +#define tx_pg_spare_mode_8_9_width 2 +#define tx_pg_spare_mode_8_9_endbit 9 +#define tx_pg_spare_mode_8_9_shift 6 +#define tx_pg_spare_mode_8_9_mask 0xc0 + + +#define tx_pl_fir_err_addr 0b110100000 +#define tx_pl_fir_err_startbit 15 +#define tx_pl_fir_err_width 1 +#define tx_pl_fir_err_endbit 15 +#define tx_pl_fir_err_shift 0 +#define tx_pl_fir_err_mask 0x1 + + +#define tx_pl_fir_err_inj_addr 0b010000110 +#define tx_pl_fir_err_inj_startbit 0 +#define tx_pl_fir_err_inj_width 1 +#define tx_pl_fir_err_inj_endbit 0 +#define tx_pl_fir_err_inj_shift 15 +#define tx_pl_fir_err_inj_mask 0x8000 + + +#define tx_pl_fir_err_mask_addr 0b110100001 +#define tx_pl_fir_err_mask_startbit 15 +#define tx_pl_fir_err_mask_width 1 +#define tx_pl_fir_err_mask_endbit 15 +#define tx_pl_fir_err_mask_shift 0 +#define tx_pl_fir_err_mask_mask 0x1 + + +#define tx_pl_fir_errs_addr 0b010000100 +#define tx_pl_fir_errs_startbit 0 +#define tx_pl_fir_errs_width 1 +#define tx_pl_fir_errs_endbit 0 +#define tx_pl_fir_errs_shift 15 +#define tx_pl_fir_errs_mask 0x8000 + + +#define tx_pl_fir_errs_mask_addr 0b010000101 +#define tx_pl_fir_errs_mask_startbit 0 +#define tx_pl_fir_errs_mask_width 1 +#define tx_pl_fir_errs_mask_endbit 0 +#define tx_pl_fir_errs_mask_shift 15 +#define tx_pl_fir_errs_mask_mask 0x8000 + + +#define tx_pl_spare_mode_0_addr 0b010000000 +#define tx_pl_spare_mode_0_startbit 12 +#define tx_pl_spare_mode_0_width 1 +#define tx_pl_spare_mode_0_endbit 12 +#define tx_pl_spare_mode_0_shift 3 +#define tx_pl_spare_mode_0_mask 0x8 + + +#define tx_pl_spare_mode_1_addr 0b010000000 +#define tx_pl_spare_mode_1_startbit 13 +#define tx_pl_spare_mode_1_width 1 +#define tx_pl_spare_mode_1_endbit 13 +#define tx_pl_spare_mode_1_shift 2 +#define tx_pl_spare_mode_1_mask 0x4 + + +#define tx_pl_spare_mode_2_addr 0b010000000 +#define tx_pl_spare_mode_2_startbit 14 +#define tx_pl_spare_mode_2_width 1 +#define tx_pl_spare_mode_2_endbit 14 +#define tx_pl_spare_mode_2_shift 1 +#define tx_pl_spare_mode_2_mask 0x2 + + +#define tx_pl_spare_mode_3_addr 0b010000000 +#define tx_pl_spare_mode_3_startbit 15 +#define tx_pl_spare_mode_3_width 1 +#define tx_pl_spare_mode_3_endbit 15 +#define tx_pl_spare_mode_3_shift 0 +#define tx_pl_spare_mode_3_mask 0x1 + + +#define tx_pseg_marginpd_en_addr 0b110101000 +#define tx_pseg_marginpd_en_startbit 8 +#define tx_pseg_marginpd_en_width 8 +#define tx_pseg_marginpd_en_endbit 15 +#define tx_pseg_marginpd_en_shift 0 +#define tx_pseg_marginpd_en_mask 0xff + + +#define tx_pseg_marginpu_en_addr 0b110101000 +#define tx_pseg_marginpu_en_startbit 0 +#define tx_pseg_marginpu_en_width 8 +#define tx_pseg_marginpu_en_endbit 7 +#define tx_pseg_marginpu_en_shift 8 +#define tx_pseg_marginpu_en_mask 0xff00 + + +#define tx_pseg_pre_en_addr 0b110100110 +#define tx_pseg_pre_en_startbit 3 +#define tx_pseg_pre_en_width 5 +#define tx_pseg_pre_en_endbit 7 +#define tx_pseg_pre_en_shift 8 +#define tx_pseg_pre_en_mask 0x1f00 + + +#define tx_pseg_pre_sel_addr 0b110100110 +#define tx_pseg_pre_sel_startbit 8 +#define tx_pseg_pre_sel_width 5 +#define tx_pseg_pre_sel_endbit 12 +#define tx_pseg_pre_sel_shift 3 +#define tx_pseg_pre_sel_mask 0xf8 + + +#define tx_seg_test_leakage_ctrl_addr 0b110100101 +#define tx_seg_test_leakage_ctrl_startbit 13 +#define tx_seg_test_leakage_ctrl_width 1 +#define tx_seg_test_leakage_ctrl_endbit 13 +#define tx_seg_test_leakage_ctrl_shift 2 +#define tx_seg_test_leakage_ctrl_mask 0x4 + + +#define tx_seg_test_mode_addr 0b110100101 +#define tx_seg_test_mode_startbit 2 +#define tx_seg_test_mode_width 8 +#define tx_seg_test_mode_endbit 9 +#define tx_seg_test_mode_shift 6 +#define tx_seg_test_mode_mask 0x3fc0 + + +#define tx_seg_test_status_addr 0b010000011 +#define tx_seg_test_status_startbit 2 +#define tx_seg_test_status_width 2 +#define tx_seg_test_status_endbit 3 +#define tx_seg_test_status_shift 12 +#define tx_seg_test_status_mask 0x3000 + + +#define tx_set_unload_clk_disable_addr 0b010000010 +#define tx_set_unload_clk_disable_startbit 12 +#define tx_set_unload_clk_disable_width 1 +#define tx_set_unload_clk_disable_endbit 12 +#define tx_set_unload_clk_disable_shift 3 +#define tx_set_unload_clk_disable_mask 0x8 + + +#define tx_tdr_capt_val_addr 0b010000011 +#define tx_tdr_capt_val_startbit 15 +#define tx_tdr_capt_val_width 1 +#define tx_tdr_capt_val_endbit 15 +#define tx_tdr_capt_val_shift 0 +#define tx_tdr_capt_val_mask 0x1 + + +#define tx_tdr_dac_cntl_addr 0b110011001 +#define tx_tdr_dac_cntl_startbit 0 +#define tx_tdr_dac_cntl_width 8 +#define tx_tdr_dac_cntl_endbit 7 +#define tx_tdr_dac_cntl_shift 8 +#define tx_tdr_dac_cntl_mask 0xff00 + + +#define tx_tdr_enable_addr 0b010001010 +#define tx_tdr_enable_startbit 0 +#define tx_tdr_enable_width 1 +#define tx_tdr_enable_endbit 0 +#define tx_tdr_enable_shift 15 +#define tx_tdr_enable_mask 0x8000 + + +#define tx_tdr_phase_sel_addr 0b110011001 +#define tx_tdr_phase_sel_startbit 9 +#define tx_tdr_phase_sel_width 1 +#define tx_tdr_phase_sel_endbit 9 +#define tx_tdr_phase_sel_shift 6 +#define tx_tdr_phase_sel_mask 0x40 + + +#define tx_tdr_pulse_offset_addr 0b110011010 +#define tx_tdr_pulse_offset_startbit 0 +#define tx_tdr_pulse_offset_width 14 +#define tx_tdr_pulse_offset_endbit 13 +#define tx_tdr_pulse_offset_shift 2 +#define tx_tdr_pulse_offset_mask 0xfffc + + +#define tx_unload_clk_disable_addr 0b010000001 +#define tx_unload_clk_disable_startbit 8 +#define tx_unload_clk_disable_width 1 +#define tx_unload_clk_disable_endbit 8 +#define tx_unload_clk_disable_shift 7 +#define tx_unload_clk_disable_mask 0x80 + + +#define tx_unload_sel_addr 0b010000001 +#define tx_unload_sel_startbit 10 +#define tx_unload_sel_width 3 +#define tx_unload_sel_endbit 12 +#define tx_unload_sel_shift 3 +#define tx_unload_sel_mask 0x38 + + +#define tx_zcal_ans_not_found_error_addr 0b111100111 +#define tx_zcal_ans_not_found_error_startbit 1 +#define tx_zcal_ans_not_found_error_width 1 +#define tx_zcal_ans_not_found_error_endbit 1 +#define tx_zcal_ans_not_found_error_shift 14 +#define tx_zcal_ans_not_found_error_mask 0x4000 + + +#define tx_zcal_ans_range_error_addr 0b111100111 +#define tx_zcal_ans_range_error_startbit 2 +#define tx_zcal_ans_range_error_width 1 +#define tx_zcal_ans_range_error_endbit 2 +#define tx_zcal_ans_range_error_shift 13 +#define tx_zcal_ans_range_error_mask 0x2000 + + +#define tx_zcal_busy_addr 0b111100000 +#define tx_zcal_busy_startbit 4 +#define tx_zcal_busy_width 1 +#define tx_zcal_busy_endbit 4 +#define tx_zcal_busy_shift 11 +#define tx_zcal_busy_mask 0x800 + + +#define tx_zcal_cmp_out_addr 0b111100000 +#define tx_zcal_cmp_out_startbit 6 +#define tx_zcal_cmp_out_width 1 +#define tx_zcal_cmp_out_endbit 6 +#define tx_zcal_cmp_out_shift 9 +#define tx_zcal_cmp_out_mask 0x200 + + +#define tx_zcal_cya_data_inv_addr 0b111100100 +#define tx_zcal_cya_data_inv_startbit 8 +#define tx_zcal_cya_data_inv_width 1 +#define tx_zcal_cya_data_inv_endbit 8 +#define tx_zcal_cya_data_inv_shift 7 +#define tx_zcal_cya_data_inv_mask 0x80 + + +#define tx_zcal_done_addr 0b111100000 +#define tx_zcal_done_startbit 2 +#define tx_zcal_done_width 1 +#define tx_zcal_done_endbit 2 +#define tx_zcal_done_shift 13 +#define tx_zcal_done_mask 0x2000 + + +#define tx_zcal_error_addr 0b111100000 +#define tx_zcal_error_startbit 3 +#define tx_zcal_error_width 1 +#define tx_zcal_error_endbit 3 +#define tx_zcal_error_shift 12 +#define tx_zcal_error_mask 0x1000 + + +#define tx_zcal_force_sample_addr 0b111100000 +#define tx_zcal_force_sample_startbit 5 +#define tx_zcal_force_sample_width 1 +#define tx_zcal_force_sample_endbit 5 +#define tx_zcal_force_sample_shift 10 +#define tx_zcal_force_sample_mask 0x400 + + +#define tx_zcal_n_addr 0b111100001 +#define tx_zcal_n_startbit 0 +#define tx_zcal_n_width 9 +#define tx_zcal_n_endbit 8 +#define tx_zcal_n_shift 7 +#define tx_zcal_n_mask 0xff80 + + +#define tx_zcal_p_addr 0b111100010 +#define tx_zcal_p_startbit 0 +#define tx_zcal_p_width 9 +#define tx_zcal_p_endbit 8 +#define tx_zcal_p_shift 7 +#define tx_zcal_p_mask 0xff80 + + +#define tx_zcal_p_4x_addr 0b111100011 +#define tx_zcal_p_4x_startbit 0 +#define tx_zcal_p_4x_width 5 +#define tx_zcal_p_4x_endbit 4 +#define tx_zcal_p_4x_shift 11 +#define tx_zcal_p_4x_mask 0xf800 + + +#define tx_zcal_range_check_addr 0b111100100 +#define tx_zcal_range_check_startbit 7 +#define tx_zcal_range_check_width 1 +#define tx_zcal_range_check_endbit 7 +#define tx_zcal_range_check_shift 8 +#define tx_zcal_range_check_mask 0x100 + + +#define tx_zcal_req_addr 0b111100000 +#define tx_zcal_req_startbit 1 +#define tx_zcal_req_width 1 +#define tx_zcal_req_endbit 1 +#define tx_zcal_req_shift 14 +#define tx_zcal_req_mask 0x4000 + + +#define tx_zcal_sample_cnt_addr 0b111100000 +#define tx_zcal_sample_cnt_startbit 7 +#define tx_zcal_sample_cnt_width 9 +#define tx_zcal_sample_cnt_endbit 15 +#define tx_zcal_sample_cnt_shift 0 +#define tx_zcal_sample_cnt_mask 0x1ff + + +#define tx_zcal_sm_max_val_addr 0b111100101 +#define tx_zcal_sm_max_val_startbit 7 +#define tx_zcal_sm_max_val_width 7 +#define tx_zcal_sm_max_val_endbit 13 +#define tx_zcal_sm_max_val_shift 2 +#define tx_zcal_sm_max_val_mask 0x1fc + + +#define tx_zcal_sm_min_val_addr 0b111100101 +#define tx_zcal_sm_min_val_startbit 0 +#define tx_zcal_sm_min_val_width 7 +#define tx_zcal_sm_min_val_endbit 6 +#define tx_zcal_sm_min_val_shift 9 +#define tx_zcal_sm_min_val_mask 0xfe00 + + +#define tx_zcal_swo_cal_segs_addr 0b111100100 +#define tx_zcal_swo_cal_segs_startbit 1 +#define tx_zcal_swo_cal_segs_width 1 +#define tx_zcal_swo_cal_segs_endbit 1 +#define tx_zcal_swo_cal_segs_shift 14 +#define tx_zcal_swo_cal_segs_mask 0x4000 + + +#define tx_zcal_swo_cmp_inv_addr 0b111100100 +#define tx_zcal_swo_cmp_inv_startbit 2 +#define tx_zcal_swo_cmp_inv_width 1 +#define tx_zcal_swo_cmp_inv_endbit 2 +#define tx_zcal_swo_cmp_inv_shift 13 +#define tx_zcal_swo_cmp_inv_mask 0x2000 + + +#define tx_zcal_swo_cmp_offset_addr 0b111100100 +#define tx_zcal_swo_cmp_offset_startbit 3 +#define tx_zcal_swo_cmp_offset_width 1 +#define tx_zcal_swo_cmp_offset_endbit 3 +#define tx_zcal_swo_cmp_offset_shift 12 +#define tx_zcal_swo_cmp_offset_mask 0x1000 + + +#define tx_zcal_swo_cmp_reset_addr 0b111100100 +#define tx_zcal_swo_cmp_reset_startbit 4 +#define tx_zcal_swo_cmp_reset_width 1 +#define tx_zcal_swo_cmp_reset_endbit 4 +#define tx_zcal_swo_cmp_reset_shift 11 +#define tx_zcal_swo_cmp_reset_mask 0x800 + + +#define tx_zcal_swo_en_addr 0b111100100 +#define tx_zcal_swo_en_startbit 0 +#define tx_zcal_swo_en_width 1 +#define tx_zcal_swo_en_endbit 0 +#define tx_zcal_swo_en_shift 15 +#define tx_zcal_swo_en_mask 0x8000 + + +#define tx_zcal_swo_powerdown_addr 0b111100100 +#define tx_zcal_swo_powerdown_startbit 5 +#define tx_zcal_swo_powerdown_width 1 +#define tx_zcal_swo_powerdown_endbit 5 +#define tx_zcal_swo_powerdown_shift 10 +#define tx_zcal_swo_powerdown_mask 0x400 + + +#define tx_zcal_swo_tcoil_addr 0b111100100 +#define tx_zcal_swo_tcoil_startbit 6 +#define tx_zcal_swo_tcoil_width 1 +#define tx_zcal_swo_tcoil_endbit 6 +#define tx_zcal_swo_tcoil_shift 9 +#define tx_zcal_swo_tcoil_mask 0x200 + + +#define tx_zcal_test_clk_div_addr 0b111100100 +#define tx_zcal_test_clk_div_startbit 12 +#define tx_zcal_test_clk_div_width 1 +#define tx_zcal_test_clk_div_endbit 12 +#define tx_zcal_test_clk_div_shift 3 +#define tx_zcal_test_clk_div_mask 0x8 + + +#define tx_zcal_test_done_addr 0b111100111 +#define tx_zcal_test_done_startbit 7 +#define tx_zcal_test_done_width 1 +#define tx_zcal_test_done_endbit 7 +#define tx_zcal_test_done_shift 8 +#define tx_zcal_test_done_mask 0x100 + + +#define tx_zcal_test_enable_addr 0b111100111 +#define tx_zcal_test_enable_startbit 5 +#define tx_zcal_test_enable_width 1 +#define tx_zcal_test_enable_endbit 5 +#define tx_zcal_test_enable_shift 10 +#define tx_zcal_test_enable_mask 0x400 + + +#define tx_zcal_test_ovr_1r_addr 0b111100100 +#define tx_zcal_test_ovr_1r_startbit 10 +#define tx_zcal_test_ovr_1r_width 1 +#define tx_zcal_test_ovr_1r_endbit 10 +#define tx_zcal_test_ovr_1r_shift 5 +#define tx_zcal_test_ovr_1r_mask 0x20 + + +#define tx_zcal_test_ovr_2r_addr 0b111100100 +#define tx_zcal_test_ovr_2r_startbit 9 +#define tx_zcal_test_ovr_2r_width 1 +#define tx_zcal_test_ovr_2r_endbit 9 +#define tx_zcal_test_ovr_2r_shift 6 +#define tx_zcal_test_ovr_2r_mask 0x40 + + +#define tx_zcal_test_ovr_4x_seg_addr 0b111100100 +#define tx_zcal_test_ovr_4x_seg_startbit 11 +#define tx_zcal_test_ovr_4x_seg_width 1 +#define tx_zcal_test_ovr_4x_seg_endbit 11 +#define tx_zcal_test_ovr_4x_seg_shift 4 +#define tx_zcal_test_ovr_4x_seg_mask 0x10 + + +#define tx_zcal_test_status_addr 0b111100111 +#define tx_zcal_test_status_startbit 6 +#define tx_zcal_test_status_width 1 +#define tx_zcal_test_status_endbit 6 +#define tx_zcal_test_status_shift 9 +#define tx_zcal_test_status_mask 0x200 diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_mem_reg_const_pkg.h b/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_mem_reg_const_pkg.h new file mode 100644 index 00000000..f8d69929 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_mem_reg_const_pkg.h @@ -0,0 +1,1370 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_mem_reg_const_pkg.h $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//- *!*************************************************************************** +//- *! FILENAME : ppe_reg_const_pkg.h +//- *! TITLE : PPE Register Constants Package Header +//- *! DESCRIPTION : Constants containing register info for use by PPE +//- *! +//- *! +//- *! OWNER NAME : John Rell III Email: jgrell@us.ibm.com +//- *! BACKUP NAME : Mike Spear Email: mspear@us.ibm.com +//- *! +//- *!*************************************************************************** + + +#define fir1_errs_mask_full_reg_addr 0b101010010 +#define fir1_errs_mask_full_reg_startbit 0 +#define fir1_errs_mask_full_reg_width 16 +#define fir1_errs_mask_full_reg_endbit 15 +#define fir1_errs_mask_full_reg_shift 0 +#define fir1_errs_mask_full_reg_mask 0xffff + + +#define fir_err_mask_gcr_buff_addr 0b101010010 +#define fir_err_mask_gcr_buff_startbit 1 +#define fir_err_mask_gcr_buff_width 1 +#define fir_err_mask_gcr_buff_endbit 1 +#define fir_err_mask_gcr_buff_shift 14 +#define fir_err_mask_gcr_buff_mask 0x4000 + + +#define fir_err_mask_pg_regs_addr 0b101010010 +#define fir_err_mask_pg_regs_startbit 0 +#define fir_err_mask_pg_regs_width 1 +#define fir_err_mask_pg_regs_endbit 0 +#define fir_err_mask_pg_regs_shift 15 +#define fir_err_mask_pg_regs_mask 0x8000 + + +#define ppe_ddc_failed_status_addr 0b001110010 +#define ppe_ddc_failed_status_startbit 12 +#define ppe_ddc_failed_status_width 1 +#define ppe_ddc_failed_status_endbit 12 +#define ppe_ddc_failed_status_shift 3 +#define ppe_ddc_failed_status_mask 0x8 + + +#define ppe_dft_rx_done_addr 0b100001001 +#define ppe_dft_rx_done_startbit 1 +#define ppe_dft_rx_done_width 1 +#define ppe_dft_rx_done_endbit 1 +#define ppe_dft_rx_done_shift 14 +#define ppe_dft_rx_done_mask 0x4000 + + +#define ppe_dft_seg_done_addr 0b100001001 +#define ppe_dft_seg_done_startbit 2 +#define ppe_dft_seg_done_width 1 +#define ppe_dft_seg_done_endbit 2 +#define ppe_dft_seg_done_shift 13 +#define ppe_dft_seg_done_mask 0x2000 + + +#define ppe_dft_tx_done_addr 0b100001001 +#define ppe_dft_tx_done_startbit 0 +#define ppe_dft_tx_done_width 1 +#define ppe_dft_tx_done_endbit 0 +#define ppe_dft_tx_done_shift 15 +#define ppe_dft_tx_done_mask 0x8000 + + +#define ppe_dft_zcal_done_addr 0b100001001 +#define ppe_dft_zcal_done_startbit 3 +#define ppe_dft_zcal_done_width 1 +#define ppe_dft_zcal_done_endbit 3 +#define ppe_dft_zcal_done_shift 12 +#define ppe_dft_zcal_done_mask 0x1000 + + +#define ppe_gcr_port_addr 0b100000001 +#define ppe_gcr_port_startbit 6 +#define ppe_gcr_port_width 2 +#define ppe_gcr_port_endbit 7 +#define ppe_gcr_port_shift 8 +#define ppe_gcr_port_mask 0x300 + + +#define ppe_init_done_wait_addr 0b100011100 +#define ppe_init_done_wait_startbit 10 +#define ppe_init_done_wait_width 3 +#define ppe_init_done_wait_endbit 12 +#define ppe_init_done_wait_shift 3 +#define ppe_init_done_wait_mask 0x38 + + +#define ppe_last_thread_run_addr 0b100011100 +#define ppe_last_thread_run_startbit 7 +#define ppe_last_thread_run_width 3 +#define ppe_last_thread_run_endbit 9 +#define ppe_last_thread_run_shift 6 +#define ppe_last_thread_run_mask 0x1c0 + + +#define ppe_num_threads_addr 0b100011100 +#define ppe_num_threads_startbit 4 +#define ppe_num_threads_width 3 +#define ppe_num_threads_endbit 6 +#define ppe_num_threads_shift 9 +#define ppe_num_threads_mask 0xe00 + + +#define rx_b_ap_addr 0b001110110 +#define rx_b_ap_startbit 4 +#define rx_b_ap_width 8 +#define rx_b_ap_endbit 11 +#define rx_b_ap_shift 4 +#define rx_b_ap_mask 0xff0 + + +#define rx_bad_lane_cntr_addr 0b101001110 +#define rx_bad_lane_cntr_startbit 2 +#define rx_bad_lane_cntr_width 3 +#define rx_bad_lane_cntr_endbit 4 +#define rx_bad_lane_cntr_shift 11 +#define rx_bad_lane_cntr_mask 0x3800 + + +#define rx_bad_lane_enc_alias_addr 0b101101011 +#define rx_bad_lane_enc_alias_startbit 0 +#define rx_bad_lane_enc_alias_width 16 +#define rx_bad_lane_enc_alias_endbit 15 +#define rx_bad_lane_enc_alias_shift 0 +#define rx_bad_lane_enc_alias_mask 0xffff + + +#define rx_dc_step_cntl_edi_alias_addr 0b100101111 +#define rx_dc_step_cntl_edi_alias_startbit 0 +#define rx_dc_step_cntl_edi_alias_width 7 +#define rx_dc_step_cntl_edi_alias_endbit 6 +#define rx_dc_step_cntl_edi_alias_shift 9 +#define rx_dc_step_cntl_edi_alias_mask 0xfe00 + + +#define rx_dc_step_cntl_opt_alias_addr 0b100101111 +#define rx_dc_step_cntl_opt_alias_startbit 0 +#define rx_dc_step_cntl_opt_alias_width 5 +#define rx_dc_step_cntl_opt_alias_endbit 4 +#define rx_dc_step_cntl_opt_alias_shift 11 +#define rx_dc_step_cntl_opt_alias_mask 0xf800 + + +#define rx_dyn_rpr_ip_addr 0b101001110 +#define rx_dyn_rpr_ip_startbit 0 +#define rx_dyn_rpr_ip_width 1 +#define rx_dyn_rpr_ip_endbit 0 +#define rx_dyn_rpr_ip_shift 15 +#define rx_dyn_rpr_ip_mask 0x8000 + + +#define rx_eo_step_cntl2_edi_alias_addr 0b100101101 +#define rx_eo_step_cntl2_edi_alias_startbit 0 +#define rx_eo_step_cntl2_edi_alias_width 16 +#define rx_eo_step_cntl2_edi_alias_endbit 15 +#define rx_eo_step_cntl2_edi_alias_shift 0 +#define rx_eo_step_cntl2_edi_alias_mask 0xffff + + +#define rx_eo_step_cntl2_opt_alias_addr 0b100101101 +#define rx_eo_step_cntl2_opt_alias_startbit 0 +#define rx_eo_step_cntl2_opt_alias_width 3 +#define rx_eo_step_cntl2_opt_alias_endbit 2 +#define rx_eo_step_cntl2_opt_alias_shift 13 +#define rx_eo_step_cntl2_opt_alias_mask 0xe000 + + +#define rx_eo_step_cntl_edi_alias_addr 0b100010110 +#define rx_eo_step_cntl_edi_alias_startbit 0 +#define rx_eo_step_cntl_edi_alias_width 16 +#define rx_eo_step_cntl_edi_alias_endbit 15 +#define rx_eo_step_cntl_edi_alias_shift 0 +#define rx_eo_step_cntl_edi_alias_mask 0xffff + + +#define rx_eo_step_cntl_opt_alias_addr 0b100010110 +#define rx_eo_step_cntl_opt_alias_startbit 0 +#define rx_eo_step_cntl_opt_alias_width 11 +#define rx_eo_step_cntl_opt_alias_endbit 10 +#define rx_eo_step_cntl_opt_alias_shift 5 +#define rx_eo_step_cntl_opt_alias_mask 0xffe0 + + +#define rx_mode_pl_full_reg_addr 0b001000100 +#define rx_mode_pl_full_reg_startbit 0 +#define rx_mode_pl_full_reg_width 16 +#define rx_mode_pl_full_reg_endbit 15 +#define rx_mode_pl_full_reg_shift 0 +#define rx_mode_pl_full_reg_mask 0xffff + + +#define rx_pb_fir_err_gcr_buff0_addr 0b111110001 +#define rx_pb_fir_err_gcr_buff0_startbit 1 +#define rx_pb_fir_err_gcr_buff0_width 1 +#define rx_pb_fir_err_gcr_buff0_endbit 1 +#define rx_pb_fir_err_gcr_buff0_shift 14 +#define rx_pb_fir_err_gcr_buff0_mask 0x4000 + + +#define rx_pb_fir_err_gcr_buff1_addr 0b111110001 +#define rx_pb_fir_err_gcr_buff1_startbit 2 +#define rx_pb_fir_err_gcr_buff1_width 1 +#define rx_pb_fir_err_gcr_buff1_endbit 2 +#define rx_pb_fir_err_gcr_buff1_shift 13 +#define rx_pb_fir_err_gcr_buff1_mask 0x2000 + + +#define rx_pb_fir_err_gcr_buff2_addr 0b111110001 +#define rx_pb_fir_err_gcr_buff2_startbit 3 +#define rx_pb_fir_err_gcr_buff2_width 1 +#define rx_pb_fir_err_gcr_buff2_endbit 3 +#define rx_pb_fir_err_gcr_buff2_shift 12 +#define rx_pb_fir_err_gcr_buff2_mask 0x1000 + + +#define rx_pb_fir_err_gcrs_ld_sm0_addr 0b111110001 +#define rx_pb_fir_err_gcrs_ld_sm0_startbit 4 +#define rx_pb_fir_err_gcrs_ld_sm0_width 1 +#define rx_pb_fir_err_gcrs_ld_sm0_endbit 4 +#define rx_pb_fir_err_gcrs_ld_sm0_shift 11 +#define rx_pb_fir_err_gcrs_ld_sm0_mask 0x800 + + +#define rx_pb_fir_err_gcrs_ld_sm1_addr 0b111110001 +#define rx_pb_fir_err_gcrs_ld_sm1_startbit 5 +#define rx_pb_fir_err_gcrs_ld_sm1_width 1 +#define rx_pb_fir_err_gcrs_ld_sm1_endbit 5 +#define rx_pb_fir_err_gcrs_ld_sm1_shift 10 +#define rx_pb_fir_err_gcrs_ld_sm1_mask 0x400 + + +#define rx_pb_fir_err_gcrs_ld_sm2_addr 0b111110001 +#define rx_pb_fir_err_gcrs_ld_sm2_startbit 6 +#define rx_pb_fir_err_gcrs_ld_sm2_width 1 +#define rx_pb_fir_err_gcrs_ld_sm2_endbit 6 +#define rx_pb_fir_err_gcrs_ld_sm2_shift 9 +#define rx_pb_fir_err_gcrs_ld_sm2_mask 0x200 + + +#define rx_pb_fir_err_gcrs_unld_sm0_addr 0b111110001 +#define rx_pb_fir_err_gcrs_unld_sm0_startbit 7 +#define rx_pb_fir_err_gcrs_unld_sm0_width 1 +#define rx_pb_fir_err_gcrs_unld_sm0_endbit 7 +#define rx_pb_fir_err_gcrs_unld_sm0_shift 8 +#define rx_pb_fir_err_gcrs_unld_sm0_mask 0x100 + + +#define rx_pb_fir_err_gcrs_unld_sm1_addr 0b111110001 +#define rx_pb_fir_err_gcrs_unld_sm1_startbit 8 +#define rx_pb_fir_err_gcrs_unld_sm1_width 1 +#define rx_pb_fir_err_gcrs_unld_sm1_endbit 8 +#define rx_pb_fir_err_gcrs_unld_sm1_shift 7 +#define rx_pb_fir_err_gcrs_unld_sm1_mask 0x80 + + +#define rx_pb_fir_err_gcrs_unld_sm2_addr 0b111110001 +#define rx_pb_fir_err_gcrs_unld_sm2_startbit 9 +#define rx_pb_fir_err_gcrs_unld_sm2_width 1 +#define rx_pb_fir_err_gcrs_unld_sm2_endbit 9 +#define rx_pb_fir_err_gcrs_unld_sm2_shift 6 +#define rx_pb_fir_err_gcrs_unld_sm2_mask 0x40 + + +#define rx_pb_fir_err_inj_gcr_buff2_addr 0b111110011 +#define rx_pb_fir_err_inj_gcr_buff2_startbit 3 +#define rx_pb_fir_err_inj_gcr_buff2_width 1 +#define rx_pb_fir_err_inj_gcr_buff2_endbit 3 +#define rx_pb_fir_err_inj_gcr_buff2_shift 12 +#define rx_pb_fir_err_inj_gcr_buff2_mask 0x1000 + + +#define rx_pb_fir_err_inj_gcrs_ld_sm0_addr 0b111110011 +#define rx_pb_fir_err_inj_gcrs_ld_sm0_startbit 4 +#define rx_pb_fir_err_inj_gcrs_ld_sm0_width 1 +#define rx_pb_fir_err_inj_gcrs_ld_sm0_endbit 4 +#define rx_pb_fir_err_inj_gcrs_ld_sm0_shift 11 +#define rx_pb_fir_err_inj_gcrs_ld_sm0_mask 0x800 + + +#define rx_pb_fir_err_inj_gcrs_ld_sm1_addr 0b111110011 +#define rx_pb_fir_err_inj_gcrs_ld_sm1_startbit 5 +#define rx_pb_fir_err_inj_gcrs_ld_sm1_width 1 +#define rx_pb_fir_err_inj_gcrs_ld_sm1_endbit 5 +#define rx_pb_fir_err_inj_gcrs_ld_sm1_shift 10 +#define rx_pb_fir_err_inj_gcrs_ld_sm1_mask 0x400 + + +#define rx_pb_fir_err_inj_gcrs_ld_sm2_addr 0b111110011 +#define rx_pb_fir_err_inj_gcrs_ld_sm2_startbit 6 +#define rx_pb_fir_err_inj_gcrs_ld_sm2_width 1 +#define rx_pb_fir_err_inj_gcrs_ld_sm2_endbit 6 +#define rx_pb_fir_err_inj_gcrs_ld_sm2_shift 9 +#define rx_pb_fir_err_inj_gcrs_ld_sm2_mask 0x200 + + +#define rx_pb_fir_err_inj_gcrs_unld_sm0_addr 0b111110011 +#define rx_pb_fir_err_inj_gcrs_unld_sm0_startbit 7 +#define rx_pb_fir_err_inj_gcrs_unld_sm0_width 1 +#define rx_pb_fir_err_inj_gcrs_unld_sm0_endbit 7 +#define rx_pb_fir_err_inj_gcrs_unld_sm0_shift 8 +#define rx_pb_fir_err_inj_gcrs_unld_sm0_mask 0x100 + + +#define rx_pb_fir_err_inj_gcrs_unld_sm1_addr 0b111110011 +#define rx_pb_fir_err_inj_gcrs_unld_sm1_startbit 8 +#define rx_pb_fir_err_inj_gcrs_unld_sm1_width 1 +#define rx_pb_fir_err_inj_gcrs_unld_sm1_endbit 8 +#define rx_pb_fir_err_inj_gcrs_unld_sm1_shift 7 +#define rx_pb_fir_err_inj_gcrs_unld_sm1_mask 0x80 + + +#define rx_pb_fir_err_inj_gcrs_unld_sm2_addr 0b111110011 +#define rx_pb_fir_err_inj_gcrs_unld_sm2_startbit 9 +#define rx_pb_fir_err_inj_gcrs_unld_sm2_width 1 +#define rx_pb_fir_err_inj_gcrs_unld_sm2_endbit 9 +#define rx_pb_fir_err_inj_gcrs_unld_sm2_shift 6 +#define rx_pb_fir_err_inj_gcrs_unld_sm2_mask 0x40 + + +#define rx_pb_fir_err_inj_pb_regs_addr 0b111110011 +#define rx_pb_fir_err_inj_pb_regs_startbit 0 +#define rx_pb_fir_err_inj_pb_regs_width 1 +#define rx_pb_fir_err_inj_pb_regs_endbit 0 +#define rx_pb_fir_err_inj_pb_regs_shift 15 +#define rx_pb_fir_err_inj_pb_regs_mask 0x8000 + + +#define rx_pb_fir_err_inj_spare0_addr 0b111110011 +#define rx_pb_fir_err_inj_spare0_startbit 1 +#define rx_pb_fir_err_inj_spare0_width 1 +#define rx_pb_fir_err_inj_spare0_endbit 1 +#define rx_pb_fir_err_inj_spare0_shift 14 +#define rx_pb_fir_err_inj_spare0_mask 0x4000 + + +#define rx_pb_fir_err_inj_spare1_addr 0b111110011 +#define rx_pb_fir_err_inj_spare1_startbit 2 +#define rx_pb_fir_err_inj_spare1_width 1 +#define rx_pb_fir_err_inj_spare1_endbit 2 +#define rx_pb_fir_err_inj_spare1_shift 13 +#define rx_pb_fir_err_inj_spare1_mask 0x2000 + + +#define rx_pb_fir_err_mask_gcr_buff0_addr 0b111110010 +#define rx_pb_fir_err_mask_gcr_buff0_startbit 1 +#define rx_pb_fir_err_mask_gcr_buff0_width 1 +#define rx_pb_fir_err_mask_gcr_buff0_endbit 1 +#define rx_pb_fir_err_mask_gcr_buff0_shift 14 +#define rx_pb_fir_err_mask_gcr_buff0_mask 0x4000 + + +#define rx_pb_fir_err_mask_gcr_buff1_addr 0b111110010 +#define rx_pb_fir_err_mask_gcr_buff1_startbit 2 +#define rx_pb_fir_err_mask_gcr_buff1_width 1 +#define rx_pb_fir_err_mask_gcr_buff1_endbit 2 +#define rx_pb_fir_err_mask_gcr_buff1_shift 13 +#define rx_pb_fir_err_mask_gcr_buff1_mask 0x2000 + + +#define rx_pb_fir_err_mask_gcr_buff2_addr 0b111110010 +#define rx_pb_fir_err_mask_gcr_buff2_startbit 3 +#define rx_pb_fir_err_mask_gcr_buff2_width 1 +#define rx_pb_fir_err_mask_gcr_buff2_endbit 3 +#define rx_pb_fir_err_mask_gcr_buff2_shift 12 +#define rx_pb_fir_err_mask_gcr_buff2_mask 0x1000 + + +#define rx_pb_fir_err_mask_gcrs_ld_sm0_addr 0b111110010 +#define rx_pb_fir_err_mask_gcrs_ld_sm0_startbit 4 +#define rx_pb_fir_err_mask_gcrs_ld_sm0_width 1 +#define rx_pb_fir_err_mask_gcrs_ld_sm0_endbit 4 +#define rx_pb_fir_err_mask_gcrs_ld_sm0_shift 11 +#define rx_pb_fir_err_mask_gcrs_ld_sm0_mask 0x800 + + +#define rx_pb_fir_err_mask_gcrs_ld_sm1_addr 0b111110010 +#define rx_pb_fir_err_mask_gcrs_ld_sm1_startbit 5 +#define rx_pb_fir_err_mask_gcrs_ld_sm1_width 1 +#define rx_pb_fir_err_mask_gcrs_ld_sm1_endbit 5 +#define rx_pb_fir_err_mask_gcrs_ld_sm1_shift 10 +#define rx_pb_fir_err_mask_gcrs_ld_sm1_mask 0x400 + + +#define rx_pb_fir_err_mask_gcrs_ld_sm2_addr 0b111110010 +#define rx_pb_fir_err_mask_gcrs_ld_sm2_startbit 6 +#define rx_pb_fir_err_mask_gcrs_ld_sm2_width 1 +#define rx_pb_fir_err_mask_gcrs_ld_sm2_endbit 6 +#define rx_pb_fir_err_mask_gcrs_ld_sm2_shift 9 +#define rx_pb_fir_err_mask_gcrs_ld_sm2_mask 0x200 + + +#define rx_pb_fir_err_mask_gcrs_unld_sm0_addr 0b111110010 +#define rx_pb_fir_err_mask_gcrs_unld_sm0_startbit 7 +#define rx_pb_fir_err_mask_gcrs_unld_sm0_width 1 +#define rx_pb_fir_err_mask_gcrs_unld_sm0_endbit 7 +#define rx_pb_fir_err_mask_gcrs_unld_sm0_shift 8 +#define rx_pb_fir_err_mask_gcrs_unld_sm0_mask 0x100 + + +#define rx_pb_fir_err_mask_gcrs_unld_sm1_addr 0b111110010 +#define rx_pb_fir_err_mask_gcrs_unld_sm1_startbit 8 +#define rx_pb_fir_err_mask_gcrs_unld_sm1_width 1 +#define rx_pb_fir_err_mask_gcrs_unld_sm1_endbit 8 +#define rx_pb_fir_err_mask_gcrs_unld_sm1_shift 7 +#define rx_pb_fir_err_mask_gcrs_unld_sm1_mask 0x80 + + +#define rx_pb_fir_err_mask_gcrs_unld_sm2_addr 0b111110010 +#define rx_pb_fir_err_mask_gcrs_unld_sm2_startbit 9 +#define rx_pb_fir_err_mask_gcrs_unld_sm2_width 1 +#define rx_pb_fir_err_mask_gcrs_unld_sm2_endbit 9 +#define rx_pb_fir_err_mask_gcrs_unld_sm2_shift 6 +#define rx_pb_fir_err_mask_gcrs_unld_sm2_mask 0x40 + + +#define rx_pb_fir_err_mask_pb_regs_addr 0b111110010 +#define rx_pb_fir_err_mask_pb_regs_startbit 0 +#define rx_pb_fir_err_mask_pb_regs_width 1 +#define rx_pb_fir_err_mask_pb_regs_endbit 0 +#define rx_pb_fir_err_mask_pb_regs_shift 15 +#define rx_pb_fir_err_mask_pb_regs_mask 0x8000 + + +#define rx_pb_fir_err_pb_regs_addr 0b111110001 +#define rx_pb_fir_err_pb_regs_startbit 0 +#define rx_pb_fir_err_pb_regs_width 1 +#define rx_pb_fir_err_pb_regs_endbit 0 +#define rx_pb_fir_err_pb_regs_shift 15 +#define rx_pb_fir_err_pb_regs_mask 0x8000 + + +#define rx_pb_fir_errs_full_reg_addr 0b111110001 +#define rx_pb_fir_errs_full_reg_startbit 0 +#define rx_pb_fir_errs_full_reg_width 10 +#define rx_pb_fir_errs_full_reg_endbit 9 +#define rx_pb_fir_errs_full_reg_shift 6 +#define rx_pb_fir_errs_full_reg_mask 0xffc0 + + +#define rx_pb_fir_errs_inj_full_reg_addr 0b111110011 +#define rx_pb_fir_errs_inj_full_reg_startbit 0 +#define rx_pb_fir_errs_inj_full_reg_width 10 +#define rx_pb_fir_errs_inj_full_reg_endbit 9 +#define rx_pb_fir_errs_inj_full_reg_shift 6 +#define rx_pb_fir_errs_inj_full_reg_mask 0xffc0 + + +#define rx_pb_fir_errs_mask_full_reg_addr 0b111110010 +#define rx_pb_fir_errs_mask_full_reg_startbit 0 +#define rx_pb_fir_errs_mask_full_reg_width 10 +#define rx_pb_fir_errs_mask_full_reg_endbit 9 +#define rx_pb_fir_errs_mask_full_reg_shift 6 +#define rx_pb_fir_errs_mask_full_reg_mask 0xffc0 + + +#define rx_pg_fir1_err_inj_full_reg_addr 0b101010011 +#define rx_pg_fir1_err_inj_full_reg_startbit 0 +#define rx_pg_fir1_err_inj_full_reg_width 16 +#define rx_pg_fir1_err_inj_full_reg_endbit 15 +#define rx_pg_fir1_err_inj_full_reg_shift 0 +#define rx_pg_fir1_err_inj_full_reg_mask 0xffff + + +#define rx_pg_fir1_errs_full_reg_addr 0b101010001 +#define rx_pg_fir1_errs_full_reg_startbit 0 +#define rx_pg_fir1_errs_full_reg_width 16 +#define rx_pg_fir1_errs_full_reg_endbit 15 +#define rx_pg_fir1_errs_full_reg_shift 0 +#define rx_pg_fir1_errs_full_reg_mask 0xffff + + +#define rx_pg_fir2_err_inj_full_reg_addr 0b101100010 +#define rx_pg_fir2_err_inj_full_reg_startbit 0 +#define rx_pg_fir2_err_inj_full_reg_width 16 +#define rx_pg_fir2_err_inj_full_reg_endbit 15 +#define rx_pg_fir2_err_inj_full_reg_shift 0 +#define rx_pg_fir2_err_inj_full_reg_mask 0xffff + + +#define rx_pg_fir2_errs_full_reg_addr 0b101100000 +#define rx_pg_fir2_errs_full_reg_startbit 0 +#define rx_pg_fir2_errs_full_reg_width 16 +#define rx_pg_fir2_errs_full_reg_endbit 15 +#define rx_pg_fir2_errs_full_reg_shift 0 +#define rx_pg_fir2_errs_full_reg_mask 0xffff + + +#define rx_pg_fir2_errs_mask_full_reg_addr 0b101100001 +#define rx_pg_fir2_errs_mask_full_reg_startbit 0 +#define rx_pg_fir2_errs_mask_full_reg_width 16 +#define rx_pg_fir2_errs_mask_full_reg_endbit 15 +#define rx_pg_fir2_errs_mask_full_reg_shift 0 +#define rx_pg_fir2_errs_mask_full_reg_mask 0xffff + + +#define rx_pg_fir_err_inj_bist_init_state_addr 0b101010011 +#define rx_pg_fir_err_inj_bist_init_state_startbit 10 +#define rx_pg_fir_err_inj_bist_init_state_width 1 +#define rx_pg_fir_err_inj_bist_init_state_endbit 10 +#define rx_pg_fir_err_inj_bist_init_state_shift 5 +#define rx_pg_fir_err_inj_bist_init_state_mask 0x20 + + +#define rx_pg_fir_err_inj_bist_main_state_addr 0b101010011 +#define rx_pg_fir_err_inj_bist_main_state_startbit 9 +#define rx_pg_fir_err_inj_bist_main_state_width 1 +#define rx_pg_fir_err_inj_bist_main_state_endbit 9 +#define rx_pg_fir_err_inj_bist_main_state_shift 6 +#define rx_pg_fir_err_inj_bist_main_state_mask 0x40 + + +#define rx_pg_fir_err_inj_datasm_regrw_addr 0b101010011 +#define rx_pg_fir_err_inj_datasm_regrw_startbit 7 +#define rx_pg_fir_err_inj_datasm_regrw_width 1 +#define rx_pg_fir_err_inj_datasm_regrw_endbit 7 +#define rx_pg_fir_err_inj_datasm_regrw_shift 8 +#define rx_pg_fir_err_inj_datasm_regrw_mask 0x100 + + +#define rx_pg_fir_err_inj_datasm_regs_addr 0b101010011 +#define rx_pg_fir_err_inj_datasm_regs_startbit 6 +#define rx_pg_fir_err_inj_datasm_regs_width 1 +#define rx_pg_fir_err_inj_datasm_regs_endbit 6 +#define rx_pg_fir_err_inj_datasm_regs_shift 9 +#define rx_pg_fir_err_inj_datasm_regs_mask 0x200 + + +#define rx_pg_fir_err_inj_dsm_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_dsm_sm_startbit 14 +#define rx_pg_fir_err_inj_dsm_sm_width 1 +#define rx_pg_fir_err_inj_dsm_sm_endbit 14 +#define rx_pg_fir_err_inj_dsm_sm_shift 1 +#define rx_pg_fir_err_inj_dsm_sm_mask 0x2 + + +#define rx_pg_fir_err_inj_dyn_recal_hndshk_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_dyn_recal_hndshk_sm_startbit 6 +#define rx_pg_fir_err_inj_dyn_recal_hndshk_sm_width 1 +#define rx_pg_fir_err_inj_dyn_recal_hndshk_sm_endbit 6 +#define rx_pg_fir_err_inj_dyn_recal_hndshk_sm_shift 9 +#define rx_pg_fir_err_inj_dyn_recal_hndshk_sm_mask 0x200 + + +#define rx_pg_fir_err_inj_dyn_rpr_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_dyn_rpr_sm_startbit 0 +#define rx_pg_fir_err_inj_dyn_rpr_sm_width 1 +#define rx_pg_fir_err_inj_dyn_rpr_sm_endbit 0 +#define rx_pg_fir_err_inj_dyn_rpr_sm_shift 15 +#define rx_pg_fir_err_inj_dyn_rpr_sm_mask 0x8000 + + +#define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm_startbit 1 +#define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm_width 1 +#define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm_endbit 1 +#define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm_shift 14 +#define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm_mask 0x4000 + + +#define rx_pg_fir_err_inj_eyeopt_sm_addr 0b101010011 +#define rx_pg_fir_err_inj_eyeopt_sm_startbit 8 +#define rx_pg_fir_err_inj_eyeopt_sm_width 1 +#define rx_pg_fir_err_inj_eyeopt_sm_endbit 8 +#define rx_pg_fir_err_inj_eyeopt_sm_shift 7 +#define rx_pg_fir_err_inj_eyeopt_sm_mask 0x80 + + +#define rx_pg_fir_err_inj_gcr_buff_addr 0b101010011 +#define rx_pg_fir_err_inj_gcr_buff_startbit 1 +#define rx_pg_fir_err_inj_gcr_buff_width 1 +#define rx_pg_fir_err_inj_gcr_buff_endbit 1 +#define rx_pg_fir_err_inj_gcr_buff_shift 14 +#define rx_pg_fir_err_inj_gcr_buff_mask 0x4000 + + +#define rx_pg_fir_err_inj_gcrs_ld_sm_addr 0b101010011 +#define rx_pg_fir_err_inj_gcrs_ld_sm_startbit 2 +#define rx_pg_fir_err_inj_gcrs_ld_sm_width 1 +#define rx_pg_fir_err_inj_gcrs_ld_sm_endbit 2 +#define rx_pg_fir_err_inj_gcrs_ld_sm_shift 13 +#define rx_pg_fir_err_inj_gcrs_ld_sm_mask 0x2000 + + +#define rx_pg_fir_err_inj_gcrs_unld_sm_addr 0b101010011 +#define rx_pg_fir_err_inj_gcrs_unld_sm_startbit 3 +#define rx_pg_fir_err_inj_gcrs_unld_sm_width 1 +#define rx_pg_fir_err_inj_gcrs_unld_sm_endbit 3 +#define rx_pg_fir_err_inj_gcrs_unld_sm_shift 12 +#define rx_pg_fir_err_inj_gcrs_unld_sm_mask 0x1000 + + +#define rx_pg_fir_err_inj_glb_cal_snd_msg_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_glb_cal_snd_msg_sm_startbit 7 +#define rx_pg_fir_err_inj_glb_cal_snd_msg_sm_width 1 +#define rx_pg_fir_err_inj_glb_cal_snd_msg_sm_endbit 7 +#define rx_pg_fir_err_inj_glb_cal_snd_msg_sm_shift 8 +#define rx_pg_fir_err_inj_glb_cal_snd_msg_sm_mask 0x100 + + +#define rx_pg_fir_err_inj_glbsm_regrw_addr 0b101010011 +#define rx_pg_fir_err_inj_glbsm_regrw_startbit 5 +#define rx_pg_fir_err_inj_glbsm_regrw_width 1 +#define rx_pg_fir_err_inj_glbsm_regrw_endbit 5 +#define rx_pg_fir_err_inj_glbsm_regrw_shift 10 +#define rx_pg_fir_err_inj_glbsm_regrw_mask 0x400 + + +#define rx_pg_fir_err_inj_glbsm_regs_addr 0b101010011 +#define rx_pg_fir_err_inj_glbsm_regs_startbit 4 +#define rx_pg_fir_err_inj_glbsm_regs_width 1 +#define rx_pg_fir_err_inj_glbsm_regs_endbit 4 +#define rx_pg_fir_err_inj_glbsm_regs_shift 11 +#define rx_pg_fir_err_inj_glbsm_regs_mask 0x800 + + +#define rx_pg_fir_err_inj_main_init_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_main_init_sm_startbit 9 +#define rx_pg_fir_err_inj_main_init_sm_width 1 +#define rx_pg_fir_err_inj_main_init_sm_endbit 9 +#define rx_pg_fir_err_inj_main_init_sm_shift 6 +#define rx_pg_fir_err_inj_main_init_sm_mask 0x40 + + +#define rx_pg_fir_err_inj_pg_regs_addr 0b101010011 +#define rx_pg_fir_err_inj_pg_regs_startbit 0 +#define rx_pg_fir_err_inj_pg_regs_width 1 +#define rx_pg_fir_err_inj_pg_regs_endbit 0 +#define rx_pg_fir_err_inj_pg_regs_shift 15 +#define rx_pg_fir_err_inj_pg_regs_mask 0x8000 + + +#define rx_pg_fir_err_inj_recal_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_recal_sm_startbit 5 +#define rx_pg_fir_err_inj_recal_sm_width 1 +#define rx_pg_fir_err_inj_recal_sm_endbit 5 +#define rx_pg_fir_err_inj_recal_sm_shift 10 +#define rx_pg_fir_err_inj_recal_sm_mask 0x400 + + +#define rx_pg_fir_err_inj_rpr_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_rpr_sm_startbit 13 +#define rx_pg_fir_err_inj_rpr_sm_width 1 +#define rx_pg_fir_err_inj_rpr_sm_endbit 13 +#define rx_pg_fir_err_inj_rpr_sm_shift 2 +#define rx_pg_fir_err_inj_rpr_sm_mask 0x4 + + +#define rx_pg_fir_err_inj_rx_servo_sm_addr 0b101010011 +#define rx_pg_fir_err_inj_rx_servo_sm_startbit 11 +#define rx_pg_fir_err_inj_rx_servo_sm_width 1 +#define rx_pg_fir_err_inj_rx_servo_sm_endbit 11 +#define rx_pg_fir_err_inj_rx_servo_sm_shift 4 +#define rx_pg_fir_err_inj_rx_servo_sm_mask 0x10 + + +#define rx_pg_fir_err_inj_rxdsm_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_rxdsm_sm_startbit 15 +#define rx_pg_fir_err_inj_rxdsm_sm_width 1 +#define rx_pg_fir_err_inj_rxdsm_sm_endbit 15 +#define rx_pg_fir_err_inj_rxdsm_sm_shift 0 +#define rx_pg_fir_err_inj_rxdsm_sm_mask 0x1 + + +#define rx_pg_fir_err_inj_set_sls_ln_state_addr 0b101010011 +#define rx_pg_fir_err_inj_set_sls_ln_state_startbit 13 +#define rx_pg_fir_err_inj_set_sls_ln_state_width 1 +#define rx_pg_fir_err_inj_set_sls_ln_state_endbit 13 +#define rx_pg_fir_err_inj_set_sls_ln_state_shift 2 +#define rx_pg_fir_err_inj_set_sls_ln_state_mask 0x4 + + +#define rx_pg_fir_err_inj_sls_enc_snd_msg_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_sls_enc_snd_msg_sm_startbit 2 +#define rx_pg_fir_err_inj_sls_enc_snd_msg_sm_width 1 +#define rx_pg_fir_err_inj_sls_enc_snd_msg_sm_endbit 2 +#define rx_pg_fir_err_inj_sls_enc_snd_msg_sm_shift 13 +#define rx_pg_fir_err_inj_sls_enc_snd_msg_sm_mask 0x2000 + + +#define rx_pg_fir_err_inj_sls_hndshk_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_sls_hndshk_sm_startbit 3 +#define rx_pg_fir_err_inj_sls_hndshk_sm_width 1 +#define rx_pg_fir_err_inj_sls_hndshk_sm_endbit 3 +#define rx_pg_fir_err_inj_sls_hndshk_sm_shift 12 +#define rx_pg_fir_err_inj_sls_hndshk_sm_mask 0x1000 + + +#define rx_pg_fir_err_inj_sls_rcvy_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_sls_rcvy_sm_startbit 4 +#define rx_pg_fir_err_inj_sls_rcvy_sm_width 1 +#define rx_pg_fir_err_inj_sls_rcvy_sm_endbit 4 +#define rx_pg_fir_err_inj_sls_rcvy_sm_shift 11 +#define rx_pg_fir_err_inj_sls_rcvy_sm_mask 0x800 + + +#define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm_startbit 8 +#define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm_width 1 +#define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm_endbit 8 +#define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm_shift 7 +#define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm_mask 0x80 + + +#define rx_pg_fir_err_inj_work_regs_addr 0b101010011 +#define rx_pg_fir_err_inj_work_regs_startbit 12 +#define rx_pg_fir_err_inj_work_regs_width 1 +#define rx_pg_fir_err_inj_work_regs_endbit 12 +#define rx_pg_fir_err_inj_work_regs_shift 3 +#define rx_pg_fir_err_inj_work_regs_mask 0x8 + + +#define rx_pg_fir_err_inj_wtl_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_wtl_sm_startbit 12 +#define rx_pg_fir_err_inj_wtl_sm_width 1 +#define rx_pg_fir_err_inj_wtl_sm_endbit 12 +#define rx_pg_fir_err_inj_wtl_sm_shift 3 +#define rx_pg_fir_err_inj_wtl_sm_mask 0x8 + + +#define rx_pg_fir_err_inj_wtm_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_wtm_sm_startbit 10 +#define rx_pg_fir_err_inj_wtm_sm_width 1 +#define rx_pg_fir_err_inj_wtm_sm_endbit 10 +#define rx_pg_fir_err_inj_wtm_sm_shift 5 +#define rx_pg_fir_err_inj_wtm_sm_mask 0x20 + + +#define rx_pg_fir_err_inj_wtr_sm_addr 0b101100010 +#define rx_pg_fir_err_inj_wtr_sm_startbit 11 +#define rx_pg_fir_err_inj_wtr_sm_width 1 +#define rx_pg_fir_err_inj_wtr_sm_endbit 11 +#define rx_pg_fir_err_inj_wtr_sm_shift 4 +#define rx_pg_fir_err_inj_wtr_sm_mask 0x10 + + +#define rx_pg_fir_err_mask_bist_init_state_addr 0b101010010 +#define rx_pg_fir_err_mask_bist_init_state_startbit 10 +#define rx_pg_fir_err_mask_bist_init_state_width 1 +#define rx_pg_fir_err_mask_bist_init_state_endbit 10 +#define rx_pg_fir_err_mask_bist_init_state_shift 5 +#define rx_pg_fir_err_mask_bist_init_state_mask 0x20 + + +#define rx_pg_fir_err_mask_bist_main_state_addr 0b101010010 +#define rx_pg_fir_err_mask_bist_main_state_startbit 9 +#define rx_pg_fir_err_mask_bist_main_state_width 1 +#define rx_pg_fir_err_mask_bist_main_state_endbit 9 +#define rx_pg_fir_err_mask_bist_main_state_shift 6 +#define rx_pg_fir_err_mask_bist_main_state_mask 0x40 + + +#define rx_pg_fir_err_mask_datasm_regrw_addr 0b101010010 +#define rx_pg_fir_err_mask_datasm_regrw_startbit 7 +#define rx_pg_fir_err_mask_datasm_regrw_width 1 +#define rx_pg_fir_err_mask_datasm_regrw_endbit 7 +#define rx_pg_fir_err_mask_datasm_regrw_shift 8 +#define rx_pg_fir_err_mask_datasm_regrw_mask 0x100 + + +#define rx_pg_fir_err_mask_datasm_regs_addr 0b101010010 +#define rx_pg_fir_err_mask_datasm_regs_startbit 6 +#define rx_pg_fir_err_mask_datasm_regs_width 1 +#define rx_pg_fir_err_mask_datasm_regs_endbit 6 +#define rx_pg_fir_err_mask_datasm_regs_shift 9 +#define rx_pg_fir_err_mask_datasm_regs_mask 0x200 + + +#define rx_pg_fir_err_mask_dsm_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_dsm_sm_startbit 14 +#define rx_pg_fir_err_mask_dsm_sm_width 1 +#define rx_pg_fir_err_mask_dsm_sm_endbit 14 +#define rx_pg_fir_err_mask_dsm_sm_shift 1 +#define rx_pg_fir_err_mask_dsm_sm_mask 0x2 + + +#define rx_pg_fir_err_mask_dyn_recal_hndshk_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_dyn_recal_hndshk_sm_startbit 6 +#define rx_pg_fir_err_mask_dyn_recal_hndshk_sm_width 1 +#define rx_pg_fir_err_mask_dyn_recal_hndshk_sm_endbit 6 +#define rx_pg_fir_err_mask_dyn_recal_hndshk_sm_shift 9 +#define rx_pg_fir_err_mask_dyn_recal_hndshk_sm_mask 0x200 + + +#define rx_pg_fir_err_mask_dyn_rpr_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_dyn_rpr_sm_startbit 0 +#define rx_pg_fir_err_mask_dyn_rpr_sm_width 1 +#define rx_pg_fir_err_mask_dyn_rpr_sm_endbit 0 +#define rx_pg_fir_err_mask_dyn_rpr_sm_shift 15 +#define rx_pg_fir_err_mask_dyn_rpr_sm_mask 0x8000 + + +#define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm_startbit 1 +#define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm_width 1 +#define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm_endbit 1 +#define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm_shift 14 +#define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm_mask 0x4000 + + +#define rx_pg_fir_err_mask_eyeopt_sm_addr 0b101010010 +#define rx_pg_fir_err_mask_eyeopt_sm_startbit 8 +#define rx_pg_fir_err_mask_eyeopt_sm_width 1 +#define rx_pg_fir_err_mask_eyeopt_sm_endbit 8 +#define rx_pg_fir_err_mask_eyeopt_sm_shift 7 +#define rx_pg_fir_err_mask_eyeopt_sm_mask 0x80 + + +#define rx_pg_fir_err_mask_gcrs_ld_sm_addr 0b101010010 +#define rx_pg_fir_err_mask_gcrs_ld_sm_startbit 2 +#define rx_pg_fir_err_mask_gcrs_ld_sm_width 1 +#define rx_pg_fir_err_mask_gcrs_ld_sm_endbit 2 +#define rx_pg_fir_err_mask_gcrs_ld_sm_shift 13 +#define rx_pg_fir_err_mask_gcrs_ld_sm_mask 0x2000 + + +#define rx_pg_fir_err_mask_gcrs_unld_sm_addr 0b101010010 +#define rx_pg_fir_err_mask_gcrs_unld_sm_startbit 3 +#define rx_pg_fir_err_mask_gcrs_unld_sm_width 1 +#define rx_pg_fir_err_mask_gcrs_unld_sm_endbit 3 +#define rx_pg_fir_err_mask_gcrs_unld_sm_shift 12 +#define rx_pg_fir_err_mask_gcrs_unld_sm_mask 0x1000 + + +#define rx_pg_fir_err_mask_glb_cal_snd_msg_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_glb_cal_snd_msg_sm_startbit 7 +#define rx_pg_fir_err_mask_glb_cal_snd_msg_sm_width 1 +#define rx_pg_fir_err_mask_glb_cal_snd_msg_sm_endbit 7 +#define rx_pg_fir_err_mask_glb_cal_snd_msg_sm_shift 8 +#define rx_pg_fir_err_mask_glb_cal_snd_msg_sm_mask 0x100 + + +#define rx_pg_fir_err_mask_glbsm_regrw_addr 0b101010010 +#define rx_pg_fir_err_mask_glbsm_regrw_startbit 5 +#define rx_pg_fir_err_mask_glbsm_regrw_width 1 +#define rx_pg_fir_err_mask_glbsm_regrw_endbit 5 +#define rx_pg_fir_err_mask_glbsm_regrw_shift 10 +#define rx_pg_fir_err_mask_glbsm_regrw_mask 0x400 + + +#define rx_pg_fir_err_mask_glbsm_regs_addr 0b101010010 +#define rx_pg_fir_err_mask_glbsm_regs_startbit 4 +#define rx_pg_fir_err_mask_glbsm_regs_width 1 +#define rx_pg_fir_err_mask_glbsm_regs_endbit 4 +#define rx_pg_fir_err_mask_glbsm_regs_shift 11 +#define rx_pg_fir_err_mask_glbsm_regs_mask 0x800 + + +#define rx_pg_fir_err_mask_main_init_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_main_init_sm_startbit 9 +#define rx_pg_fir_err_mask_main_init_sm_width 1 +#define rx_pg_fir_err_mask_main_init_sm_endbit 9 +#define rx_pg_fir_err_mask_main_init_sm_shift 6 +#define rx_pg_fir_err_mask_main_init_sm_mask 0x40 + + +#define rx_pg_fir_err_mask_recal_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_recal_sm_startbit 5 +#define rx_pg_fir_err_mask_recal_sm_width 1 +#define rx_pg_fir_err_mask_recal_sm_endbit 5 +#define rx_pg_fir_err_mask_recal_sm_shift 10 +#define rx_pg_fir_err_mask_recal_sm_mask 0x400 + + +#define rx_pg_fir_err_mask_rpr_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_rpr_sm_startbit 13 +#define rx_pg_fir_err_mask_rpr_sm_width 1 +#define rx_pg_fir_err_mask_rpr_sm_endbit 13 +#define rx_pg_fir_err_mask_rpr_sm_shift 2 +#define rx_pg_fir_err_mask_rpr_sm_mask 0x4 + + +#define rx_pg_fir_err_mask_rx_servo_sm_addr 0b101010010 +#define rx_pg_fir_err_mask_rx_servo_sm_startbit 11 +#define rx_pg_fir_err_mask_rx_servo_sm_width 1 +#define rx_pg_fir_err_mask_rx_servo_sm_endbit 11 +#define rx_pg_fir_err_mask_rx_servo_sm_shift 4 +#define rx_pg_fir_err_mask_rx_servo_sm_mask 0x10 + + +#define rx_pg_fir_err_mask_rxdsm_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_rxdsm_sm_startbit 15 +#define rx_pg_fir_err_mask_rxdsm_sm_width 1 +#define rx_pg_fir_err_mask_rxdsm_sm_endbit 15 +#define rx_pg_fir_err_mask_rxdsm_sm_shift 0 +#define rx_pg_fir_err_mask_rxdsm_sm_mask 0x1 + + +#define rx_pg_fir_err_mask_set_sls_ln_state_addr 0b101010010 +#define rx_pg_fir_err_mask_set_sls_ln_state_startbit 13 +#define rx_pg_fir_err_mask_set_sls_ln_state_width 1 +#define rx_pg_fir_err_mask_set_sls_ln_state_endbit 13 +#define rx_pg_fir_err_mask_set_sls_ln_state_shift 2 +#define rx_pg_fir_err_mask_set_sls_ln_state_mask 0x4 + + +#define rx_pg_fir_err_mask_sls_enc_snd_msg_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_sls_enc_snd_msg_sm_startbit 2 +#define rx_pg_fir_err_mask_sls_enc_snd_msg_sm_width 1 +#define rx_pg_fir_err_mask_sls_enc_snd_msg_sm_endbit 2 +#define rx_pg_fir_err_mask_sls_enc_snd_msg_sm_shift 13 +#define rx_pg_fir_err_mask_sls_enc_snd_msg_sm_mask 0x2000 + + +#define rx_pg_fir_err_mask_sls_hndshk_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_sls_hndshk_sm_startbit 3 +#define rx_pg_fir_err_mask_sls_hndshk_sm_width 1 +#define rx_pg_fir_err_mask_sls_hndshk_sm_endbit 3 +#define rx_pg_fir_err_mask_sls_hndshk_sm_shift 12 +#define rx_pg_fir_err_mask_sls_hndshk_sm_mask 0x1000 + + +#define rx_pg_fir_err_mask_sls_rcvy_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_sls_rcvy_sm_startbit 4 +#define rx_pg_fir_err_mask_sls_rcvy_sm_width 1 +#define rx_pg_fir_err_mask_sls_rcvy_sm_endbit 4 +#define rx_pg_fir_err_mask_sls_rcvy_sm_shift 11 +#define rx_pg_fir_err_mask_sls_rcvy_sm_mask 0x800 + + +#define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm_startbit 8 +#define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm_width 1 +#define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm_endbit 8 +#define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm_shift 7 +#define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm_mask 0x80 + + +#define rx_pg_fir_err_mask_work_regs_addr 0b101010010 +#define rx_pg_fir_err_mask_work_regs_startbit 12 +#define rx_pg_fir_err_mask_work_regs_width 1 +#define rx_pg_fir_err_mask_work_regs_endbit 12 +#define rx_pg_fir_err_mask_work_regs_shift 3 +#define rx_pg_fir_err_mask_work_regs_mask 0x8 + + +#define rx_pg_fir_err_mask_wtl_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_wtl_sm_startbit 12 +#define rx_pg_fir_err_mask_wtl_sm_width 1 +#define rx_pg_fir_err_mask_wtl_sm_endbit 12 +#define rx_pg_fir_err_mask_wtl_sm_shift 3 +#define rx_pg_fir_err_mask_wtl_sm_mask 0x8 + + +#define rx_pg_fir_err_mask_wtm_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_wtm_sm_startbit 10 +#define rx_pg_fir_err_mask_wtm_sm_width 1 +#define rx_pg_fir_err_mask_wtm_sm_endbit 10 +#define rx_pg_fir_err_mask_wtm_sm_shift 5 +#define rx_pg_fir_err_mask_wtm_sm_mask 0x20 + + +#define rx_pg_fir_err_mask_wtr_sm_addr 0b101100001 +#define rx_pg_fir_err_mask_wtr_sm_startbit 11 +#define rx_pg_fir_err_mask_wtr_sm_width 1 +#define rx_pg_fir_err_mask_wtr_sm_endbit 11 +#define rx_pg_fir_err_mask_wtr_sm_shift 4 +#define rx_pg_fir_err_mask_wtr_sm_mask 0x10 + + +#define rx_pl_fir_err_dac_regs_addr 0b001000001 +#define rx_pl_fir_err_dac_regs_startbit 2 +#define rx_pl_fir_err_dac_regs_width 1 +#define rx_pl_fir_err_dac_regs_endbit 2 +#define rx_pl_fir_err_dac_regs_shift 13 +#define rx_pl_fir_err_dac_regs_mask 0x2000 + + +#define rx_pl_fir_err_ddc_sm_addr 0b001000001 +#define rx_pl_fir_err_ddc_sm_startbit 1 +#define rx_pl_fir_err_ddc_sm_width 1 +#define rx_pl_fir_err_ddc_sm_endbit 1 +#define rx_pl_fir_err_ddc_sm_shift 14 +#define rx_pl_fir_err_ddc_sm_mask 0x4000 + + +#define rx_pl_fir_err_inj_dac_regs_addr 0b001000011 +#define rx_pl_fir_err_inj_dac_regs_startbit 2 +#define rx_pl_fir_err_inj_dac_regs_width 1 +#define rx_pl_fir_err_inj_dac_regs_endbit 2 +#define rx_pl_fir_err_inj_dac_regs_shift 13 +#define rx_pl_fir_err_inj_dac_regs_mask 0x2000 + + +#define rx_pl_fir_err_inj_ddc_sm_addr 0b001000011 +#define rx_pl_fir_err_inj_ddc_sm_startbit 1 +#define rx_pl_fir_err_inj_ddc_sm_width 1 +#define rx_pl_fir_err_inj_ddc_sm_endbit 1 +#define rx_pl_fir_err_inj_ddc_sm_shift 14 +#define rx_pl_fir_err_inj_ddc_sm_mask 0x4000 + + +#define rx_pl_fir_err_inj_full_reg_addr 0b001000011 +#define rx_pl_fir_err_inj_full_reg_startbit 0 +#define rx_pl_fir_err_inj_full_reg_width 16 +#define rx_pl_fir_err_inj_full_reg_endbit 15 +#define rx_pl_fir_err_inj_full_reg_shift 0 +#define rx_pl_fir_err_inj_full_reg_mask 0xffff + + +#define rx_pl_fir_err_inj_pl_regs_addr 0b001000011 +#define rx_pl_fir_err_inj_pl_regs_startbit 0 +#define rx_pl_fir_err_inj_pl_regs_width 1 +#define rx_pl_fir_err_inj_pl_regs_endbit 0 +#define rx_pl_fir_err_inj_pl_regs_shift 15 +#define rx_pl_fir_err_inj_pl_regs_mask 0x8000 + + +#define rx_pl_fir_err_mask_addr 0b101010010 +#define rx_pl_fir_err_mask_startbit 14 +#define rx_pl_fir_err_mask_width 1 +#define rx_pl_fir_err_mask_endbit 14 +#define rx_pl_fir_err_mask_shift 1 +#define rx_pl_fir_err_mask_mask 0x2 + + +#define rx_pl_fir_err_mask_dac_regs_addr 0b001000010 +#define rx_pl_fir_err_mask_dac_regs_startbit 2 +#define rx_pl_fir_err_mask_dac_regs_width 1 +#define rx_pl_fir_err_mask_dac_regs_endbit 2 +#define rx_pl_fir_err_mask_dac_regs_shift 13 +#define rx_pl_fir_err_mask_dac_regs_mask 0x2000 + + +#define rx_pl_fir_err_mask_ddc_sm_addr 0b001000010 +#define rx_pl_fir_err_mask_ddc_sm_startbit 1 +#define rx_pl_fir_err_mask_ddc_sm_width 1 +#define rx_pl_fir_err_mask_ddc_sm_endbit 1 +#define rx_pl_fir_err_mask_ddc_sm_shift 14 +#define rx_pl_fir_err_mask_ddc_sm_mask 0x4000 + + +#define rx_pl_fir_err_mask_pl_regs_addr 0b001000010 +#define rx_pl_fir_err_mask_pl_regs_startbit 0 +#define rx_pl_fir_err_mask_pl_regs_width 1 +#define rx_pl_fir_err_mask_pl_regs_endbit 0 +#define rx_pl_fir_err_mask_pl_regs_shift 15 +#define rx_pl_fir_err_mask_pl_regs_mask 0x8000 + + +#define rx_pl_fir_err_pl_regs_addr 0b001000001 +#define rx_pl_fir_err_pl_regs_startbit 0 +#define rx_pl_fir_err_pl_regs_width 1 +#define rx_pl_fir_err_pl_regs_endbit 0 +#define rx_pl_fir_err_pl_regs_shift 15 +#define rx_pl_fir_err_pl_regs_mask 0x8000 + + +#define rx_pl_fir_errs_full_reg_addr 0b001000001 +#define rx_pl_fir_errs_full_reg_startbit 0 +#define rx_pl_fir_errs_full_reg_width 16 +#define rx_pl_fir_errs_full_reg_endbit 15 +#define rx_pl_fir_errs_full_reg_shift 0 +#define rx_pl_fir_errs_full_reg_mask 0xffff + + +#define rx_pl_fir_errs_mask_full_reg_addr 0b001000010 +#define rx_pl_fir_errs_mask_full_reg_startbit 0 +#define rx_pl_fir_errs_mask_full_reg_width 16 +#define rx_pl_fir_errs_mask_full_reg_endbit 15 +#define rx_pl_fir_errs_mask_full_reg_shift 0 +#define rx_pl_fir_errs_mask_full_reg_mask 0xffff + + +#define rx_pr_l_r_edge_a_alias_addr 0b001001111 +#define rx_pr_l_r_edge_a_alias_startbit 0 +#define rx_pr_l_r_edge_a_alias_width 12 +#define rx_pr_l_r_edge_a_alias_endbit 11 +#define rx_pr_l_r_edge_a_alias_shift 4 +#define rx_pr_l_r_edge_a_alias_mask 0xfff0 + + +#define rx_pr_l_r_edge_b_alias_addr 0b001100011 +#define rx_pr_l_r_edge_b_alias_startbit 0 +#define rx_pr_l_r_edge_b_alias_width 12 +#define rx_pr_l_r_edge_b_alias_endbit 11 +#define rx_pr_l_r_edge_b_alias_shift 4 +#define rx_pr_l_r_edge_b_alias_mask 0xfff0 + + +#define rx_rc_step_cntl2_edi_alias_addr 0b100101110 +#define rx_rc_step_cntl2_edi_alias_startbit 0 +#define rx_rc_step_cntl2_edi_alias_width 16 +#define rx_rc_step_cntl2_edi_alias_endbit 15 +#define rx_rc_step_cntl2_edi_alias_shift 0 +#define rx_rc_step_cntl2_edi_alias_mask 0xffff + + +#define rx_rc_step_cntl2_opt_alias_addr 0b100101110 +#define rx_rc_step_cntl2_opt_alias_startbit 0 +#define rx_rc_step_cntl2_opt_alias_width 4 +#define rx_rc_step_cntl2_opt_alias_endbit 3 +#define rx_rc_step_cntl2_opt_alias_shift 12 +#define rx_rc_step_cntl2_opt_alias_mask 0xf000 + + +#define rx_rc_step_cntl_edi_alias_addr 0b100010111 +#define rx_rc_step_cntl_edi_alias_startbit 0 +#define rx_rc_step_cntl_edi_alias_width 14 +#define rx_rc_step_cntl_edi_alias_endbit 13 +#define rx_rc_step_cntl_edi_alias_shift 2 +#define rx_rc_step_cntl_edi_alias_mask 0xfffc + + +#define rx_rc_step_cntl_opt_alias_addr 0b100010111 +#define rx_rc_step_cntl_opt_alias_startbit 0 +#define rx_rc_step_cntl_opt_alias_width 11 +#define rx_rc_step_cntl_opt_alias_endbit 10 +#define rx_rc_step_cntl_opt_alias_shift 5 +#define rx_rc_step_cntl_opt_alias_mask 0xffe0 + + +#define rx_sls_rcvy_ip_addr 0b101001110 +#define rx_sls_rcvy_ip_startbit 1 +#define rx_sls_rcvy_ip_width 1 +#define rx_sls_rcvy_ip_endbit 1 +#define rx_sls_rcvy_ip_shift 14 +#define rx_sls_rcvy_ip_mask 0x4000 + + +#define rx_start_wderf_alias_addr 0b100111110 +#define rx_start_wderf_alias_startbit 0 +#define rx_start_wderf_alias_width 5 +#define rx_start_wderf_alias_endbit 4 +#define rx_start_wderf_alias_shift 11 +#define rx_start_wderf_alias_mask 0xf800 + + +#define rx_wderf_done_alias_addr 0b101000111 +#define rx_wderf_done_alias_startbit 0 +#define rx_wderf_done_alias_width 5 +#define rx_wderf_done_alias_endbit 4 +#define rx_wderf_done_alias_shift 11 +#define rx_wderf_done_alias_mask 0xf800 + + +#define rx_wderf_failed_alias_addr 0b101000111 +#define rx_wderf_failed_alias_startbit 8 +#define rx_wderf_failed_alias_width 5 +#define rx_wderf_failed_alias_endbit 12 +#define rx_wderf_failed_alias_shift 3 +#define rx_wderf_failed_alias_mask 0xf8 + + +#define rx_wt_clk_lane_status_alias_addr 0b101001011 +#define rx_wt_clk_lane_status_alias_startbit 1 +#define rx_wt_clk_lane_status_alias_width 4 +#define rx_wt_clk_lane_status_alias_endbit 4 +#define rx_wt_clk_lane_status_alias_shift 11 +#define rx_wt_clk_lane_status_alias_mask 0x7800 + + +#define rx_wt_lane_status_alias_addr 0b001110001 +#define rx_wt_lane_status_alias_startbit 5 +#define rx_wt_lane_status_alias_width 4 +#define rx_wt_lane_status_alias_endbit 8 +#define rx_wt_lane_status_alias_shift 7 +#define rx_wt_lane_status_alias_mask 0x780 + + +#define tx_bad_lane_cntr_addr 0b101001110 +#define tx_bad_lane_cntr_startbit 5 +#define tx_bad_lane_cntr_width 3 +#define tx_bad_lane_cntr_endbit 7 +#define tx_bad_lane_cntr_shift 8 +#define tx_bad_lane_cntr_mask 0x700 + + +#define tx_mode1_pl_full_reg_addr 0b010000000 +#define tx_mode1_pl_full_reg_startbit 0 +#define tx_mode1_pl_full_reg_width 16 +#define tx_mode1_pl_full_reg_endbit 15 +#define tx_mode1_pl_full_reg_shift 0 +#define tx_mode1_pl_full_reg_mask 0xffff + + +#define tx_pg_fir_err_inj_bist_addr 0b110100011 +#define tx_pg_fir_err_inj_bist_startbit 5 +#define tx_pg_fir_err_inj_bist_width 1 +#define tx_pg_fir_err_inj_bist_endbit 5 +#define tx_pg_fir_err_inj_bist_shift 10 +#define tx_pg_fir_err_inj_bist_mask 0x400 + + +#define tx_pg_fir_err_inj_ctl_regs_addr 0b110100011 +#define tx_pg_fir_err_inj_ctl_regs_startbit 4 +#define tx_pg_fir_err_inj_ctl_regs_width 1 +#define tx_pg_fir_err_inj_ctl_regs_endbit 4 +#define tx_pg_fir_err_inj_ctl_regs_shift 11 +#define tx_pg_fir_err_inj_ctl_regs_mask 0x800 + + +#define tx_pg_fir_err_inj_full_reg_addr 0b110100011 +#define tx_pg_fir_err_inj_full_reg_startbit 0 +#define tx_pg_fir_err_inj_full_reg_width 16 +#define tx_pg_fir_err_inj_full_reg_endbit 15 +#define tx_pg_fir_err_inj_full_reg_shift 0 +#define tx_pg_fir_err_inj_full_reg_mask 0xffff + + +#define tx_pg_fir_err_inj_gcr_buff_addr 0b110100011 +#define tx_pg_fir_err_inj_gcr_buff_startbit 1 +#define tx_pg_fir_err_inj_gcr_buff_width 1 +#define tx_pg_fir_err_inj_gcr_buff_endbit 1 +#define tx_pg_fir_err_inj_gcr_buff_shift 14 +#define tx_pg_fir_err_inj_gcr_buff_mask 0x4000 + + +#define tx_pg_fir_err_inj_gcrs_ld_sm_addr 0b110100011 +#define tx_pg_fir_err_inj_gcrs_ld_sm_startbit 2 +#define tx_pg_fir_err_inj_gcrs_ld_sm_width 1 +#define tx_pg_fir_err_inj_gcrs_ld_sm_endbit 2 +#define tx_pg_fir_err_inj_gcrs_ld_sm_shift 13 +#define tx_pg_fir_err_inj_gcrs_ld_sm_mask 0x2000 + + +#define tx_pg_fir_err_inj_gcrs_unld_sm_addr 0b110100011 +#define tx_pg_fir_err_inj_gcrs_unld_sm_startbit 3 +#define tx_pg_fir_err_inj_gcrs_unld_sm_width 1 +#define tx_pg_fir_err_inj_gcrs_unld_sm_endbit 3 +#define tx_pg_fir_err_inj_gcrs_unld_sm_shift 12 +#define tx_pg_fir_err_inj_gcrs_unld_sm_mask 0x1000 + + +#define tx_pg_fir_err_inj_tx_sm_regs_addr 0b110100011 +#define tx_pg_fir_err_inj_tx_sm_regs_startbit 0 +#define tx_pg_fir_err_inj_tx_sm_regs_width 1 +#define tx_pg_fir_err_inj_tx_sm_regs_endbit 0 +#define tx_pg_fir_err_inj_tx_sm_regs_shift 15 +#define tx_pg_fir_err_inj_tx_sm_regs_mask 0x8000 + + +#define tx_pg_fir_err_mask_bist_addr 0b110100001 +#define tx_pg_fir_err_mask_bist_startbit 5 +#define tx_pg_fir_err_mask_bist_width 1 +#define tx_pg_fir_err_mask_bist_endbit 5 +#define tx_pg_fir_err_mask_bist_shift 10 +#define tx_pg_fir_err_mask_bist_mask 0x400 + + +#define tx_pg_fir_err_mask_ctl_regs_addr 0b110100001 +#define tx_pg_fir_err_mask_ctl_regs_startbit 4 +#define tx_pg_fir_err_mask_ctl_regs_width 1 +#define tx_pg_fir_err_mask_ctl_regs_endbit 4 +#define tx_pg_fir_err_mask_ctl_regs_shift 11 +#define tx_pg_fir_err_mask_ctl_regs_mask 0x800 + + +#define tx_pg_fir_err_mask_full_reg_addr 0b110100001 +#define tx_pg_fir_err_mask_full_reg_startbit 0 +#define tx_pg_fir_err_mask_full_reg_width 16 +#define tx_pg_fir_err_mask_full_reg_endbit 15 +#define tx_pg_fir_err_mask_full_reg_shift 0 +#define tx_pg_fir_err_mask_full_reg_mask 0xffff + + +#define tx_pg_fir_err_mask_gcr_buff_addr 0b110100001 +#define tx_pg_fir_err_mask_gcr_buff_startbit 1 +#define tx_pg_fir_err_mask_gcr_buff_width 1 +#define tx_pg_fir_err_mask_gcr_buff_endbit 1 +#define tx_pg_fir_err_mask_gcr_buff_shift 14 +#define tx_pg_fir_err_mask_gcr_buff_mask 0x4000 + + +#define tx_pg_fir_err_mask_gcrs_ld_sm_addr 0b110100001 +#define tx_pg_fir_err_mask_gcrs_ld_sm_startbit 2 +#define tx_pg_fir_err_mask_gcrs_ld_sm_width 1 +#define tx_pg_fir_err_mask_gcrs_ld_sm_endbit 2 +#define tx_pg_fir_err_mask_gcrs_ld_sm_shift 13 +#define tx_pg_fir_err_mask_gcrs_ld_sm_mask 0x2000 + + +#define tx_pg_fir_err_mask_gcrs_unld_sm_addr 0b110100001 +#define tx_pg_fir_err_mask_gcrs_unld_sm_startbit 3 +#define tx_pg_fir_err_mask_gcrs_unld_sm_width 1 +#define tx_pg_fir_err_mask_gcrs_unld_sm_endbit 3 +#define tx_pg_fir_err_mask_gcrs_unld_sm_shift 12 +#define tx_pg_fir_err_mask_gcrs_unld_sm_mask 0x1000 + + +#define tx_pg_fir_err_mask_tx_sm_regs_addr 0b110100001 +#define tx_pg_fir_err_mask_tx_sm_regs_startbit 0 +#define tx_pg_fir_err_mask_tx_sm_regs_width 1 +#define tx_pg_fir_err_mask_tx_sm_regs_endbit 0 +#define tx_pg_fir_err_mask_tx_sm_regs_shift 15 +#define tx_pg_fir_err_mask_tx_sm_regs_mask 0x8000 + + +#define tx_pg_fir_errs_full_reg_addr 0b110100000 +#define tx_pg_fir_errs_full_reg_startbit 0 +#define tx_pg_fir_errs_full_reg_width 16 +#define tx_pg_fir_errs_full_reg_endbit 15 +#define tx_pg_fir_errs_full_reg_shift 0 +#define tx_pg_fir_errs_full_reg_mask 0xffff + + +#define tx_pl_fir_err_inj_full_reg_addr 0b010000110 +#define tx_pl_fir_err_inj_full_reg_startbit 0 +#define tx_pl_fir_err_inj_full_reg_width 16 +#define tx_pl_fir_err_inj_full_reg_endbit 15 +#define tx_pl_fir_err_inj_full_reg_shift 0 +#define tx_pl_fir_err_inj_full_reg_mask 0xffff + + +#define tx_pl_fir_err_inj_pl_regs_addr 0b010000110 +#define tx_pl_fir_err_inj_pl_regs_startbit 0 +#define tx_pl_fir_err_inj_pl_regs_width 1 +#define tx_pl_fir_err_inj_pl_regs_endbit 0 +#define tx_pl_fir_err_inj_pl_regs_shift 15 +#define tx_pl_fir_err_inj_pl_regs_mask 0x8000 + + +#define tx_pl_fir_err_mask_pl_regs_addr 0b010000101 +#define tx_pl_fir_err_mask_pl_regs_startbit 0 +#define tx_pl_fir_err_mask_pl_regs_width 1 +#define tx_pl_fir_err_mask_pl_regs_endbit 0 +#define tx_pl_fir_err_mask_pl_regs_shift 15 +#define tx_pl_fir_err_mask_pl_regs_mask 0x8000 + + +#define tx_pl_fir_err_pl_regs_addr 0b010000100 +#define tx_pl_fir_err_pl_regs_startbit 0 +#define tx_pl_fir_err_pl_regs_width 1 +#define tx_pl_fir_err_pl_regs_endbit 0 +#define tx_pl_fir_err_pl_regs_shift 15 +#define tx_pl_fir_err_pl_regs_mask 0x8000 + + +#define tx_pl_fir_errs_full_reg_addr 0b010000100 +#define tx_pl_fir_errs_full_reg_startbit 0 +#define tx_pl_fir_errs_full_reg_width 16 +#define tx_pl_fir_errs_full_reg_endbit 15 +#define tx_pl_fir_errs_full_reg_shift 0 +#define tx_pl_fir_errs_full_reg_mask 0xffff + + +#define tx_pl_fir_errs_mask_full_reg_addr 0b010000101 +#define tx_pl_fir_errs_mask_full_reg_startbit 0 +#define tx_pl_fir_errs_mask_full_reg_width 16 +#define tx_pl_fir_errs_mask_full_reg_endbit 15 +#define tx_pl_fir_errs_mask_full_reg_shift 0 +#define tx_pl_fir_errs_mask_full_reg_mask 0xffff diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_opt_reg_const_pkg.h b/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_opt_reg_const_pkg.h new file mode 100644 index 00000000..6f5fe3f1 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_opt_reg_const_pkg.h @@ -0,0 +1,1132 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/ippe/ioa/ppe_opt_reg_const_pkg.h $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//- *!*************************************************************************** +//- *! FILENAME : ppe_reg_const_pkg.h +//- *! TITLE : PPE Register Constants Package Header +//- *! DESCRIPTION : Constants containing register info for use by PPE +//- *! +//- *! +//- *! OWNER NAME : John Rell III Email: jgrell@us.ibm.com +//- *! BACKUP NAME : Mike Spear Email: mspear@us.ibm.com +//- *! +//- *!*************************************************************************** + + +#define rx_a_bank_controls_addr 0b000000001 +#define rx_a_bank_controls_startbit 0 +#define rx_a_bank_controls_width 6 +#define rx_a_bank_controls_endbit 5 +#define rx_a_bank_controls_shift 10 +#define rx_a_bank_controls_mask 0xfc00 + + +#define rx_a_ctle_coarse_addr 0b000000110 +#define rx_a_ctle_coarse_startbit 0 +#define rx_a_ctle_coarse_width 5 +#define rx_a_ctle_coarse_endbit 4 +#define rx_a_ctle_coarse_shift 11 +#define rx_a_ctle_coarse_mask 0xf800 + + +#define rx_ac_coupled_addr 0b100110001 +#define rx_ac_coupled_startbit 5 +#define rx_ac_coupled_width 1 +#define rx_ac_coupled_endbit 5 +#define rx_ac_coupled_shift 10 +#define rx_ac_coupled_mask 0x400 + + +#define rx_b_bad_dfe_conv_addr 0b001110010 +#define rx_b_bad_dfe_conv_startbit 1 +#define rx_b_bad_dfe_conv_width 1 +#define rx_b_bad_dfe_conv_endbit 1 +#define rx_b_bad_dfe_conv_shift 14 +#define rx_b_bad_dfe_conv_mask 0x4000 + + +#define rx_b_bank_controls_addr 0b000000001 +#define rx_b_bank_controls_startbit 10 +#define rx_b_bank_controls_width 6 +#define rx_b_bank_controls_endbit 15 +#define rx_b_bank_controls_shift 0 +#define rx_b_bank_controls_mask 0x3f + + +#define rx_b_bist_en_addr 0b100000010 +#define rx_b_bist_en_startbit 10 +#define rx_b_bist_en_width 1 +#define rx_b_bist_en_endbit 10 +#define rx_b_bist_en_shift 5 +#define rx_b_bist_en_mask 0x20 + + +#define rx_b_controls_addr 0b000010000 +#define rx_b_controls_startbit 0 +#define rx_b_controls_width 5 +#define rx_b_controls_endbit 4 +#define rx_b_controls_shift 11 +#define rx_b_controls_mask 0xf800 + + +#define rx_b_ctle_coarse_addr 0b000010100 +#define rx_b_ctle_coarse_startbit 0 +#define rx_b_ctle_coarse_width 5 +#define rx_b_ctle_coarse_endbit 4 +#define rx_b_ctle_coarse_shift 11 +#define rx_b_ctle_coarse_mask 0xf800 + + +#define rx_b_ctle_gain_addr 0b000010100 +#define rx_b_ctle_gain_startbit 5 +#define rx_b_ctle_gain_width 4 +#define rx_b_ctle_gain_endbit 8 +#define rx_b_ctle_gain_shift 7 +#define rx_b_ctle_gain_mask 0x780 + + +#define rx_b_even_integ_fine_gain_addr 0b000010011 +#define rx_b_even_integ_fine_gain_startbit 4 +#define rx_b_even_integ_fine_gain_width 5 +#define rx_b_even_integ_fine_gain_endbit 8 +#define rx_b_even_integ_fine_gain_shift 7 +#define rx_b_even_integ_fine_gain_mask 0xf80 + + +#define rx_b_h1ap_at_limit_addr 0b001110010 +#define rx_b_h1ap_at_limit_startbit 3 +#define rx_b_h1ap_at_limit_width 1 +#define rx_b_h1ap_at_limit_endbit 3 +#define rx_b_h1ap_at_limit_shift 12 +#define rx_b_h1ap_at_limit_mask 0x1000 + + +#define rx_b_h1e_val_addr 0b000010101 +#define rx_b_h1e_val_startbit 0 +#define rx_b_h1e_val_width 7 +#define rx_b_h1e_val_endbit 6 +#define rx_b_h1e_val_shift 9 +#define rx_b_h1e_val_mask 0xfe00 + + +#define rx_b_h1o_val_addr 0b000010101 +#define rx_b_h1o_val_startbit 8 +#define rx_b_h1o_val_width 7 +#define rx_b_h1o_val_endbit 14 +#define rx_b_h1o_val_shift 1 +#define rx_b_h1o_val_mask 0xfe + + +#define rx_b_integ_coarse_gain_addr 0b000010011 +#define rx_b_integ_coarse_gain_startbit 0 +#define rx_b_integ_coarse_gain_width 4 +#define rx_b_integ_coarse_gain_endbit 3 +#define rx_b_integ_coarse_gain_shift 12 +#define rx_b_integ_coarse_gain_mask 0xf000 + + +#define rx_b_odd_integ_fine_gain_addr 0b000010011 +#define rx_b_odd_integ_fine_gain_startbit 9 +#define rx_b_odd_integ_fine_gain_width 5 +#define rx_b_odd_integ_fine_gain_endbit 13 +#define rx_b_odd_integ_fine_gain_shift 2 +#define rx_b_odd_integ_fine_gain_mask 0x7c + + +#define rx_b_offset_e0_addr 0b000010001 +#define rx_b_offset_e0_startbit 0 +#define rx_b_offset_e0_width 7 +#define rx_b_offset_e0_endbit 6 +#define rx_b_offset_e0_shift 9 +#define rx_b_offset_e0_mask 0xfe00 + + +#define rx_b_offset_e1_addr 0b000010001 +#define rx_b_offset_e1_startbit 8 +#define rx_b_offset_e1_width 7 +#define rx_b_offset_e1_endbit 14 +#define rx_b_offset_e1_shift 1 +#define rx_b_offset_e1_mask 0xfe + + +#define rx_b_offset_o0_addr 0b000010010 +#define rx_b_offset_o0_startbit 0 +#define rx_b_offset_o0_width 7 +#define rx_b_offset_o0_endbit 6 +#define rx_b_offset_o0_shift 9 +#define rx_b_offset_o0_mask 0xfe00 + + +#define rx_b_offset_o1_addr 0b000010010 +#define rx_b_offset_o1_startbit 8 +#define rx_b_offset_o1_width 7 +#define rx_b_offset_o1_endbit 14 +#define rx_b_offset_o1_shift 1 +#define rx_b_offset_o1_mask 0xfe + + +#define rx_b_path_off_even_addr 0b001110100 +#define rx_b_path_off_even_startbit 0 +#define rx_b_path_off_even_width 6 +#define rx_b_path_off_even_endbit 5 +#define rx_b_path_off_even_shift 10 +#define rx_b_path_off_even_mask 0xfc00 + + +#define rx_b_path_off_odd_addr 0b001110100 +#define rx_b_path_off_odd_startbit 6 +#define rx_b_path_off_odd_width 6 +#define rx_b_path_off_odd_endbit 11 +#define rx_b_path_off_odd_shift 4 +#define rx_b_path_off_odd_mask 0x3f0 + + +#define rx_b_pr_dfe_clkadj_addr 0b001100011 +#define rx_b_pr_dfe_clkadj_startbit 12 +#define rx_b_pr_dfe_clkadj_width 4 +#define rx_b_pr_dfe_clkadj_endbit 15 +#define rx_b_pr_dfe_clkadj_shift 0 +#define rx_b_pr_dfe_clkadj_mask 0xf + + +#define rx_bank_sel_a_addr 0b001001000 +#define rx_bank_sel_a_startbit 3 +#define rx_bank_sel_a_width 1 +#define rx_bank_sel_a_endbit 3 +#define rx_bank_sel_a_shift 12 +#define rx_bank_sel_a_mask 0x1000 + + +#define rx_bist_err_a_addr 0b001110001 +#define rx_bist_err_a_startbit 13 +#define rx_bist_err_a_width 1 +#define rx_bist_err_a_endbit 13 +#define rx_bist_err_a_shift 2 +#define rx_bist_err_a_mask 0x4 + + +#define rx_bist_err_b_addr 0b001110001 +#define rx_bist_err_b_startbit 14 +#define rx_bist_err_b_width 1 +#define rx_bist_err_b_endbit 14 +#define rx_bist_err_b_shift 1 +#define rx_bist_err_b_mask 0x2 + + +#define rx_bist_err_e_addr 0b001110001 +#define rx_bist_err_e_startbit 15 +#define rx_bist_err_e_width 1 +#define rx_bist_err_e_endbit 15 +#define rx_bist_err_e_shift 0 +#define rx_bist_err_e_mask 0x1 + + +#define rx_bist_ll_err_addr 0b100101011 +#define rx_bist_ll_err_startbit 2 +#define rx_bist_ll_err_width 1 +#define rx_bist_ll_err_endbit 2 +#define rx_bist_ll_err_shift 13 +#define rx_bist_ll_err_mask 0x2000 + + +#define rx_bist_ll_test_en_addr 0b100100011 +#define rx_bist_ll_test_en_startbit 15 +#define rx_bist_ll_test_en_width 1 +#define rx_bist_ll_test_en_endbit 15 +#define rx_bist_ll_test_en_shift 0 +#define rx_bist_ll_test_en_mask 0x1 + + +#define rx_bist_pipe_data_shift_addr 0b001001000 +#define rx_bist_pipe_data_shift_startbit 9 +#define rx_bist_pipe_data_shift_width 1 +#define rx_bist_pipe_data_shift_endbit 9 +#define rx_bist_pipe_data_shift_shift 6 +#define rx_bist_pipe_data_shift_mask 0x40 + + +#define rx_bistclk_en_addr 0b100000010 +#define rx_bistclk_en_startbit 12 +#define rx_bistclk_en_width 2 +#define rx_bistclk_en_endbit 13 +#define rx_bistclk_en_shift 2 +#define rx_bistclk_en_mask 0xc + + +#define rx_cfg_lte_mc_addr 0b000000000 +#define rx_cfg_lte_mc_startbit 12 +#define rx_cfg_lte_mc_width 4 +#define rx_cfg_lte_mc_endbit 15 +#define rx_cfg_lte_mc_shift 0 +#define rx_cfg_lte_mc_mask 0xf + + +#define rx_clr_run_dccal_addr 0b001100110 +#define rx_clr_run_dccal_startbit 3 +#define rx_clr_run_dccal_width 1 +#define rx_clr_run_dccal_endbit 3 +#define rx_clr_run_dccal_shift 12 +#define rx_clr_run_dccal_mask 0x1000 + + +#define rx_clr_run_lane_addr 0b001100110 +#define rx_clr_run_lane_startbit 1 +#define rx_clr_run_lane_width 1 +#define rx_clr_run_lane_endbit 1 +#define rx_clr_run_lane_shift 14 +#define rx_clr_run_lane_mask 0x4000 + + +#define rx_dccal_done_addr 0b001100101 +#define rx_dccal_done_startbit 1 +#define rx_dccal_done_width 1 +#define rx_dccal_done_endbit 1 +#define rx_dccal_done_shift 14 +#define rx_dccal_done_mask 0x4000 + + +#define rx_decouple_edge_a_addr 0b001000100 +#define rx_decouple_edge_a_startbit 2 +#define rx_decouple_edge_a_width 1 +#define rx_decouple_edge_a_endbit 2 +#define rx_decouple_edge_a_shift 13 +#define rx_decouple_edge_a_mask 0x2000 + + +#define rx_decouple_edge_b_addr 0b001000100 +#define rx_decouple_edge_b_startbit 3 +#define rx_decouple_edge_b_width 1 +#define rx_decouple_edge_b_endbit 3 +#define rx_decouple_edge_b_shift 12 +#define rx_decouple_edge_b_mask 0x1000 + + +#define rx_disable_bank_pdwn_addr 0b100000010 +#define rx_disable_bank_pdwn_startbit 14 +#define rx_disable_bank_pdwn_width 1 +#define rx_disable_bank_pdwn_endbit 14 +#define rx_disable_bank_pdwn_shift 1 +#define rx_disable_bank_pdwn_mask 0x2 + + +#define rx_e_bist_en_addr 0b100000010 +#define rx_e_bist_en_startbit 11 +#define rx_e_bist_en_width 1 +#define rx_e_bist_en_endbit 11 +#define rx_e_bist_en_shift 4 +#define rx_e_bist_en_mask 0x10 + + +#define rx_e_controls_addr 0b000010110 +#define rx_e_controls_startbit 0 +#define rx_e_controls_width 3 +#define rx_e_controls_endbit 2 +#define rx_e_controls_shift 13 +#define rx_e_controls_mask 0xe000 + + +#define rx_e_ctle_coarse_addr 0b000011001 +#define rx_e_ctle_coarse_startbit 0 +#define rx_e_ctle_coarse_width 5 +#define rx_e_ctle_coarse_endbit 4 +#define rx_e_ctle_coarse_shift 11 +#define rx_e_ctle_coarse_mask 0xf800 + + +#define rx_e_ctle_gain_addr 0b000011001 +#define rx_e_ctle_gain_startbit 5 +#define rx_e_ctle_gain_width 4 +#define rx_e_ctle_gain_endbit 8 +#define rx_e_ctle_gain_shift 7 +#define rx_e_ctle_gain_mask 0x780 + + +#define rx_e_even_integ_fine_gain_addr 0b000011000 +#define rx_e_even_integ_fine_gain_startbit 4 +#define rx_e_even_integ_fine_gain_width 5 +#define rx_e_even_integ_fine_gain_endbit 8 +#define rx_e_even_integ_fine_gain_shift 7 +#define rx_e_even_integ_fine_gain_mask 0xf80 + + +#define rx_e_integ_coarse_gain_addr 0b000011000 +#define rx_e_integ_coarse_gain_startbit 0 +#define rx_e_integ_coarse_gain_width 4 +#define rx_e_integ_coarse_gain_endbit 3 +#define rx_e_integ_coarse_gain_shift 12 +#define rx_e_integ_coarse_gain_mask 0xf000 + + +#define rx_e_odd_integ_fine_gain_addr 0b000011000 +#define rx_e_odd_integ_fine_gain_startbit 9 +#define rx_e_odd_integ_fine_gain_width 5 +#define rx_e_odd_integ_fine_gain_endbit 13 +#define rx_e_odd_integ_fine_gain_shift 2 +#define rx_e_odd_integ_fine_gain_mask 0x7c + + +#define rx_e_offset_e_addr 0b000010111 +#define rx_e_offset_e_startbit 0 +#define rx_e_offset_e_width 7 +#define rx_e_offset_e_endbit 6 +#define rx_e_offset_e_shift 9 +#define rx_e_offset_e_mask 0xfe00 + + +#define rx_e_offset_o_addr 0b000010111 +#define rx_e_offset_o_startbit 8 +#define rx_e_offset_o_width 7 +#define rx_e_offset_o_endbit 14 +#define rx_e_offset_o_shift 1 +#define rx_e_offset_o_mask 0xfe + + +#define rx_eo_enable_ctle_edge_offset_cal_addr 0b100010110 +#define rx_eo_enable_ctle_edge_offset_cal_startbit 10 +#define rx_eo_enable_ctle_edge_offset_cal_width 1 +#define rx_eo_enable_ctle_edge_offset_cal_endbit 10 +#define rx_eo_enable_ctle_edge_offset_cal_shift 5 +#define rx_eo_enable_ctle_edge_offset_cal_mask 0x20 + + +#define rx_eo_enable_vga_edge_offset_cal_addr 0b100010110 +#define rx_eo_enable_vga_edge_offset_cal_startbit 9 +#define rx_eo_enable_vga_edge_offset_cal_width 1 +#define rx_eo_enable_vga_edge_offset_cal_endbit 9 +#define rx_eo_enable_vga_edge_offset_cal_shift 6 +#define rx_eo_enable_vga_edge_offset_cal_mask 0x40 + + +#define rx_force_init_done_addr 0b001100100 +#define rx_force_init_done_startbit 5 +#define rx_force_init_done_width 1 +#define rx_force_init_done_endbit 5 +#define rx_force_init_done_shift 10 +#define rx_force_init_done_mask 0x400 + + +#define rx_force_recal_done_addr 0b001100100 +#define rx_force_recal_done_startbit 6 +#define rx_force_recal_done_width 1 +#define rx_force_recal_done_endbit 6 +#define rx_force_recal_done_shift 9 +#define rx_force_recal_done_mask 0x200 + + +#define rx_init_done_addr 0b001100101 +#define rx_init_done_startbit 0 +#define rx_init_done_width 1 +#define rx_init_done_endbit 0 +#define rx_init_done_shift 15 +#define rx_init_done_mask 0x8000 + + +#define rx_init_done_dl_mask_addr 0b100000011 +#define rx_init_done_dl_mask_startbit 10 +#define rx_init_done_dl_mask_width 1 +#define rx_init_done_dl_mask_endbit 10 +#define rx_init_done_dl_mask_shift 5 +#define rx_init_done_dl_mask_mask 0x20 + + +#define rx_iref_bypass_addr 0b100011000 +#define rx_iref_bypass_startbit 5 +#define rx_iref_bypass_width 1 +#define rx_iref_bypass_endbit 5 +#define rx_iref_bypass_shift 10 +#define rx_iref_bypass_mask 0x400 + + +#define rx_iref_parity_chk_addr 0b101111000 +#define rx_iref_parity_chk_startbit 11 +#define rx_iref_parity_chk_width 4 +#define rx_iref_parity_chk_endbit 14 +#define rx_iref_parity_chk_shift 1 +#define rx_iref_parity_chk_mask 0x1e + + +#define rx_iref_pdwn_b_addr 0b100011000 +#define rx_iref_pdwn_b_startbit 6 +#define rx_iref_pdwn_b_width 1 +#define rx_iref_pdwn_b_endbit 6 +#define rx_iref_pdwn_b_shift 9 +#define rx_iref_pdwn_b_mask 0x200 + + +#define rx_iref_res_dac_addr 0b100011000 +#define rx_iref_res_dac_startbit 2 +#define rx_iref_res_dac_width 3 +#define rx_iref_res_dac_endbit 4 +#define rx_iref_res_dac_shift 11 +#define rx_iref_res_dac_mask 0x3800 + + +#define rx_lane_busy_addr 0b001100101 +#define rx_lane_busy_startbit 2 +#define rx_lane_busy_width 1 +#define rx_lane_busy_endbit 2 +#define rx_lane_busy_shift 13 +#define rx_lane_busy_mask 0x2000 + + +#define rx_lane_disabled_addr 0b001100100 +#define rx_lane_disabled_startbit 4 +#define rx_lane_disabled_width 1 +#define rx_lane_disabled_endbit 4 +#define rx_lane_disabled_shift 11 +#define rx_lane_disabled_mask 0x800 + + +#define rx_minikerf_addr 0b100110110 +#define rx_minikerf_startbit 0 +#define rx_minikerf_width 16 +#define rx_minikerf_endbit 15 +#define rx_minikerf_shift 0 +#define rx_minikerf_mask 0xffff + + +#define rx_octant_select_addr 0b100110001 +#define rx_octant_select_startbit 0 +#define rx_octant_select_width 3 +#define rx_octant_select_endbit 2 +#define rx_octant_select_shift 13 +#define rx_octant_select_mask 0xe000 + + +#define rx_pipe_margin_addr 0b001001000 +#define rx_pipe_margin_startbit 4 +#define rx_pipe_margin_width 1 +#define rx_pipe_margin_endbit 4 +#define rx_pipe_margin_shift 11 +#define rx_pipe_margin_mask 0x800 + + +#define rx_pr_bump_to_edge_b_addr 0b001001001 +#define rx_pr_bump_to_edge_b_startbit 8 +#define rx_pr_bump_to_edge_b_width 1 +#define rx_pr_bump_to_edge_b_endbit 8 +#define rx_pr_bump_to_edge_b_shift 7 +#define rx_pr_bump_to_edge_b_mask 0x80 + + +#define rx_pr_coarse_mode_en_addr 0b001000111 +#define rx_pr_coarse_mode_en_startbit 0 +#define rx_pr_coarse_mode_en_width 1 +#define rx_pr_coarse_mode_en_endbit 0 +#define rx_pr_coarse_mode_en_shift 15 +#define rx_pr_coarse_mode_en_mask 0x8000 + + +#define rx_pr_coarse_mode_timer_sel_addr 0b001000111 +#define rx_pr_coarse_mode_timer_sel_startbit 9 +#define rx_pr_coarse_mode_timer_sel_width 2 +#define rx_pr_coarse_mode_timer_sel_endbit 10 +#define rx_pr_coarse_mode_timer_sel_shift 5 +#define rx_pr_coarse_mode_timer_sel_mask 0x60 + + +#define rx_pr_data_b_offset_addr 0b001001010 +#define rx_pr_data_b_offset_startbit 6 +#define rx_pr_data_b_offset_width 6 +#define rx_pr_data_b_offset_endbit 11 +#define rx_pr_data_b_offset_shift 4 +#define rx_pr_data_b_offset_mask 0x3f0 + + +#define rx_pr_data_offset_disable_b_addr 0b001001001 +#define rx_pr_data_offset_disable_b_startbit 12 +#define rx_pr_data_offset_disable_b_width 1 +#define rx_pr_data_offset_disable_b_endbit 12 +#define rx_pr_data_offset_disable_b_shift 3 +#define rx_pr_data_offset_disable_b_mask 0x8 + + +#define rx_pr_ddc_b_addr 0b001001001 +#define rx_pr_ddc_b_startbit 6 +#define rx_pr_ddc_b_width 1 +#define rx_pr_ddc_b_endbit 6 +#define rx_pr_ddc_b_shift 9 +#define rx_pr_ddc_b_mask 0x200 + + +#define rx_pr_fw_gray_coded_addr 0b001010000 +#define rx_pr_fw_gray_coded_startbit 2 +#define rx_pr_fw_gray_coded_width 7 +#define rx_pr_fw_gray_coded_endbit 8 +#define rx_pr_fw_gray_coded_shift 7 +#define rx_pr_fw_gray_coded_mask 0x3f80 + + +#define rx_pr_fw_inertia_amt_addr 0b001000101 +#define rx_pr_fw_inertia_amt_startbit 9 +#define rx_pr_fw_inertia_amt_width 3 +#define rx_pr_fw_inertia_amt_endbit 11 +#define rx_pr_fw_inertia_amt_shift 4 +#define rx_pr_fw_inertia_amt_mask 0x70 + + +#define rx_pr_fw_inertia_amt_coarse_addr 0b001000111 +#define rx_pr_fw_inertia_amt_coarse_startbit 2 +#define rx_pr_fw_inertia_amt_coarse_width 3 +#define rx_pr_fw_inertia_amt_coarse_endbit 4 +#define rx_pr_fw_inertia_amt_coarse_shift 11 +#define rx_pr_fw_inertia_amt_coarse_mask 0x3800 + + +#define rx_pr_fw_off_addr 0b001000101 +#define rx_pr_fw_off_startbit 8 +#define rx_pr_fw_off_width 1 +#define rx_pr_fw_off_endbit 8 +#define rx_pr_fw_off_shift 7 +#define rx_pr_fw_off_mask 0x80 + + +#define rx_pr_in_coarse_mode_addr 0b001010000 +#define rx_pr_in_coarse_mode_startbit 0 +#define rx_pr_in_coarse_mode_width 1 +#define rx_pr_in_coarse_mode_endbit 0 +#define rx_pr_in_coarse_mode_shift 15 +#define rx_pr_in_coarse_mode_mask 0x8000 + + +#define rx_pr_in_coarse_mode_sticky_addr 0b001010000 +#define rx_pr_in_coarse_mode_sticky_startbit 1 +#define rx_pr_in_coarse_mode_sticky_width 1 +#define rx_pr_in_coarse_mode_sticky_endbit 1 +#define rx_pr_in_coarse_mode_sticky_shift 14 +#define rx_pr_in_coarse_mode_sticky_mask 0x4000 + + +#define rx_pr_in_coarse_mode_sticky_clear_addr 0b001001100 +#define rx_pr_in_coarse_mode_sticky_clear_startbit 2 +#define rx_pr_in_coarse_mode_sticky_clear_width 1 +#define rx_pr_in_coarse_mode_sticky_clear_endbit 2 +#define rx_pr_in_coarse_mode_sticky_clear_shift 13 +#define rx_pr_in_coarse_mode_sticky_clear_mask 0x2000 + + +#define rx_pr_invalid_lock_coarse_en_addr 0b001000111 +#define rx_pr_invalid_lock_coarse_en_startbit 1 +#define rx_pr_invalid_lock_coarse_en_width 1 +#define rx_pr_invalid_lock_coarse_en_endbit 1 +#define rx_pr_invalid_lock_coarse_en_shift 14 +#define rx_pr_invalid_lock_coarse_en_mask 0x4000 + + +#define rx_pr_left_edge_b_addr 0b001100011 +#define rx_pr_left_edge_b_startbit 0 +#define rx_pr_left_edge_b_width 6 +#define rx_pr_left_edge_b_endbit 5 +#define rx_pr_left_edge_b_shift 10 +#define rx_pr_left_edge_b_mask 0xfc00 + + +#define rx_pr_phase_step_coarse_addr 0b001000111 +#define rx_pr_phase_step_coarse_startbit 5 +#define rx_pr_phase_step_coarse_width 4 +#define rx_pr_phase_step_coarse_endbit 8 +#define rx_pr_phase_step_coarse_shift 7 +#define rx_pr_phase_step_coarse_mask 0x780 + + +#define rx_pr_reset_addr 0b001001011 +#define rx_pr_reset_startbit 14 +#define rx_pr_reset_width 1 +#define rx_pr_reset_endbit 14 +#define rx_pr_reset_shift 1 +#define rx_pr_reset_mask 0x2 + + +#define rx_pr_right_edge_b_addr 0b001100011 +#define rx_pr_right_edge_b_startbit 6 +#define rx_pr_right_edge_b_width 6 +#define rx_pr_right_edge_b_endbit 11 +#define rx_pr_right_edge_b_shift 4 +#define rx_pr_right_edge_b_mask 0x3f0 + + +#define rx_pr_use_dfe_clock_b_addr 0b001001001 +#define rx_pr_use_dfe_clock_b_startbit 14 +#define rx_pr_use_dfe_clock_b_width 1 +#define rx_pr_use_dfe_clock_b_endbit 14 +#define rx_pr_use_dfe_clock_b_shift 1 +#define rx_pr_use_dfe_clock_b_mask 0x2 + + +#define rx_pr_wobble_b_addr 0b001001001 +#define rx_pr_wobble_b_startbit 3 +#define rx_pr_wobble_b_width 1 +#define rx_pr_wobble_b_endbit 3 +#define rx_pr_wobble_b_shift 12 +#define rx_pr_wobble_b_mask 0x1000 + + +#define rx_pr_wobble_b_ip_addr 0b001001110 +#define rx_pr_wobble_b_ip_startbit 3 +#define rx_pr_wobble_b_ip_width 1 +#define rx_pr_wobble_b_ip_endbit 3 +#define rx_pr_wobble_b_ip_shift 12 +#define rx_pr_wobble_b_ip_mask 0x1000 + + +#define rx_pr_wobble_edge_addr 0b001001001 +#define rx_pr_wobble_edge_startbit 4 +#define rx_pr_wobble_edge_width 1 +#define rx_pr_wobble_edge_endbit 4 +#define rx_pr_wobble_edge_shift 11 +#define rx_pr_wobble_edge_mask 0x800 + + +#define rx_pr_wobble_edge_ip_addr 0b001001110 +#define rx_pr_wobble_edge_ip_startbit 4 +#define rx_pr_wobble_edge_ip_width 1 +#define rx_pr_wobble_edge_ip_endbit 4 +#define rx_pr_wobble_edge_ip_shift 11 +#define rx_pr_wobble_edge_ip_mask 0x800 + + +#define rx_psave_ana_req_dis_addr 0b001000100 +#define rx_psave_ana_req_dis_startbit 5 +#define rx_psave_ana_req_dis_width 1 +#define rx_psave_ana_req_dis_endbit 5 +#define rx_psave_ana_req_dis_shift 10 +#define rx_psave_ana_req_dis_mask 0x400 + + +#define rx_psave_dig_req_dis_addr 0b001000100 +#define rx_psave_dig_req_dis_startbit 4 +#define rx_psave_dig_req_dis_width 1 +#define rx_psave_dig_req_dis_endbit 4 +#define rx_psave_dig_req_dis_shift 11 +#define rx_psave_dig_req_dis_mask 0x800 + + +#define rx_rc_enable_auto_recal_addr 0b100101110 +#define rx_rc_enable_auto_recal_startbit 3 +#define rx_rc_enable_auto_recal_width 1 +#define rx_rc_enable_auto_recal_endbit 3 +#define rx_rc_enable_auto_recal_shift 12 +#define rx_rc_enable_auto_recal_mask 0x1000 + + +#define rx_rc_enable_ctle_edge_offset_cal_addr 0b100010111 +#define rx_rc_enable_ctle_edge_offset_cal_startbit 10 +#define rx_rc_enable_ctle_edge_offset_cal_width 1 +#define rx_rc_enable_ctle_edge_offset_cal_endbit 10 +#define rx_rc_enable_ctle_edge_offset_cal_shift 5 +#define rx_rc_enable_ctle_edge_offset_cal_mask 0x20 + + +#define rx_rc_enable_pu_edge_track_addr 0b101011111 +#define rx_rc_enable_pu_edge_track_startbit 0 +#define rx_rc_enable_pu_edge_track_width 1 +#define rx_rc_enable_pu_edge_track_endbit 0 +#define rx_rc_enable_pu_edge_track_shift 15 +#define rx_rc_enable_pu_edge_track_mask 0x8000 + + +#define rx_rc_enable_vga_edge_offset_cal_addr 0b100010111 +#define rx_rc_enable_vga_edge_offset_cal_startbit 9 +#define rx_rc_enable_vga_edge_offset_cal_width 1 +#define rx_rc_enable_vga_edge_offset_cal_endbit 9 +#define rx_rc_enable_vga_edge_offset_cal_shift 6 +#define rx_rc_enable_vga_edge_offset_cal_mask 0x40 + + +#define rx_recal_abort_addr 0b001100100 +#define rx_recal_abort_startbit 3 +#define rx_recal_abort_width 1 +#define rx_recal_abort_endbit 3 +#define rx_recal_abort_shift 12 +#define rx_recal_abort_mask 0x1000 + +#define rx_glbsm_pl_cntl1_o_pl_addr 0b001100100 +#define rx_glbsm_pl_cntl1_o_pl_startbit 0 +#define rx_glbsm_pl_cntl1_o_pl_width 16 +#define rx_glbsm_pl_cntl1_o_pl_endbit 15 +#define rx_glbsm_pl_cntl1_o_pl_shift 0 +#define rx_glbsm_pl_cntl1_o_pl_mask 0xffff + +#define rx_ctl_mode2_eo_pg_addr 0b100000011 +#define rx_ctl_mode2_eo_pg_startbit 0 +#define rx_ctl_mode2_eo_pg_width 16 +#define rx_ctl_mode2_eo_pg_endbit 15 +#define rx_ctl_mode2_eo_pg_shift 0 +#define rx_ctl_mode2_eo_pg_mask 0xffff + + + + +#define rx_recal_abort_active_addr 0b001100101 +#define rx_recal_abort_active_startbit 6 +#define rx_recal_abort_active_width 1 +#define rx_recal_abort_active_endbit 6 +#define rx_recal_abort_active_shift 9 +#define rx_recal_abort_active_mask 0x200 + + +#define rx_recal_abort_dl_mask_addr 0b100000011 +#define rx_recal_abort_dl_mask_startbit 9 +#define rx_recal_abort_dl_mask_width 1 +#define rx_recal_abort_dl_mask_endbit 9 +#define rx_recal_abort_dl_mask_shift 6 +#define rx_recal_abort_dl_mask_mask 0x40 + + +#define rx_recal_done_addr 0b001100101 +#define rx_recal_done_startbit 3 +#define rx_recal_done_width 1 +#define rx_recal_done_endbit 3 +#define rx_recal_done_shift 12 +#define rx_recal_done_mask 0x1000 + + +#define rx_recal_done_dl_mask_addr 0b100000011 +#define rx_recal_done_dl_mask_startbit 7 +#define rx_recal_done_dl_mask_width 1 +#define rx_recal_done_dl_mask_endbit 7 +#define rx_recal_done_dl_mask_shift 8 +#define rx_recal_done_dl_mask_mask 0x100 + + +#define rx_recal_req_addr 0b001100100 +#define rx_recal_req_startbit 2 +#define rx_recal_req_width 1 +#define rx_recal_req_endbit 2 +#define rx_recal_req_shift 13 +#define rx_recal_req_mask 0x2000 + + +#define rx_recal_req_active_addr 0b001100101 +#define rx_recal_req_active_startbit 5 +#define rx_recal_req_active_width 1 +#define rx_recal_req_active_endbit 5 +#define rx_recal_req_active_shift 10 +#define rx_recal_req_active_mask 0x400 + + +#define rx_recal_req_dl_mask_addr 0b100000011 +#define rx_recal_req_dl_mask_startbit 6 +#define rx_recal_req_dl_mask_width 1 +#define rx_recal_req_dl_mask_endbit 6 +#define rx_recal_req_dl_mask_shift 9 +#define rx_recal_req_dl_mask_mask 0x200 + + +#define rx_run_dccal_addr 0b001100100 +#define rx_run_dccal_startbit 1 +#define rx_run_dccal_width 1 +#define rx_run_dccal_endbit 1 +#define rx_run_dccal_shift 14 +#define rx_run_dccal_mask 0x4000 + + +#define rx_run_lane_addr 0b001100100 +#define rx_run_lane_startbit 0 +#define rx_run_lane_width 1 +#define rx_run_lane_endbit 0 +#define rx_run_lane_shift 15 +#define rx_run_lane_mask 0x8000 + + +#define rx_run_lane_active_addr 0b001100101 +#define rx_run_lane_active_startbit 4 +#define rx_run_lane_active_width 1 +#define rx_run_lane_active_endbit 4 +#define rx_run_lane_active_shift 11 +#define rx_run_lane_active_mask 0x800 + + +#define rx_run_lane_dl_mask_addr 0b100000011 +#define rx_run_lane_dl_mask_startbit 8 +#define rx_run_lane_dl_mask_width 1 +#define rx_run_lane_dl_mask_endbit 8 +#define rx_run_lane_dl_mask_shift 7 +#define rx_run_lane_dl_mask_mask 0x80 + + +#define rx_scope_mode_addr 0b001001000 +#define rx_scope_mode_startbit 5 +#define rx_scope_mode_width 2 +#define rx_scope_mode_endbit 6 +#define rx_scope_mode_shift 9 +#define rx_scope_mode_mask 0x600 + + +#define rx_set_run_dccal_addr 0b001100110 +#define rx_set_run_dccal_startbit 2 +#define rx_set_run_dccal_width 1 +#define rx_set_run_dccal_endbit 2 +#define rx_set_run_dccal_shift 13 +#define rx_set_run_dccal_mask 0x2000 + + +#define rx_set_run_lane_addr 0b001100110 +#define rx_set_run_lane_startbit 0 +#define rx_set_run_lane_width 1 +#define rx_set_run_lane_endbit 0 +#define rx_set_run_lane_shift 15 +#define rx_set_run_lane_mask 0x8000 + + +#define rx_speed_select_addr 0b100110001 +#define rx_speed_select_startbit 3 +#define rx_speed_select_width 2 +#define rx_speed_select_endbit 4 +#define rx_speed_select_shift 11 +#define rx_speed_select_mask 0x1800 + + +#define rx_work_regs_ioreset_addr 0b001110101 +#define rx_work_regs_ioreset_startbit 0 +#define rx_work_regs_ioreset_width 1 +#define rx_work_regs_ioreset_endbit 0 +#define rx_work_regs_ioreset_shift 15 +#define rx_work_regs_ioreset_mask 0x8000 + + +#define tx_nseg_post_en_addr 0b110110001 +#define tx_nseg_post_en_startbit 1 +#define tx_nseg_post_en_width 7 +#define tx_nseg_post_en_endbit 7 +#define tx_nseg_post_en_shift 8 +#define tx_nseg_post_en_mask 0x7f00 + + +#define tx_nseg_post_sel_addr 0b110110001 +#define tx_nseg_post_sel_startbit 8 +#define tx_nseg_post_sel_width 7 +#define tx_nseg_post_sel_endbit 14 +#define tx_nseg_post_sel_shift 1 +#define tx_nseg_post_sel_mask 0xfe + + +#define tx_psave_req_dis_addr 0b010000000 +#define tx_psave_req_dis_startbit 6 +#define tx_psave_req_dis_width 1 +#define tx_psave_req_dis_endbit 6 +#define tx_psave_req_dis_shift 9 +#define tx_psave_req_dis_mask 0x200 + + +#define tx_pseg_pre_en_addr 0b110100110 +#define tx_pseg_pre_en_startbit 3 +#define tx_pseg_pre_en_width 5 +#define tx_pseg_pre_en_endbit 7 +#define tx_pseg_pre_en_shift 8 +#define tx_pseg_pre_en_mask 0x1f00 + +//#define tx_pseg_pre_sel_addr 0b110100110 +//#define tx_pseg_pre_sel_startbit 8 +//#define tx_pseg_pre_sel_width 5 +//#define tx_pseg_pre_sel_endbit 12 +//#define tx_pseg_pre_sel_shift 3 +//#define tx_pseg_pre_sel_mask 0x00f8 + +#define tx_nseg_pre_en_addr 0b110100111 +#define tx_nseg_pre_en_startbit 3 +#define tx_nseg_pre_en_width 5 +#define tx_nseg_pre_en_endbit 7 +#define tx_nseg_pre_en_shift 8 +#define tx_nseg_pre_en_mask 0x1f00 + + +//#define tx_nseg_pre_sel_addr 0b110100111 +//#define tx_nseg_pre_sel_startbit 8 +//#define tx_nseg_pre_sel_width 5 +//#define tx_nseg_pre_sel_endbit 12 +//#define tx_nseg_pre_sel_shift 3 +//#define tx_nseg_pre_sel_mask 0x00f8 + + + + +#define tx_pseg_post_en_addr 0b110110000 +#define tx_pseg_post_en_startbit 1 +#define tx_pseg_post_en_width 7 +#define tx_pseg_post_en_endbit 7 +#define tx_pseg_post_en_shift 8 +#define tx_pseg_post_en_mask 0x7f00 + +#define tx_pseg_post_sel_addr 0b110110000 +#define tx_pseg_post_sel_startbit 8 +#define tx_pseg_post_sel_width 7 +#define tx_pseg_post_sel_endbit 14 +#define tx_pseg_post_sel_shift 1 +#define tx_pseg_post_sel_mask 0xfe + +#define tx_nseg_post_en_addr 0b110110001 +#define tx_nseg_post_en_startbit 1 +#define tx_nseg_post_en_width 7 +#define tx_nseg_post_en_endbit 7 +#define tx_nseg_post_en_shift 8 +#define tx_nseg_post_en_mask 0x7f00 + +#define tx_nseg_post_sel_addr 0b110110001 +#define tx_nseg_post_sel_startbit 8 +#define tx_nseg_post_sel_width 7 +#define tx_nseg_post_sel_endbit 14 +#define tx_nseg_post_sel_shift 1 +#define tx_nseg_post_sel_mask 0xfe + +//#define tx_pseg_marginpu_en_addr 0b110101000 +//#define tx_pseg_marginpu_en_startbit 0 +//#define tx_pseg_marginpu_en_width 8 +//#define tx_pseg_marginpu_en_endbit 7 +//#define tx_pseg_marginpu_en_shift 8 +//#define tx_pseg_marginpu_en_mask 0xff00 +//#define tx_pseg_marginpd_en_addr 0b110101000 +//#define tx_pseg_marginpd_en_startbit 8 +//#define tx_pseg_marginpd_en_width 8 +//#define tx_pseg_marginpd_en_endbit 15 +//#define tx_pseg_marginpd_en_shift 0 +//#define tx_pseg_marginpd_en_mask 0x00ff + +//#define tx_nseg_marginpu_en_addr 0b110101000 +//#define tx_nseg_marginpu_en_startbit 0 +//#define tx_nseg_marginpu_en_width 8 +//#define tx_nseg_marginpu_en_endbit 7 +//#define tx_nseg_marginpu_en_shift 8 +//#define tx_nseg_marginpu_en_mask 0xff00 +//#define tx_nseg_marginpd_en_addr 0b110101000 +//#define tx_nseg_marginpd_en_startbit 8 +//#define tx_nseg_marginpd_en_width 8 +//#define tx_nseg_marginpd_en_endbit 15 +//#define tx_nseg_marginpd_en_shift 0 +//#define tx_nseg_marginpd_en_mask 0x00ff + +//#define tx_marginpu_sel_addr 0b110101010 +//#define tx_marginpu_sel_startbit 0 +//#define tx_marginpu_sel_width 8 +//#define tx_marginpu_sel_endbit 7 +//#define tx_marginpu_sel_shift 8 +//#define tx_marginpu_sel_mask 0xff00 +//#define tx_marginpd_sel_addr 0b110101010 +//#define tx_marginpd_sel_startbit 8 +//#define tx_marginpd_sel_width 8 +//#define tx_marginpd_sel_endbit 15 +//#define tx_marginpd_sel_shift 0 +//#define tx_marginpd_sel_mask 0x00ff + +#define tx_lane_invert_addr 0b010000000 +#define tx_lane_invert_startbit 1 +#define tx_lane_invert_width 1 +#define tx_lane_invert_endbit 1 +#define tx_lane_invert_shift 14 +#define tx_lane_invert_mask 0x4000 + +#define tx_lane_pdwn_addr 0b010000000 +#define tx_lane_pdwn_startbit 0 +#define tx_lane_pdwn_width 1 +#define tx_lane_pdwn_endbit 0 +#define tx_lane_pdwn_shift 15 +#define tx_lane_pdwn_mask 0x8000 + +#define tx_pdwn_lite_addr 0b010000001 +#define tx_pdwn_lite_startbit 13 +#define tx_pdwn_lite_width 1 +#define tx_pdwn_lite_endbit 13 +#define tx_pdwn_lite_shift 2 +#define tx_pdwn_lite_mask 0x0004 + +#define tx_drv_data_pattern_addr 0b110000100 +#define tx_drv_data_pattern_startbit 2 +#define tx_drv_data_pattern_width 4 +#define tx_drv_data_pattern_endbit 5 +#define tx_drv_data_pattern_shift 10 +#define tx_drv_data_pattern_mask 0x3C00 + + + + +#define tx_rxcal_addr 0b010000001 +#define tx_rxcal_startbit 9 +#define tx_rxcal_width 1 +#define tx_rxcal_endbit 9 +#define tx_rxcal_shift 6 +#define tx_rxcal_mask 0x40 + + +#define rx_clkdist_pdwn_addr 0b100000010 +#define rx_clkdist_pdwn_startbit 0 +#define rx_clkdist_pdwn_width 3 +#define rx_clkdist_pdwn_endbit 2 +#define rx_clkdist_pdwn_shift 13 +#define rx_clkdist_pdwn_mask 0xe000 + + +#define rx_ioreset_addr 0b001001011 +#define rx_ioreset_startbit 15 +#define rx_ioreset_width 1 +#define rx_ioreset_endbit 15 +#define rx_ioreset_shift 0 +#define rx_ioreset_mask 0x1 + + +#define rx_pipe_sel_addr 0b001001000 +#define rx_pipe_sel_startbit 1 +#define rx_pipe_sel_width 2 +#define rx_pipe_sel_endbit 2 +#define rx_pipe_sel_shift 13 +#define rx_pipe_sel_mask 0x6000 + + +#define tx_clkdist_pdwn_addr 0b110000010 +#define tx_clkdist_pdwn_startbit 0 +#define tx_clkdist_pdwn_width 3 +#define tx_clkdist_pdwn_endbit 2 +#define tx_clkdist_pdwn_shift 13 +#define tx_clkdist_pdwn_mask 0xe000 + + +#define tx_ioreset_addr 0b010001001 +#define tx_ioreset_startbit 0 +#define tx_ioreset_width 1 +#define tx_ioreset_endbit 0 +#define tx_ioreset_shift 15 +#define tx_ioreset_mask 0x8000 + + +#define tx_nseg_main_en_addr 0b110101100 +#define tx_nseg_main_en_startbit 3 +#define tx_nseg_main_en_width 7 +#define tx_nseg_main_en_endbit 9 +#define tx_nseg_main_en_shift 6 +#define tx_nseg_main_en_mask 0x1fc0 + + +#define tx_pseg_main_en_addr 0b110101011 +#define tx_pseg_main_en_startbit 3 +#define tx_pseg_main_en_width 7 +#define tx_pseg_main_en_endbit 9 +#define tx_pseg_main_en_shift 6 +#define tx_pseg_main_en_mask 0x1fc0 + + +#define tx_tdr_pulse_width_addr 0b110011011 +#define tx_tdr_pulse_width_startbit 0 +#define tx_tdr_pulse_width_width 8 +#define tx_tdr_pulse_width_endbit 7 +#define tx_tdr_pulse_width_shift 8 +#define tx_tdr_pulse_width_mask 0xff00 diff --git a/import/chips/p9/procedures/ppe_closed/ippe/ioa/topfiles.mk b/import/chips/p9/procedures/ppe_closed/ippe/ioa/topfiles.mk index d131712f..2b218cb3 100644 --- a/import/chips/p9/procedures/ppe_closed/ippe/ioa/topfiles.mk +++ b/import/chips/p9/procedures/ppe_closed/ippe/ioa/topfiles.mk @@ -5,7 +5,7 @@ # # OpenPOWER HCODE Project # -# COPYRIGHT 2016,2017 +# COPYRIGHT 2016,2018 # [+] International Business Machines Corp. # # @@ -22,8 +22,9 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG + # Source files depends on build target -TOP-C-SOURCES = p9_abus_main.c pk_app_irq_table.c +TOP-C-SOURCES = p9_abus_main.c pk_app_irq_table.c io_lib.c p9_a_common.c TOP-CXX-SOURCES = TOP-S-SOURCES = |
