diff options
author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-05-27 07:56:45 -0500 |
---|---|---|
committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:06:49 -0500 |
commit | 6c515ac1898135e3ead15b5227c625e79aee7d11 (patch) | |
tree | 290e3895025a81f925539c90fb086038d697d540 | |
parent | df29a180ab0e19e7d792822b7af47a179944f936 (diff) | |
download | talos-hcode-6c515ac1898135e3ead15b5227c625e79aee7d11.tar.gz talos-hcode-6c515ac1898135e3ead15b5227c625e79aee7d11.zip |
PM:Changing calling convention of STOP API.
Changes made in function arguments to make it suitable for C world.
This is based on feedback received from Power Mixer team.
RTC:154530
Change-Id: I402822918089df2ac05774ede1e770bd013678b3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25143
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
6 files changed, 98 insertions, 79 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_stop_util.H b/import/chips/p9/procedures/hwp/lib/p9_stop_util.H index a43ff93d..ea515ede 100755 --- a/import/chips/p9/procedures/hwp/lib/p9_stop_util.H +++ b/import/chips/p9/procedures/hwp/lib/p9_stop_util.H @@ -123,13 +123,14 @@ enum * @brief returns core id and thread id by parsing a given PIR. * @param i_pStopImage points to STOP image associated with a proc chip. * @param i_pir PIR associated with a core's thread. - * @param o_coreId core id obtained from PIR. - * @param o_threadId thread id obtained from PIR. + * @param o_coreId points to core id value obtained from PIR. + * @param o_threadId points to thread id value obtained from PIR. * @return SUCCESS if function suceeds, error code otherwise. */ StopReturnCode_t getCoreAndThread( void* const i_pStopImage, const uint64_t i_pir, - uint32_t& o_coreId, uint32_t& o_threadId ); + uint32_t* o_coreId, + uint32_t* o_threadId ); } // namespace stopImageSection ends diff --git a/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H b/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H index 388f5804..fdc8dcf0 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H +++ b/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H @@ -40,10 +40,10 @@ #ifdef __cplusplus extern "C" { -#endif namespace stopImageSection { +#endif /** * @brief enumerates opcodes for few instructions. @@ -66,10 +66,10 @@ enum ATTN_OPCODE = 0x00000200, }; +#ifdef __cplusplus } // namespace stopImageSection ends -#ifdef __cplusplus } // extern "C" -#endif +#endif //__cplusplus #endif //__REG_RESTORE_INSTRUCTION_H diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index 41bc8380..89ec27e7 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -46,10 +46,13 @@ #ifdef __cplusplus extern "C" { -#endif namespace stopImageSection { +#endif +// a true in the table below means register is of scope thread +// whereas a false meanse register is of scope core. + const StopSprReg_t g_sprRegister[] = { { P9_STOP_SPR_HSPRG0, true }, @@ -73,9 +76,8 @@ const uint32_t MAX_SPR_SUPPORTED = * @param[in] i_pImage pointer to beginning of chip's HOMER image. * @param[in] i_regId SPR register id * @param[in] i_coreId core id - * @param[in|out] io_threadId thread id - * @param[in|out] io_threadLevelReg true if register is of thread scope, false if of - * core scope. + * @param[in|out] i_pThreadId points to thread id + * @param[in|out] i_pThreadLevelReg points to scope information of SPR * @return STOP_SAVE_SUCCESS if arguments found valid, error code otherwise. * @note for register of scope core, function shall force io_threadId to * zero. @@ -83,12 +85,12 @@ const uint32_t MAX_SPR_SUPPORTED = StopReturnCode_t validateSprImageInputs( void* const i_pImage, const CpuReg_t i_regId, const uint32_t i_coreId, - uint32_t& io_threadId, - bool& io_threadLevelReg ) + uint32_t* i_pThreadId, + bool* i_pThreadLevelReg ) { StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; bool sprSupported = false; - io_threadLevelReg = false; + *i_pThreadLevelReg = false; do { @@ -117,7 +119,7 @@ StopReturnCode_t validateSprImageInputs( void* const i_pImage, break; } - if( MAX_THREAD_ID_SUPPORTED < io_threadId ) + if( MAX_THREAD_ID_SUPPORTED < *i_pThreadId ) { //Error: invalid core thread. Given core thread exceeds maximum //threads supported in a core. @@ -131,14 +133,16 @@ StopReturnCode_t validateSprImageInputs( void* const i_pImage, break; } - for( uint32_t index = 0; index < MAX_SPR_SUPPORTED; ++index ) + uint32_t index = 0; + + for( index = 0; index < MAX_SPR_SUPPORTED; ++index ) { - if( i_regId == g_sprRegister[index].sprId ) + if( i_regId == (CpuReg_t )g_sprRegister[index].sprId ) { // given register is in the list of register supported sprSupported = true; - io_threadLevelReg = g_sprRegister[index].isThreadScope; - io_threadId = io_threadLevelReg ? io_threadId : 0; + *i_pThreadLevelReg = g_sprRegister[index].isThreadScope; + *i_pThreadId = *i_pThreadLevelReg ? *i_pThreadId : 0; break; } } @@ -160,7 +164,7 @@ StopReturnCode_t validateSprImageInputs( void* const i_pImage, { MY_ERR( "image 0x%08x, regId %08d, coreId %d, " "threadId %d return code 0x%08x", i_pImage, i_regId, - i_coreId, io_threadId, l_rc ); + i_coreId, *i_pThreadId, l_rc ); } return l_rc; @@ -171,7 +175,7 @@ StopReturnCode_t validateSprImageInputs( void* const i_pImage, /** * @brief generates ori instruction code. * @param[in] i_Rs Source register number - * @param[in] i_Ra destination regiser number + * @param[in] i_Ra destination register number * @param[in] i_data 16 bit immediate data * @return returns 32 bit instruction representing ori instruction. */ @@ -182,7 +186,7 @@ uint32_t getOriInstruction( const uint16_t i_Rs, const uint16_t i_Ra, oriInstOpcode = 0; oriInstOpcode = ORI_OPCODE << 26; oriInstOpcode |= i_Rs << 21; - oriInstOpcode |= i_Rs << 16; + oriInstOpcode |= i_Ra << 16; oriInstOpcode |= i_data; return SWIZZLE_4_BYTE(oriInstOpcode); @@ -214,7 +218,7 @@ uint32_t getXorInstruction( const uint16_t i_Ra, const uint16_t i_Rs, xorRegInstOpcode = XOR_CONST << 1; xorRegInstOpcode |= OPCODE_31 << 26; xorRegInstOpcode |= i_Rs << 21; - xorRegInstOpcode |= i_Rs << 16; + xorRegInstOpcode |= i_Ra << 16; xorRegInstOpcode |= i_Rb << 11; return SWIZZLE_4_BYTE(xorRegInstOpcode); @@ -253,6 +257,7 @@ uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr ) { uint32_t mtsprInstOpcode = 0; uint32_t temp = (( i_Spr & 0x03FF ) << 11); + mtsprInstOpcode = (uint8_t)i_Rs << 21; mtsprInstOpcode = ( temp & 0x0000F800 ) << 5; mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5; mtsprInstOpcode |= MTSPR_BASE_OPCODE; @@ -317,13 +322,13 @@ uint32_t getMtmsrdInstruction( const uint16_t i_Rs ) StopReturnCode_t lookUpSprInImage( uint32_t* i_pThreadSectLoc, const uint32_t i_lookUpKey, const bool i_isCoreReg, - void*& io_pSprEntryLoc ) + void** io_pSprEntryLoc ) { StopReturnCode_t l_rc = STOP_SAVE_FAIL; uint32_t temp = i_isCoreReg ? CORE_SPR_SECTN_SIZE : THREAD_SECTN_SIZE; uint32_t* i_threadSectEnd = i_pThreadSectLoc + temp; uint32_t bctr_inst = SWIZZLE_4_BYTE(BLR_INST); - io_pSprEntryLoc = NULL; + *io_pSprEntryLoc = NULL; do { @@ -341,7 +346,7 @@ StopReturnCode_t lookUpSprInImage( uint32_t* i_pThreadSectLoc, if( ( temp == i_lookUpKey ) || ( temp == bctr_inst ) ) { - io_pSprEntryLoc = i_pThreadSectLoc; + *io_pSprEntryLoc = i_pThreadSectLoc; l_rc = STOP_SAVE_SUCCESS; break; } @@ -370,11 +375,8 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, { StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; uint32_t tempInst = 0; - typedef union - { - uint64_t regData; - uint16_t dataBit[4]; - } RegData; + uint64_t tempRegData = 0; + bool newEntry = true; do { @@ -385,10 +387,13 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, break; } - RegData regValue; - regValue.regData = i_regData; - tempInst = genKeyForSprLookup( i_regId ); + + if( *i_pSprEntryLocation == tempInst ) + { + newEntry = false; + } + *i_pSprEntryLocation = tempInst; i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; @@ -396,11 +401,13 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, *i_pSprEntryLocation = tempInst; i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; - tempInst = getOrisInstruction( 0, 0, regValue.dataBit[0] ); + tempRegData = i_regData >> 48; + tempInst = getOrisInstruction( 0, 0, (uint16_t)tempRegData ); *i_pSprEntryLocation = tempInst; i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; - tempInst = getOriInstruction( 0, 0, regValue.dataBit[1] ); + tempRegData = ((i_regData >> 32) & 0x0000FFFF ); + tempInst = getOriInstruction( 0, 0, (uint16_t)tempRegData ); *i_pSprEntryLocation = tempInst; i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; @@ -408,11 +415,13 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, *i_pSprEntryLocation = tempInst; i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; - tempInst = getOrisInstruction( 0, 0, regValue.dataBit[2] ); + tempRegData = ((i_regData >> 16) & 0x000000FFFF ); + tempInst = getOrisInstruction( 0, 0, (uint16_t)tempRegData ); *i_pSprEntryLocation = tempInst; i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; - tempInst = getOriInstruction( 0, 0, regValue.dataBit[3] ); + tempRegData = (uint16_t)i_regData; + tempInst = getOriInstruction( 0, 0, (uint16_t)i_regData ); *i_pSprEntryLocation = tempInst; i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; @@ -431,11 +440,13 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, } *i_pSprEntryLocation = tempInst; - i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; - - tempInst = SWIZZLE_4_BYTE(BLR_INST); - *i_pSprEntryLocation = tempInst; + if( newEntry ) + { + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + tempInst = SWIZZLE_4_BYTE(BLR_INST); + *i_pSprEntryLocation = tempInst; + } } while(0); @@ -461,16 +472,18 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage, void* pThreadLocation = NULL; bool threadScopeReg = false; - l_rc = getCoreAndThread( i_pImage, i_pir, coreId, threadId ); + l_rc = getCoreAndThread( i_pImage, i_pir, &coreId, &threadId ); + MY_INF( " PIR 0x%016llx coreId %d threadid %d " " registerId %d", i_pir, coreId, threadId, i_regId ); + // First of all let us validate all input arguments. l_rc = validateSprImageInputs( i_pImage, i_regId, coreId, - threadId, - threadScopeReg ); + &threadId, + &threadScopeReg ); if( l_rc ) { @@ -506,10 +519,9 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage, l_rc = lookUpSprInImage( (uint32_t*)pThreadLocation, lookUpKey, threadScopeReg, - pSprEntryLocation ); + &pSprEntryLocation ); } - if( l_rc ) { MY_ERR("Invalid or corrupt SPR entry. CoreId 0x%08x threadId ", @@ -671,14 +683,14 @@ StopReturnCode_t editScomEntry( uint32_t i_scomAddr, uint64_t i_scomData, case P9_STOP_SCOM_NOOP: { uint32_t nopInst = getOriInstruction( 0, 0, 0 ); - i_pEntryLocation->scomEntryHeader = SCOM_ENTRY_START; + i_pEntryLocation->scomEntryHeader = SWIZZLE_4_BYTE(SCOM_ENTRY_START); i_pEntryLocation->scomEntryData = nopInst; i_pEntryLocation->scomEntryAddress = nopInst; } break; case P9_STOP_SCOM_APPEND: - i_pEntryLocation->scomEntryHeader = SCOM_ENTRY_START; + i_pEntryLocation->scomEntryHeader = SWIZZLE_4_BYTE(SCOM_ENTRY_START); i_pEntryLocation->scomEntryData = i_scomData; i_pEntryLocation->scomEntryAddress = i_scomAddr; break; @@ -716,7 +728,7 @@ StopReturnCode_t updateScomEntry( uint32_t i_scomAddr, uint64_t i_scomData, break; } - i_scomEntry->scomEntryHeader = SCOM_ENTRY_START; // done for now + i_scomEntry->scomEntryHeader = SWIZZLE_4_BYTE(SCOM_ENTRY_START); // done for now i_scomEntry->scomEntryAddress = i_scomAddr; i_scomEntry->scomEntryData = i_scomData; @@ -830,25 +842,27 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, uint32_t swizzleAddr = SWIZZLE_4_BYTE(i_scomAddress); uint64_t swizzleData = SWIZZLE_8_BYTE(i_scomData); uint32_t swizzleAttn = SWIZZLE_4_BYTE(ATTN_OPCODE); + uint32_t swizzleEntry = SWIZZLE_4_BYTE(SCOM_ENTRY_START); uint32_t index = 0; for( index = 0; index < entryLimit; ++index ) { - if( ( swizzleAddr == pScomEntry[index].scomEntryAddress ) && - ( !pEntryLocation ) ) + uint32_t entrySwzAddress = pScomEntry[index].scomEntryAddress; + + if( ( swizzleAddr == entrySwzAddress ) && ( !pEntryLocation ) ) { pEntryLocation = &pScomEntry[index]; } - if( (( nopInst == pScomEntry[index].scomEntryAddress ) || - ( swizzleAttn == pScomEntry[index].scomEntryAddress )) && + if( (( nopInst == entrySwzAddress ) || + ( swizzleAttn == entrySwzAddress )) && ( !pNopLocation ) ) { pNopLocation = &pScomEntry[index]; } - if( SCOM_ENTRY_START == pScomEntry[index].scomEntryHeader ) + if( swizzleEntry == pScomEntry[index].scomEntryHeader ) { continue; } @@ -981,8 +995,8 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, } +#ifdef __cplusplus } //namespace stopImageSection ends -#ifdef __cplusplus } //extern "C" #endif diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H index 8c15f3b5..300213d5 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H @@ -37,8 +37,10 @@ // *HWP Level : 2 // *HWP Consumed by : HB:HYP +#ifdef __cplusplus namespace stopImageSection { +#endif /** * @brief all SPRs and MSR for which register restore is to be supported. @@ -149,8 +151,7 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, #ifdef __cplusplus } // extern "C" -#endif }; // namespace stopImageSection ends - +#endif //__cplusplus #endif //__P9_STOP_IMAGE_API_ diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H b/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H index 25247497..ac69c7ce 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H @@ -48,9 +48,9 @@ #ifdef __cplusplus extern "C" { -#endif namespace stopImageSection { +#endif typedef struct { @@ -133,7 +133,8 @@ enum SCOM_SIZE_PER_CACHE_CHIPLET )); #ifdef __cplusplus } // extern "C" -#endif } //namespace stopImageSection ends +#endif //__cplusplus + #endif diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C b/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C index af4a7f1f..27f3ad61 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C @@ -36,18 +36,21 @@ #include "p9_stop_api.H" #include "p9_stop_util.H" #include "p9_stop_data_struct.H" + +#ifdef __cplusplus namespace stopImageSection { +#endif /** * @brief Returns proc chip's fuse mode status. * @param i_pImage points to start of chip's HOMER image. - * @param o_fuseMode true if system is in fuse mode, false otherwise. + * @param o_fuseMode points to fuse mode information. * @return STOP_SAVE_SUCCESS if functions succeeds, error code otherwise. */ -StopReturnCode_t isFusedMode( void* const i_pImage, bool& o_fuseMode ) +StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fuseMode ) { - o_fuseMode = false; + *o_fuseMode = false; StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; do @@ -72,7 +75,7 @@ StopReturnCode_t isFusedMode( void* const i_pImage, bool& o_fuseMode ) if( (uint8_t) FUSE_MODE == pHomer->fuseModeStatus ) { - o_fuseMode = true; + *o_fuseMode = true; break; } @@ -94,7 +97,7 @@ StopReturnCode_t isFusedMode( void* const i_pImage, bool& o_fuseMode ) //---------------------------------------------------------------------- StopReturnCode_t getCoreAndThread( void* const i_pImage, const uint64_t i_pir, - uint32_t& o_coreId, uint32_t& o_threadId ) + uint32_t* o_pCoreId, uint32_t* o_pThreadId ) { StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; @@ -109,9 +112,9 @@ StopReturnCode_t getCoreAndThread( void* const i_pImage, const uint64_t i_pir, // whereas b30 and b31 gives logical and virtual thread id. bool fuseMode = false; uint8_t coreThreadInfo = (uint8_t)i_pir; - o_coreId = 0; - o_threadId = 0; - l_rc = isFusedMode( i_pImage, fuseMode ); + *o_pCoreId = 0; + *o_pThreadId = 0; + l_rc = isFusedMode( i_pImage, &fuseMode ); if( l_rc ) { @@ -123,56 +126,55 @@ StopReturnCode_t getCoreAndThread( void* const i_pImage, const uint64_t i_pir, { if( coreThreadInfo & FUSE_BIT1 ) { - o_threadId = 2; + *o_pThreadId = 2; } if( coreThreadInfo & FUSE_BIT2 ) { - o_threadId += 1; + *o_pThreadId += 1; } if( coreThreadInfo & FUSE_BIT0 ) { - o_coreId = 2; + *o_pCoreId = 2; } if( coreThreadInfo & FUSE_BIT3 ) { - o_coreId += 1; + *o_pCoreId += 1; } } else { if( coreThreadInfo & FUSE_BIT0 ) { - o_coreId = 2; + *o_pCoreId = 2; } if ( coreThreadInfo & FUSE_BIT1 ) { - o_coreId += 1; + *o_pCoreId += 1; } if( coreThreadInfo & FUSE_BIT2 ) { - o_threadId = 2; + *o_pThreadId = 2; } if( coreThreadInfo & FUSE_BIT3 ) { - o_threadId += 1; + *o_pThreadId += 1; } - - } //quad field is not affected by fuse mode - o_coreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 ); - + *o_pCoreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 ); } while(0); return l_rc; } +#ifdef __cplusplus }//namespace stopImageSection ends +#endif |