CME/SGPE: STOP image updates and fixes

patchset 1: fix quad spwu(initial)
patchset 2: fix quad spwu
patchset 3: set scan0 and arrayinit code as default
patchset 4: fix for stop3 being nop
patchset 5: fix unitified interrupt handler hole of ee bit
patchset 6: workaround for pbie read ptr hw bug(initial)
patchset 7: optional debug trap based on occ flag[12]/[13]
            fix stop8 history update typo
            update fix in patchset 6(still more to come)
patchset 8: default disable HW386311_PBIE_RW_PTR_STOP11_FIX
patchset 9: workaround for pbie read ptr hw bug(complete)
patchset 10:update workaround debug trace and RTC comment
patchset 11:add more pk traces to workaround and fix addr
patchset 12:fix region bits for the workaround
patchset 13:fix region bits ver2
patchset 14:rebase for merge conflict
patchset 15:reset scan0/arrayinit to on after rebase
patchset 16:fix workaround ring length for rotate back
patchset 17:fix pk trace on printing 64bit variables
patchset 18:fix l3 purge abort
            add more traces in partial good config
patchset 19:fix history reporting in scominit
patchset 20:fix spin bug on 6bits
            change thread stack size on cme to 512
            fix sgpe default pk_app_cfg on istep15_hack
patchset 21:fix a typo in patchset 20
patchset 22:fix quad stop history bit0
patchset 23:fix typo in previous 22
patchset 24:add more debug thrace for workaround
            have parameter for each thread stack size
patchset 25:fix typo in 24
patchset 26:fix quad spwu done and possible for pfet error
patchset 27:fix stupid kernel bug to cause 0x03abcdef
patchset 28:1) add dls+stop1 workaround for pls+srr1 issue
            2) some code for bce irritator
            3) add block wakeup support and db1+db2 change
            4) Note: one marker change for doorbell
patchset 29:add broadside support for scan0 module
patchset 30:add fused core mode workaround
            fix workaround compiler define
patchset 31:fix qspwu parital good case
            fix compiler error with broadside mode
            fix conflict of enum between two headers
patchset 32:fix stop handler anormaly introduced by
            unified interrupt handler returns group id
patchset 33:fix a bug introduced by patchset 32
patchset 34:clean scan0 region after workaround
patchset 35:Rebased

Change-Id: I93f9f02b337ee953886cb72f0f1d0058cf6e04b3
Original-Change-Id: I315d8ccc425a0d420a77d82814962ff6eaa38152
RTC: 161155
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29405
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

3 files changed, 150 insertions, 25 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 2dadb37f..29fefc38 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -60,6 +60,7 @@ p9_cme_stop_entry()
     uint32_t        deeper_core         = 0;
     uint32_t        core_aborted        = 0;
     uint32_t        core_catchup        = 0;
+    uint32_t        core_stop1          = 0;
     uint32_t        core;
     uint32_t        loop;
     uint32_t        pm_states;
@@ -129,12 +130,24 @@ p9_cme_stop_entry()
         {
             G_cme_stop_record.req_level_c0 =
                 (pm_states & BITS32(4, 4)) >> SHIFT32(7);
+
+            if (G_cme_stop_record.req_level_c0 == STOP_LEVEL_1)
+            {
+                G_cme_stop_record.act_level_c0 = STOP_LEVEL_1;
+                core_stop1 |= CME_MASK_C0;
+            }
         }
 
         if (core & CME_MASK_C1)
         {
             G_cme_stop_record.req_level_c1 =
                 (pm_states & BITS32(8, 4)) >> SHIFT32(11);
+
+            if (G_cme_stop_record.req_level_c1 == STOP_LEVEL_1)
+            {
+                G_cme_stop_record.act_level_c1 = STOP_LEVEL_1;
+                core_stop1 |= CME_MASK_C1;
+            }
         }
 
         G_cme_stop_record.core_running &= ~core;
@@ -146,16 +159,32 @@ p9_cme_stop_entry()
                  G_cme_stop_record.act_level_c1);
 
         // Return error if target STOP level == 1(Nap)
-        if((core == CME_MASK_C0 &&
-            G_cme_stop_record.req_level_c0 <= STOP_LEVEL_1) ||
-           (core == CME_MASK_C1 &&
-            G_cme_stop_record.req_level_c1 <= STOP_LEVEL_1) ||
-           (core == CME_MASK_BC &&
-            (G_cme_stop_record.req_level_c0 <= STOP_LEVEL_1 ||
-             G_cme_stop_record.req_level_c1 <= STOP_LEVEL_1)))
+        if(core_stop1)
         {
+#if HW386841_PLS_SRR1_DLS_STOP1_FIX
+            // Acknowledge the STOP Entry to PC with a pulse
+            out32(CME_LCL_SICR_OR,  core_stop1 << SHIFT32(1));
+            out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1));
+
+            CME_STOP_UPDATE_HISTORY(core_stop1,
+                                    STOP_CORE_IS_GATED,
+                                    STOP_TRANS_COMPLETE,
+                                    STOP_LEVEL_1,
+                                    STOP_LEVEL_1,
+                                    STOP_REQ_ENABLE,
+                                    STOP_ACT_ENABLE);
+
+            core = core & ~core_stop1;
+
+            if (!core)
+            {
+                break;
+            }
+
+#else
             PK_TRACE("Error: stop 1 requested to hcode");
             pk_halt();
+#endif
         }
 
         //----------------------------------------------------------------------
@@ -233,10 +262,11 @@ p9_cme_stop_entry()
         //=============================
 
         /// Set LMCR bits 12/13, 14/15 (override disables)
+        out32(CME_LCL_LMCR_OR, (core << SHIFT32(15)));
 #if SPWU_AUTO
         out32(CME_LCL_LMCR_OR, (core << SHIFT32(13)));
 #endif
-        out32(CME_LCL_LMCR_OR, (core << SHIFT32(15)));
+
         PK_TRACE("SE2.h");
         // Raise Core-L2 + Core-CC Quiesces
         out32(CME_LCL_SICR_OR, (core << SHIFT32(7)) | (core << SHIFT32(9)));
@@ -508,18 +538,17 @@ p9_cme_stop_entry()
 
         if (target_level == 3)
         {
+            /*
+                        //==========================
+                        MARK_TAG(SE_CORE_VMIN, core)
+                        //==========================
 
-            //==========================
-            MARK_TAG(SE_CORE_VMIN, core)
-            //==========================
-
-            PK_TRACE("SE3.a");
-            // Enable IVRM if not already
+                        PK_TRACE("SE3.a");
+                        // Enable IVRM if not already
 
-            PK_TRACE("SE3.b");
+                        PK_TRACE("SE3.b");
 
-            // Drop to Vmin
-            /*
+                        // Drop to Vmin
                         if(core & CME_MASK_C0)
                         {
                             G_cme_stop_record.act_level_c0 = STOP_LEVEL_3;
@@ -868,7 +897,7 @@ p9_cme_stop_entry()
     //--------------------------------------------------------------------------
 
     // Release PPM Write Protection
-    CME_PUTSCOM(CPPM_CPMMR_CLR, core, BIT64(0));
+    CME_PUTSCOM(CPPM_CPMMR_CLR, CME_MASK_BC, BIT64(0));
 
     //============================
     MARK_TRAP(ENDSCOPE_STOP_ENTRY)
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index 982809a3..4607518f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -107,6 +107,9 @@ extern "C" {
 #define PERV_SCAN_REGION_TYPE    0x10030005
 #define PERV_CLK_REGION          0x10030006
 #define PERV_BIST                0x1003000B
+#define PERV_OPCG_CAPT0          0x10030010
+#define PERV_OPCG_CAPT1          0x10030011
+#define PERV_OPCG_CAPT2          0x10030012
 #define PERV_CPLT_STAT0          0x10000100
 
 /// Macro to update STOP History
@@ -172,6 +175,11 @@ enum SGPE_STOP_VECTOR_INDEX
     VECTOR_CONFIG                     = 2
 };
 
+#if HW386311_PBIE_RW_PTR_STOP11_FIX
+#define EXTRACT_RING_BITS(mask, ring, save) save = (ring) & (mask);
+#define RESTORE_RING_BITS(mask, ring, save) ring = (((ring) & (~mask)) | (save));
+#endif
+
 typedef struct
 {
     // requested stop state calculated from core stop levels
@@ -193,7 +201,7 @@ typedef struct
     uint32_t ex_r[3];
     uint32_t ex_b[3];
     uint32_t quad[3];
-    uint32_t qswu[2];
+    uint32_t qswu[3];
 } sgpe_group_t;
 
 /// SGPE Stop Score Board Structure
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index bd771b4e..187ad5fe 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -27,6 +27,30 @@
 #include "p9_sgpe_stop_enter_marks.h"
 
 extern SgpeStopRecord G_sgpe_stop_record;
+#if HW386311_PBIE_RW_PTR_STOP11_FIX
+uint64_t G_ring_save[MAX_QUADS][8] =
+{
+    {0, 0, 0, 0, 0, 0, 0, 0},
+    {0, 0, 0, 0, 0, 0, 0, 0},
+    {0, 0, 0, 0, 0, 0, 0, 0},
+    {0, 0, 0, 0, 0, 0, 0, 0},
+    {0, 0, 0, 0, 0, 0, 0, 0},
+    {0, 0, 0, 0, 0, 0, 0, 0}
+};
+uint64_t G_ring_spin[10][2] =
+{
+    {0,    0},
+    {5039, 0xE000000000000000}, //3
+    {5100, 0xC1E061FFED5F0000}, //29
+    {5664, 0xE000000000000000}, //3
+    {5725, 0xC1E061FFED5F0000}, //29
+    {5973, 0xE000000000000000}, //3
+    {6034, 0xC1E061FFED5F0000}, //29
+    {6282, 0xE000000000000000}, //3
+    {6343, 0xC1E061FFED5F0000}, //29
+    {17871, 0}                  //128
+};
+#endif
 
 int
 p9_sgpe_stop_entry()
@@ -43,6 +67,9 @@ p9_sgpe_stop_entry()
     uint64_t     scom_data;
     uint64_t     temp_data;
     ppm_sshsrc_t hist;
+#if HW386311_PBIE_RW_PTR_STOP11_FIX
+    int          spin;
+#endif
 
     //================================
     MARK_TAG(BEGINSCOPE_STOP_ENTRY, 0)
@@ -56,7 +83,7 @@ p9_sgpe_stop_entry()
     for(qloop = 0; qloop < MAX_QUADS; qloop++)
     {
 
-        if (G_sgpe_stop_record.group.qswu[VECTOR_EXIT] & BIT32(qloop))
+        if (G_sgpe_stop_record.group.qswu[VECTOR_CONFIG] & BIT32(qloop))
         {
             continue;
         }
@@ -127,6 +154,8 @@ p9_sgpe_stop_entry()
         G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG];
     G_sgpe_stop_record.group.ex_r[VECTOR_ENTRY] &=
         G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG];
+    G_sgpe_stop_record.group.quad[VECTOR_ENTRY] &=
+        G_sgpe_stop_record.group.quad[VECTOR_CONFIG];
 
     PK_TRACE("Core Entry Vectors:   X[%x] X0[%x] X1[%x] Q[%x]",
              G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY],
@@ -301,7 +330,7 @@ p9_sgpe_stop_entry()
             climit = CORES_PER_QUAD;
             G_sgpe_stop_record.state[qloop].act_state_x1 = STOP_LEVEL_8;
             entry_ongoing[1] =
-                G_sgpe_stop_record.state[qloop].req_state_x0 == STOP_LEVEL_8 ?
+                G_sgpe_stop_record.state[qloop].req_state_x1 == STOP_LEVEL_8 ?
                 STOP_TRANS_COMPLETE : STOP_TRANS_ENTRY;
         }
         else
@@ -365,7 +394,7 @@ p9_sgpe_stop_entry()
         // Update Quad STOP History
         SGPE_STOP_UPDATE_HISTORY(qloop,
                                  QUAD_ADDR_BASE,
-                                 STOP_CORE_IS_GATED,
+                                 STOP_CACHE_IS_GATED,
                                  STOP_TRANS_ENTRY,
                                  G_sgpe_stop_record.state[qloop].req_state_q,
                                  STOP_LEVEL_11,
@@ -414,11 +443,15 @@ p9_sgpe_stop_entry()
         {
 #if !SKIP_L3_PURGE_ABORT
 
-            if (in32(OCB_OISR1) & (BITS32(15, 2) & BIT32(19)))
+            if (in32(OCB_OISR1) & (BITS32(15, 2) | BIT32(19)))
             {
+                PK_TRACE("SE: interrupt detected");
+
                 if ((in32(OCB_OPITNPRA(2)) & BITS32((qloop << 2), 4)) ||
                     (in32(OCB_OPITNPRA(3)) & BITS32((qloop << 2), 4)))
                 {
+                    PK_TRACE("SE: core interrupt detected");
+
                     for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)
                     {
                         if ((in32(OCB_OPIT2CN(((qloop << 2) + cloop))) &
@@ -426,6 +459,7 @@ p9_sgpe_stop_entry()
                             (in32(OCB_OPIT3CN(((qloop << 2) + cloop))) &
                              TYPE3_PAYLOAD_EXIT_EVENT))
                         {
+                            PK_TRACE("SE: core wakeup detected");
                             l3_purge_aborted = 1;
                             break;
                         }
@@ -435,6 +469,7 @@ p9_sgpe_stop_entry()
                 if ((in32(OCB_OPIT6PRB) & BIT32(qloop)) &&
                     (in32(OCB_OPIT6QN(qloop)) & TYPE6_PAYLOAD_EXIT_EVENT))
                 {
+                    PK_TRACE("SE: quad wakeup detected");
                     l3_purge_aborted = 1;
                 }
 
@@ -654,6 +689,60 @@ p9_sgpe_stop_entry()
         MARK_TAG(SE_POWER_OFF_CACHE, (32 >> qloop))
         //=========================================
 
+#if HW386311_PBIE_RW_PTR_STOP11_FIX
+        // bit4,5,11 = perv/eqpb/pbieq, bit59 = inex
+        PK_TRACE("SE: Setup scan register to select the ring");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), BITS64(4, 2) | BIT64(11) | BIT64(59));
+
+        PK_TRACE("SE: checkword set");
+        scom_data = 0xa5a5a5a5a5a5a5a5;
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data);
+
+        for(spin = 1;; spin++)
+        {
+            PK_TRACE("SE: spin ring loop%d", spin);
+            scom_data = (G_ring_spin[spin][0] - G_ring_spin[spin - 1][0]) << 32;
+            GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data);
+
+            PK_TRACE("SE: Poll OPCG done for ring spin");
+
+            do
+            {
+                GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x10000100, qloop), scom_data);
+            }
+            while(~scom_data & BIT64(8));
+
+            if (spin == 9)
+            {
+                PK_TRACE("SE: checkword check");
+                GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data);
+
+                if (scom_data != 0xa5a5a5a5a5a5a5a5)
+                {
+                    PK_TRACE("checkword[%x%x] failed", UPPER32(scom_data), LOWER32(scom_data));
+                    pk_halt();
+                }
+
+                break;
+            }
+
+            PK_TRACE("SE: save pbie read ptr");
+            GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data);
+            EXTRACT_RING_BITS(G_ring_spin[spin][1], scom_data, G_ring_save[qloop][spin - 1]);
+            PK_TRACE("SE: mask: %8x %8x",
+                     UPPER32(G_ring_spin[spin][1]),
+                     LOWER32(G_ring_spin[spin][1]));
+            PK_TRACE("SE: ring: %8x %8x",
+                     UPPER32(scom_data),
+                     LOWER32(scom_data));
+            PK_TRACE("SE: save: %8x %8x",
+                     UPPER32(G_ring_save[qloop][spin - 1]),
+                     LOWER32(G_ring_save[qloop][spin - 1]));
+        }
+
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), 0);
+#endif
+
         // DD: Assert Cache Vital Thold/PCB Fence/Electrical Fence
         PK_TRACE("SE11.q");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(25));
@@ -755,7 +844,7 @@ p9_sgpe_stop_entry()
 
         SGPE_STOP_UPDATE_HISTORY(qloop,
                                  QUAD_ADDR_BASE,
-                                 STOP_CORE_IS_GATED,
+                                 STOP_CACHE_IS_GATED,
                                  STOP_TRANS_COMPLETE,
                                  STOP_LEVEL_11,
                                  STOP_LEVEL_11,
@@ -778,7 +867,6 @@ p9_sgpe_stop_entry()
     {
         if (G_sgpe_stop_record.group.qswu[VECTOR_ENTRY] & BIT32(qloop))
         {
-            GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_CLR, qloop), BIT64(0));
             G_sgpe_stop_record.group.qswu[VECTOR_ENTRY] &= ~BIT32(qloop);
         }
     }