diff options
| author | Yue Du <daviddu@us.ibm.com> | 2018-05-08 21:28:45 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-05-31 10:37:05 -0500 |
| commit | 63c49e23a2cd0058eb5ca993480b3644a3c23560 (patch) | |
| tree | d6f42589834524d02240ea4da0b3d30d51b9a837 | |
| parent | 331a145623c27b41bcf712f4616ebe650114f099 (diff) | |
| download | talos-hcode-63c49e23a2cd0058eb5ca993480b3644a3c23560.tar.gz talos-hcode-63c49e23a2cd0058eb5ca993480b3644a3c23560.zip | |
STOP: CME/SGPE Hcode size reduction via global use of literals
Key_Cronus_Test=PM_REGRESS
Change-Id: Ic9ec56beff42f052e88bde98e90e01d44ac43e4f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58542
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
32 files changed, 474 insertions, 372 deletions
diff --git a/import/chips/p9/common/pmlib/include/stop_sgpe_cme_api.h b/import/chips/p9/common/pmlib/include/stop_sgpe_cme_api.h index 81b6ba9e..9754a706 100644 --- a/import/chips/p9/common/pmlib/include/stop_sgpe_cme_api.h +++ b/import/chips/p9/common/pmlib/include/stop_sgpe_cme_api.h @@ -85,8 +85,6 @@ enum CME_DOORBELL_MESSAGE_IDS MSGID_DB1_SUSPEND_STOP_EXITS = 0x0D, // 1101 MSGID_DB1_SUSPEND_STOP_ENTRIES_EXITS = 0x0F, // 1111 - MSGID_DB1_WAKEUP_GRANTED = 0x10, - MSGID_DB2_DECREMENTER_WAKEUP = 0x01, MSGID_DB2_RESONANT_CLOCK_DISABLE = 0x02, MSGID_DB2_RESONANT_CLOCK_ENABLE = 0x03 diff --git a/import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h b/import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h index e8f843a6..84721f0c 100644 --- a/import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h +++ b/import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h @@ -26,29 +26,9 @@ #ifndef __IPC_MESSAGES_H__ #define __IPC_MESSAGES_H__ -//--------------- -// IPC from SGPE to PGPE -//--------------- -enum MESSAGE_ID_IPI2HI_SGPE_PGPE -{ - MSGID_SGPE_PGPE_UPDATE_ACTIVE_CORES = 0x8, - MSGID_SGPE_PGPE_UPDATE_ACTIVE_QUADS = 0x9, - MSGID_SGPE_PGPE_SUSPEND_PSTATES = 0x10 -}; - -//--------------- -// IPC from PGPE to SGPE -//--------------- -enum MESSAGE_ID_IPI3HI_PGPE_SGPE -{ - MSGID_PGPE_SGPE_INVALID = 0, - MSGID_PGPE_SGPE_CONTROL_STOP_UPDATES = 1, - MSGID_PGPE_SGPE_SUSPEND_STOP = 2 -}; - enum CTRL_STOP_UPDATES_ACTIONS { - CTRL_STOP_UPDT_ENABLE_CORE = 0x1, + CTRL_STOP_UPDT_ENABLE_CORE = 0x1, }; diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h index f3ad4f98..fb6a6be9 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h @@ -28,6 +28,38 @@ #include "pk.h" #include "p9_pm_hcd_flags.h" + +extern uint32_t G_CME_LCL_EINR; +extern uint32_t G_CME_LCL_EISR; +extern uint32_t G_CME_LCL_EISR_CLR; +extern uint32_t G_CME_LCL_EIMR_CLR; +extern uint32_t G_CME_LCL_EIMR_OR; +extern uint32_t G_CME_LCL_EIPR_CLR; +extern uint32_t G_CME_LCL_EIPR_OR; +extern uint32_t G_CME_LCL_EITR_OR; +extern uint32_t G_CME_LCL_FLAGS; +extern uint32_t G_CME_LCL_FLAGS_CLR; +extern uint32_t G_CME_LCL_FLAGS_OR; +extern uint32_t G_CME_LCL_SRTCH0; +extern uint32_t G_CME_LCL_TSEL; +extern uint32_t G_CME_LCL_TBR; +extern uint32_t G_CME_LCL_DBG; +extern uint32_t G_CME_LCL_LMCR; +extern uint32_t G_CME_LCL_LMCR_CLR; +extern uint32_t G_CME_LCL_LMCR_OR; +extern uint32_t G_CME_LCL_ICSR; +extern uint32_t G_CME_LCL_ICRR; +extern uint32_t G_CME_LCL_ICCR_CLR; +extern uint32_t G_CME_LCL_ICCR_OR; +extern uint32_t G_CME_LCL_SISR; +extern uint32_t G_CME_LCL_SICR_CLR; +extern uint32_t G_CME_LCL_SICR_OR; +extern uint32_t G_CME_LCL_PSCRS00; +extern uint32_t G_CME_LCL_PSCRS10; +extern uint32_t G_CME_LCL_PSCRS20; +extern uint32_t G_CME_LCL_PSCRS30; + + #if !DISABLE_PERIODIC_CORE_QUIESCE && (NIMBUS_DD_LEVEL == 20 || NIMBUS_DD_LEVEL == 21 || CUMULUS_DD_LEVEL == 10) typedef struct diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c index 501e56e7..92d1a8bd 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c @@ -45,6 +45,38 @@ CmeStopRecord G_cme_stop_record __attribute__((section (".dump_ptr_stop"))) = {{ CmeFitRecord G_cme_fit_record = {0, 0, 0, 0, 0xFFFFFFFF, 0}; #endif + +uint32_t G_CME_LCL_EINR = CME_LCL_EINR; +uint32_t G_CME_LCL_EISR = CME_LCL_EISR; +uint32_t G_CME_LCL_EISR_CLR = CME_LCL_EISR_CLR; +uint32_t G_CME_LCL_EIMR_CLR = CME_LCL_EIMR_CLR; +uint32_t G_CME_LCL_EIMR_OR = CME_LCL_EIMR_OR; +uint32_t G_CME_LCL_EIPR_CLR = CME_LCL_EIPR_CLR; +uint32_t G_CME_LCL_EIPR_OR = CME_LCL_EIPR_OR; +uint32_t G_CME_LCL_EITR_OR = CME_LCL_EITR_OR; +uint32_t G_CME_LCL_FLAGS = CME_LCL_FLAGS; +uint32_t G_CME_LCL_FLAGS_CLR = CME_LCL_FLAGS_CLR; +uint32_t G_CME_LCL_FLAGS_OR = CME_LCL_FLAGS_OR; +uint32_t G_CME_LCL_SRTCH0 = CME_LCL_SRTCH0; +uint32_t G_CME_LCL_TSEL = CME_LCL_TSEL; +uint32_t G_CME_LCL_TBR = CME_LCL_TBR; +uint32_t G_CME_LCL_DBG = CME_LCL_DBG; +uint32_t G_CME_LCL_LMCR = CME_LCL_LMCR; +uint32_t G_CME_LCL_LMCR_CLR = CME_LCL_LMCR_CLR; +uint32_t G_CME_LCL_LMCR_OR = CME_LCL_LMCR_OR; +uint32_t G_CME_LCL_ICSR = CME_LCL_ICSR; +uint32_t G_CME_LCL_ICRR = CME_LCL_ICRR; +uint32_t G_CME_LCL_ICCR_CLR = CME_LCL_ICCR_CLR; +uint32_t G_CME_LCL_ICCR_OR = CME_LCL_ICCR_OR; +uint32_t G_CME_LCL_SISR = CME_LCL_SISR; +uint32_t G_CME_LCL_SICR_CLR = CME_LCL_SICR_CLR; +uint32_t G_CME_LCL_SICR_OR = CME_LCL_SICR_OR; +uint32_t G_CME_LCL_PSCRS00 = CME_LCL_PSCRS00; +uint32_t G_CME_LCL_PSCRS10 = CME_LCL_PSCRS10; +uint32_t G_CME_LCL_PSCRS20 = CME_LCL_PSCRS20; +uint32_t G_CME_LCL_PSCRS30 = CME_LCL_PSCRS30; + + #if !DISABLE_CME_FIT_TIMER void fit_handler() @@ -83,7 +115,7 @@ void dec_handler() void p9_cme_hipri_ext_handler(uint32_t task_idx) { //Only look at bits 0,1,2,3, and 5 - uint32_t eisr_subset = in32(CME_LCL_EISR) & BITS32(0, 6); + uint32_t eisr_subset = in32(G_CME_LCL_EISR) & BITS32(0, 6); //exclude bit 4: PGPE Heartbeat lost eisr_subset &= ~BIT32(4); @@ -91,7 +123,7 @@ void p9_cme_hipri_ext_handler(uint32_t task_idx) uint32_t bitnum = cntlz32(eisr_subset); - if(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_PM_DEBUG_HALT_ENABLE)) + if(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_PM_DEBUG_HALT_ENABLE)) { switch (bitnum) { @@ -117,7 +149,7 @@ void p9_cme_hipri_ext_handler(uint32_t task_idx) //if debug halt is NOT enabled, clear the ones reported in the trace //above and return - out32(CME_LCL_EISR_CLR, eisr_subset); + out32(G_CME_LCL_EISR_CLR, eisr_subset); } IOTA_BEGIN_TASK_TABLE @@ -165,17 +197,17 @@ int main() // Clear SPRG0 ppe42_app_ctx_set(0); - G_cme_record.core_enabled = in32(CME_LCL_FLAGS) & + G_cme_record.core_enabled = in32(G_CME_LCL_FLAGS) & (BIT32(CME_FLAGS_CORE0_GOOD) | BIT32(CME_FLAGS_CORE1_GOOD)); PK_TRACE("CME Register Partial Good Cores[%d]", G_cme_record.core_enabled); #if defined(USE_CME_QUEUED_SCOM) || defined(USE_CME_QUEUED_SCAN) PK_TRACE("CME Enabling Queued Scom/Scan"); - out32(CME_LCL_LMCR_OR, BITS32(8, 2)); + out32(G_CME_LCL_LMCR_OR, BITS32(8, 2)); #endif PK_TRACE("Set Watch Dog Timer Rate to 6 and FIT Timer Rate to 8"); - out32(CME_LCL_TSEL, (BITS32(1, 2) | BIT32(4))); + out32(G_CME_LCL_TSEL, (BITS32(1, 2) | BIT32(4))); #if (!DISABLE_CME_FIT_TIMER || ENABLE_CME_DEC_TIMER) diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c index 5d044856..e802448e 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c @@ -68,19 +68,19 @@ void p9_cme_pstate_sibling_lock_and_intercme_protocol(INTERCME_MSG_LOCK_ACTION i } // Block on the intercme0/intercme1/intercme2 interrupt - while((!(in32(CME_LCL_EISR) & BIT32(7))) && + while((!(in32(G_CME_LCL_EISR) & BIT32(7))) && (!(in32_sh(CME_LCL_EISR) & BIT64SH(38)))) {} //If INTERCME_DIRECT_IN1, then error. if(in32_sh(CME_LCL_EISR) & BIT64SH(38)) { - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PSTATES_SUSPENDED)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PSTATES_SUSPENDED)); p9_cme_pstate_pmsr_updt(); intercme_direct(INTERCME_DIRECT_IN1, INTERCME_DIRECT_ACK, 0); } //If INTERCME_DIRECT_IN0, then process DB0 data - if(in32(CME_LCL_EISR) & BIT32(7)) + if(in32(G_CME_LCL_EISR) & BIT32(7)) { p9_cme_pstate_process_db0_sibling(); } @@ -99,7 +99,7 @@ void p9_cme_pstate_process_db0_sibling() PK_TRACE_INF("INTER0: Enter"); - dbQuadInfo = (dbData.value >> (in32(CME_LCL_SRTCH0) & + dbQuadInfo = (dbData.value >> (in32(G_CME_LCL_SRTCH0) & (BITS32(CME_SCRATCH_LOCAL_PSTATE_IDX_START, CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH) ))) & 0xFF; dbBit8_15 = (dbData.value & BITS64(8, 8)) >> SHIFT64(15); @@ -167,11 +167,11 @@ void p9_cme_pstate_process_db0_sibling() switch(dbBit8_15) { case DB0_PMSR_UPDT_SET_PSTATES_SUSPENDED: - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PSTATES_SUSPENDED)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PSTATES_SUSPENDED)); break; case DB0_PMSR_UPDT_CLEAR_PSTATES_SUSPENDED: - out32(CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_PSTATES_SUSPENDED)); + out32(G_CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_PSTATES_SUSPENDED)); break; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c index d0b00ca3..93b51cb7 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c @@ -128,7 +128,7 @@ uint32_t poll_dpll_stat() // DYNAMIC_PROTECT -> DPLL Mode 5 // DPLL Mode 2 - if(!(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE))) + if(!(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE))) { PK_TRACE_INF("Poll on DPLL_STAT[freq_change=0]"); @@ -155,7 +155,7 @@ uint32_t poll_dpll_stat() CME_GETSCOM(CPPM_CSAR, G_cme_pstate_record.firstGoodCoreMask, csar.value); //Read TimebaseStart - tbStart = in32(CME_LCL_TBR); + tbStart = in32(G_CME_LCL_TBR); do { @@ -169,7 +169,7 @@ uint32_t poll_dpll_stat() } //Read TimebaseEnd - tbEnd = in32(CME_LCL_TBR); + tbEnd = in32(G_CME_LCL_TBR); //Compute Elapsed Count with accounting for Timebase Wrapping if (tbEnd > tbStart) @@ -276,22 +276,22 @@ void ippm_write(uint32_t addr, uint64_t data) void intercme_msg_send(uint32_t msg, INTERCME_MSG_TYPE type) { - out32(CME_LCL_ICSR, (msg << 4) | type); + out32(G_CME_LCL_ICSR, (msg << 4) | type); PK_TRACE_DBG("imt send | msg=%08x", ((msg << 4) | type)); // Block on ack from companion CME - while(!(in32(CME_LCL_EISR) & BIT32(30))) {} + while(!(in32(G_CME_LCL_EISR) & BIT32(30))) {} - out32(CME_LCL_EISR_CLR, BIT32(30)); + out32(G_CME_LCL_EISR_CLR, BIT32(30)); } void intercme_msg_recv(uint32_t* msg, INTERCME_MSG_TYPE type) { // Poll for inter-cme communication from QM - while(!(in32(CME_LCL_EISR) & BIT32(29))) {} + while(!(in32(G_CME_LCL_EISR) & BIT32(29))) {} - *msg = in32(CME_LCL_ICRR); + *msg = in32(G_CME_LCL_ICRR); PK_TRACE_DBG("imt recv | msg=%08x", *msg); if(*msg & type) @@ -305,10 +305,10 @@ void intercme_msg_recv(uint32_t* msg, INTERCME_MSG_TYPE type) } // Ack back to companion CME that msg was received - out32(CME_LCL_ICCR_OR, BIT32(0)); + out32(G_CME_LCL_ICCR_OR, BIT32(0)); // Clear the ack - out32(CME_LCL_ICCR_CLR, BIT32(0)); - out32(CME_LCL_EISR_CLR, BIT32(29)); + out32(G_CME_LCL_ICCR_CLR, BIT32(0)); + out32(G_CME_LCL_EISR_CLR, BIT32(29)); } void intercme_direct(INTERCME_DIRECT_INTF intf, INTERCME_DIRECT_TYPE type, uint32_t retry_enable) @@ -320,8 +320,8 @@ void intercme_direct(INTERCME_DIRECT_INTF intf, INTERCME_DIRECT_TYPE type, uint3 orig_intf = intf; // Send intercme interrupt, this is the same whether notifying or acking - out32(CME_LCL_ICCR_OR , BIT32(intf)); - out32(CME_LCL_ICCR_CLR, BIT32(intf)); + out32(G_CME_LCL_ICCR_OR , BIT32(intf)); + out32(G_CME_LCL_ICCR_CLR, BIT32(intf)); // Adjust the EI*R base address based on which intercme direct interface // is used since the bits are spread across both words in the EI*R registers @@ -351,11 +351,11 @@ void intercme_direct(INTERCME_DIRECT_INTF intf, INTERCME_DIRECT_TYPE type, uint3 if (retry_enable && ((poll_count & 0x1FF) == 0x1FF)) { // Send intercme interrupt, this is the same whether notifying or acking - out32(CME_LCL_ICCR_OR , BIT32(orig_intf)); - out32(CME_LCL_ICCR_CLR, BIT32(orig_intf)); + out32(G_CME_LCL_ICCR_OR , BIT32(orig_intf)); + out32(G_CME_LCL_ICCR_CLR, BIT32(orig_intf)); } - if(in32((CME_LCL_EISR + addr_offset)) & BIT32(intf)) + if(in32((G_CME_LCL_EISR + addr_offset)) & BIT32(intf)) { intercme_acked = 1; } @@ -364,7 +364,7 @@ void intercme_direct(INTERCME_DIRECT_INTF intf, INTERCME_DIRECT_TYPE type, uint3 } } - out32((CME_LCL_EISR_CLR + addr_offset), BIT32(intf)); // Clear the interrupt + out32((G_CME_LCL_EISR_CLR + addr_offset), BIT32(intf)); // Clear the interrupt } #ifdef USE_CME_RESCLK_FEATURE @@ -387,7 +387,7 @@ void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable) { #ifdef USE_CME_RESCLK_FEATURE - if(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_RCLK_OPERABLE)) + if(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_RCLK_OPERABLE)) { uint32_t pstate; uint32_t curr_idx; @@ -439,7 +439,7 @@ void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable) #ifdef USE_CME_VDM_FEATURE - if(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE)) + if(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE)) { if(enable) { @@ -872,7 +872,7 @@ void p9_cme_resclk_update(ANALOG_TARGET target, uint32_t next_idx, uint32_t curr void p9_cme_pstate_pmsr_updt() { uint64_t pmsrData; - uint32_t cme_flags = in32(CME_LCL_FLAGS); + uint32_t cme_flags = in32(G_CME_LCL_FLAGS); //Note: PMSR[58/UPDATE_IN_PROGRESS] is always cleared here pmsrData = ((uint64_t)G_cme_pstate_record.globalPstate) << 56; @@ -883,7 +883,7 @@ void p9_cme_pstate_pmsr_updt() //LMCR[0] = 1 means PMCR SCOM update are enabled ie. //PMCR SPR does not control Pstates. We reflect that in //PMSR[32/PMCR_DISABLED] - if ((in32(CME_LCL_LMCR) & BIT32(0))) + if ((in32(G_CME_LCL_LMCR) & BIT32(0))) { pmsrData |= BIT64(32); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c index 01d0aade..15890fed 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c @@ -85,7 +85,7 @@ p9_cme_pgpe_hb_loss_handler(void* arg, PkIrqId irq) PK_TRACE_ERR("HB LOSS OCCURED"); //Clear Interrupt - out32(CME_LCL_EISR_CLR, BIT32(4)); + out32(G_CME_LCL_EISR_CLR, BIT32(4)); //Quad Manager if(G_cme_pstate_record.qmFlag) @@ -97,11 +97,11 @@ p9_cme_pgpe_hb_loss_handler(void* arg, PkIrqId irq) #ifdef USE_CME_RESCLK_FEATURE - if (in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_RCLK_OPERABLE)) + if (in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_RCLK_OPERABLE)) { p9_cme_resclk_update(ANALOG_COMMON, p9_cme_resclk_get_index(ANALOG_PSTATE_RESCLK_OFF), G_cme_pstate_record.resclkData.common_resclk_idx); - out32(CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_RCLK_OPERABLE)); + out32(G_CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_RCLK_OPERABLE)); } #endif @@ -110,8 +110,8 @@ p9_cme_pgpe_hb_loss_handler(void* arg, PkIrqId irq) ippm_read(QPPM_QPMMR, &scom_data.value); uint32_t FSafe = (scom_data.words.upper >> 20) & 0x7FF; - out32(CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_PSTATES_ENABLED)); - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_SAFE_MODE) | + out32(G_CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_PSTATES_ENABLED)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_SAFE_MODE) | BIT32(CME_FLAGS_PGPE_HB_LOSS_SAFE_MODE)); if(FSafe) @@ -137,8 +137,8 @@ p9_cme_pgpe_hb_loss_handler(void* arg, PkIrqId irq) PK_TRACE_INF("RCVed Notify and ACKed"); - out32(CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_PSTATES_ENABLED)); - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_SAFE_MODE) | + out32(G_CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_PSTATES_ENABLED)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_SAFE_MODE) | BIT32(CME_FLAGS_PGPE_HB_LOSS_SAFE_MODE)); //Wait to receive a notify from Quad Manager @@ -159,12 +159,10 @@ p9_cme_pgpe_hb_loss_handler(void* arg, PkIrqId irq) void p9_cme_pstate_db0_handler(void) { //Mask EIMR[PGPE_HB_LOSS/4]; -// out32(CME_LCL_EIMR_OR, BIT32(4)); g_eimr_override |= BIT64(4); p9_cme_pstate_process_db0(); -// out32(CME_LCL_EIMR_CLR, BIT32(4)); g_eimr_override &= ~BIT64(4); } @@ -179,7 +177,7 @@ void p9_cme_pstate_db3_handler(void) uint32_t cm; //Clear EISR and read DB3 register - out32(CME_LCL_EISR_CLR, BITS32(10, 2)); + out32(G_CME_LCL_EISR_CLR, BITS32(10, 2)); CME_GETSCOM(CPPM_CMEDB3, G_cme_pstate_record.firstGoodCoreMask, db3.value); PK_TRACE_INF("DB3 Handler DB3=0x%08x%08x", db3.value >> 32, db3.value); @@ -213,7 +211,7 @@ void p9_cme_pstate_db3_handler(void) if (db3.fields.cme_message_numbern == MSGID_DB3_ENTER_SAFE_MODE) { - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_SAFE_MODE)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_SAFE_MODE)); } G_cme_pstate_record.skipSiblingLock = 0; @@ -225,7 +223,7 @@ void p9_cme_pstate_db3_handler(void) for(cm = 2; cm > 0; cm--) { - if (in32(CME_LCL_FLAGS) & cm) + if (in32(G_CME_LCL_FLAGS) & cm) { CME_GETSCOM(PPM_SSHSRC, cm, sshsrc); @@ -235,7 +233,7 @@ void p9_cme_pstate_db3_handler(void) (sshsrc.fields.act_stop_level == 5 && sshsrc.fields.stop_transition != 0x2))) { CME_PUTSCOM(CPPM_CPMMR_CLR, cm, BIT64(13)); - out32(CME_LCL_EIMR_CLR, cm << SHIFT32(13)); + out32(G_CME_LCL_EIMR_CLR, cm << SHIFT32(13)); } } } @@ -340,7 +338,7 @@ void p9_cme_pstate_init() //Read CME_LCL_FLAGS - uint32_t cme_flags = in32(CME_LCL_FLAGS); + uint32_t cme_flags = in32(G_CME_LCL_FLAGS); G_cme_pstate_record.qmFlag = cme_flags & BIT32(CME_FLAGS_QMGR_MASTER); G_cme_pstate_record.siblingCMEFlag = cme_flags & BIT32(CME_FLAGS_SIBLING_FUNCTIONAL); @@ -358,7 +356,7 @@ void p9_cme_pstate_init() //Disable PGPE heart beat loss g_eimr_override |= BIT64(4); - out32(CME_LCL_EIMR_OR, BIT32(4)); + out32(G_CME_LCL_EIMR_OR, BIT32(4)); //Enable Interrupts depending on whether this CME is //a quadManager or siblingCME. DB0 is enabled only @@ -442,8 +440,8 @@ void p9_cme_pstate_init() // Synchronize initial pstate w/ sibling CME if(G_cme_pstate_record.siblingCMEFlag) { - out32(CME_LCL_EITR_OR, BIT32(30)); - out32(CME_LCL_EIPR_OR, BIT32(30)); + out32(G_CME_LCL_EITR_OR, BIT32(30)); + out32(G_CME_LCL_EIPR_OR, BIT32(30)); intercme_msg_send(G_cme_pstate_record.quadPstate, IMT_INIT_PSTATE); } @@ -455,8 +453,8 @@ void p9_cme_pstate_init() // Sibling set-up for intercme messaging, after this respond to the QMs // notify to tell him the Sib is ready to go - out32(CME_LCL_EITR_OR, BIT32(29)); - out32(CME_LCL_EIPR_OR, BIT32(29)); + out32(G_CME_LCL_EITR_OR, BIT32(29)); + out32(G_CME_LCL_EIPR_OR, BIT32(29)); // Wait for QM to send an initial notify while(!(in32_sh(CME_LCL_EISR) & BIT64SH(38))); @@ -549,7 +547,7 @@ void p9_cme_pstate_init() } - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_RCLK_OPERABLE)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_RCLK_OPERABLE)); } #endif//USE_CME_RESCLK_FEATURE @@ -560,7 +558,7 @@ void p9_cme_pstate_init() // completed all initialization for VDMs and QM and Sib are interlocked if(G_cmeHeader->g_cme_qm_mode_flags & CME_QM_FLAG_SYS_VDM_ENABLE) { - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_VDM_OPERABLE)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_VDM_OPERABLE)); } #endif//USE_CME_VDM_FEATURE @@ -593,7 +591,7 @@ void p9_cme_pstate_process_db0() PK_PANIC(CME_PSTATE_TRAP_INJECT); } - uint32_t cme_flags = in32(CME_LCL_FLAGS); + uint32_t cme_flags = in32(G_CME_LCL_FLAGS); PK_TRACE_INF("PSTATE: DB0=0x%08x%08x", G_dbData.value >> 32, G_dbData.value); @@ -658,7 +656,7 @@ void p9_cme_pstate_process_db0() PK_TRACE_INF("PSTATE: Bad DB0=0x%x", (uint8_t)G_dbData.fields.cme_message_number0); send_ack_to_pgpe(MSGID_PCB_TYPE4_ACK_ERROR); - if(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_PM_DEBUG_HALT_ENABLE)) + if(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_PM_DEBUG_HALT_ENABLE)) { if(G_dbData.fields.cme_message_number0 < MSGID_DB0_VALID_START || G_dbData.fields.cme_message_number0 > MSGID_DB0_VALID_END) @@ -697,14 +695,6 @@ inline void p9_cme_pstate_register() if(register_enable) { - PK_TRACE_INF("PSTATE: Wait on Pstate Start"); - - //Wait until PGPE has set DB0_PROCESSING_ENABLE. This is important as - //PGPE might send DB0 to other quads as part of processing registration - //msg from this quad, but we don't want this quad to process them until - //PGPE has set DB0_PROCESSING_ENABLE - //while(!(in32(CME_LCL_SRTCH0) & BIT32(CME_SCRATCH_DB0_PROCESSING_ENABLE))); - PK_TRACE_INF("PSTATE: DB0 Processing is Enabled"); //PGPE sends MSGID_DB0_REGISTER_DONE, if Pstates aren't active anymore. @@ -731,7 +721,7 @@ inline void p9_cme_pstate_register() msgCnt++; } else if ((G_dbData.fields.cme_message_number0 == MSGID_DB0_CLIP_BROADCAST) && - ((in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_PSTATES_ENABLED)))) + ((in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_PSTATES_ENABLED)))) { p9_cme_pstate_db0_clip_bcast(); msgCnt++; @@ -818,7 +808,7 @@ void p9_cme_pstate_db0_start() { ack = MSGID_PCB_TYPE4_ACK_PSTATE_PROTO_ACK; - out32(CME_LCL_FLAGS_OR, BIT32(24));//Set Pstates Enabled + out32(G_CME_LCL_FLAGS_OR, BIT32(24));//Set Pstates Enabled //Enable PMCR Interrupts (for good cores) when this task is done g_eimr_override &= ~(uint64_t)(G_cme_record.core_enabled << SHIFT64(35)); @@ -870,12 +860,12 @@ inline void p9_cme_pstate_db0_stop() { PK_TRACE_INF("PSTATE: DB0 Stop Enter"); - out32(CME_LCL_FLAGS_CLR, BIT32(24));//Set Pstates Disabled + out32(G_CME_LCL_FLAGS_CLR, BIT32(24));//Set Pstates Disabled //Disable PGPE_HEARTBEAT_LOSS in EIMR //will be applied on return from DB0 interrupt g_eimr_override |= BIT64(4); - out32(CME_LCL_EIMR_OR, BIT32(4)); + out32(G_CME_LCL_EIMR_OR, BIT32(4)); // Disable both PMCR regs ignoring partial-goodness out32_sh(CME_LCL_EIMR_OR, BITS64SH(34, 2)); @@ -903,7 +893,7 @@ void p9_cme_pstate_db0_clip_bcast() uint32_t dbBit8_15 = (G_dbData.value & BITS64(8, 8)) >> SHIFT64(15); - uint32_t dbQuadValue = (G_dbData.value >> (in32(CME_LCL_SRTCH0) & + uint32_t dbQuadValue = (G_dbData.value >> (in32(G_CME_LCL_SRTCH0) & (BITS32(CME_SCRATCH_LOCAL_PSTATE_IDX_START, CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH)))) & 0xFF; @@ -942,11 +932,11 @@ inline void p9_cme_pstate_db0_pmsr_updt() switch(dbBit8_15) { case DB0_PMSR_UPDT_SET_PSTATES_SUSPENDED: - out32(CME_LCL_FLAGS_OR, BIT32(17)); + out32(G_CME_LCL_FLAGS_OR, BIT32(17)); break; case DB0_PMSR_UPDT_CLEAR_PSTATES_SUSPENDED: - out32(CME_LCL_FLAGS_CLR, BIT32(17)); + out32(G_CME_LCL_FLAGS_CLR, BIT32(17)); break; } @@ -1014,7 +1004,7 @@ inline void p9_cme_pstate_update_analog() do { - uint32_t cme_flags = in32(CME_LCL_FLAGS); + uint32_t cme_flags = in32(G_CME_LCL_FLAGS); #ifdef USE_CME_VDM_FEATURE @@ -1092,7 +1082,7 @@ void p9_cme_pstate_update() PK_TRACE_INF("PSTATE: Pstate Updt Enter"); - G_cme_pstate_record.nextPstate = (G_dbData.value >> (in32(CME_LCL_SRTCH0) & + G_cme_pstate_record.nextPstate = (G_dbData.value >> (in32(G_CME_LCL_SRTCH0) & (BITS32(CME_SCRATCH_LOCAL_PSTATE_IDX_START, CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH)))) & 0xFF; @@ -1127,7 +1117,7 @@ void p9_cme_pstate_update() } else { - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PSTATES_SUSPENDED)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PSTATES_SUSPENDED)); } pk_critical_section_exit(&ctx); diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c index 4c3a2ac7..f47658f1 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c @@ -111,13 +111,12 @@ void p9_cme_init_done() { intercme_msg_recv(&msg, IMT_SYNC_SIBLING); // Unmask the COMM_RECVD interrupt for the intercme msg handler - out32(CME_LCL_EIMR_CLR, BIT32(29)); + out32(G_CME_LCL_EIMR_CLR, BIT32(29)); } // This is the current barrier for SGPE booting the CMEs, any and all // initialization must be completed prior! -// @todo RTC173279 rename this flag to CME_FLAGS_BOOT_DONE - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PMCR_READY)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PMCR_READY)); PK_TRACE_INF("CME INIT DONE: Exit"); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c index 86168718..8daf99db 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c @@ -75,7 +75,7 @@ void bce_irr_setup() { BceReturnCode_t l_rc; uint32_t l_cmePir = 0; - uint32_t l_exId = (in32(CME_LCL_FLAGS) & BIT32(26)) >> SHIFT32(26); + uint32_t l_exId = (in32(G_CME_LCL_FLAGS) & BIT32(26)) >> SHIFT32(26); asm volatile ( "mfspr %0, %1 \n\t" : "=r" (l_cmePir) : "i" (SPR_NUM_PIR)); //CME's PIR gives only quad id. To determine the correct CME instance, follow the steps below: @@ -240,7 +240,7 @@ void bce_irr_thread() void start_cme_block_copy(uint32_t barIndex, uint32_t bcMembase, uint32_t bcSrambase, uint32_t bcLength) { uint32_t l_cmePir = 0; - uint32_t l_exId = ((in32(CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS); + uint32_t l_exId = ((in32(G_CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS); asm volatile ( "mfspr %0, %1 \n\t" : "=r" (l_cmePir) : "i" (SPR_NUM_PIR)); @@ -268,7 +268,7 @@ BceReturnCode_t check_cme_block_copy() { BceReturnCode_t l_rc; uint32_t l_cmePir = 0; - uint32_t l_exId = ((in32(CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS); + uint32_t l_exId = ((in32(G_CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS); asm volatile ( "mfspr %0, %1 \n\t" : "=r" (l_cmePir) : "i" (SPR_NUM_PIR)); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index b6ad553b..665be9c6 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -153,7 +153,7 @@ #define PK_OPTIONAL_DEBUG_HALT(panic_code) \ - if(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_PM_DEBUG_HALT_ENABLE)) {PK_PANIC(panic_code);} + if(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_PM_DEBUG_HALT_ENABLE)) {PK_PANIC(panic_code);} #if NIMBUS_DD_LEVEL == 10 diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h index a1c2b7b7..295cccd9 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -51,16 +51,14 @@ enum CME_SE_MARKS SE_IS0_BEGIN = 0xf8, SE_IS0_END = 0x100, SE_CATCHUP = 0x108, - SE_CORE_VMIN = 0x110, - SE_STOP3_DONE = 0x118, - SE_POWER_OFF_CORE = 0x120, - SE_STOP4_DONE = 0x128, - SE_IS1_BEGIN = 0x130, - SE_IS1_END = 0x138, - SE_PURGE_L2 = 0x140, - SE_PURGE_L2_ABORT = 0x148, - SE_PURGE_L2_DONE = 0x150, - SE_SGPE_HANDOFF = 0x168 + SE_POWER_OFF_CORE = 0x110, + SE_STOP4_DONE = 0x118, + SE_IS1_BEGIN = 0x120, + SE_IS1_END = 0x128, + SE_PURGE_L2 = 0x130, + SE_PURGE_L2_ABORT = 0x138, + SE_PURGE_L2_DONE = 0x140, + SE_SGPE_HANDOFF = 0x148 }; @@ -83,8 +81,6 @@ const std::vector<CME_SE_MARKS> MARKS = SE_IS0_BEGIN, SE_IS0_END, SE_CATCHUP, - SE_CORE_VMIN, - SE_STOP3_DONE, SE_POWER_OFF_CORE, SE_STOP4_DONE, SE_IS1_BEGIN, @@ -111,8 +107,6 @@ const std::map<CME_SE_MARKS, std::string> mMARKS = boost::assign::map_list_of (SE_IS0_BEGIN, "SE_IS0_BEGIN") (SE_IS0_END, "SE_IS0_END") (SE_CATCHUP, "SE_CATCHUP") - (SE_CORE_VMIN, "SE_CORE_VMIN") - (SE_STOP3_DONE, "SE_STOP3_DONE") (SE_POWER_OFF_CORE, "SE_POWER_OFF_CORE") (SE_STOP4_DONE, "SE_STOP4_DONE") (SE_IS1_BEGIN, "SE_IS1_BEGIN") diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index 2b331fff..cb9c82d7 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -270,9 +270,9 @@ p9_cme_stop_entry() // pm_active is edge trigger because its level can be phantom // due to common-core constantly gives pm_active when core is stopped, // reading from EINR for raw signal, ignore EISR if EINR signal is gone - core = (in32(CME_LCL_EISR) & BITS32(20, 2)); - core_raw = (in32(CME_LCL_EINR) & BITS32(20, 2)); - out32(CME_LCL_EISR_CLR, core); + core = (in32(G_CME_LCL_EISR) & BITS32(20, 2)); + core_raw = (in32(G_CME_LCL_EINR) & BITS32(20, 2)); + out32(G_CME_LCL_EISR_CLR, core); core = (core & core_raw) >> SHIFT32(21); // filter with partial good and running core mask @@ -295,7 +295,7 @@ p9_cme_stop_entry() // not implemented in DD1 // bit1 is Recoverable Error // bit2 is Special Attention - if (((core & CME_MASK_C0) && (in32(CME_LCL_SISR) & BITS32(13, 2))) || + if (((core & CME_MASK_C0) && (in32(G_CME_LCL_SISR) & BITS32(13, 2))) || ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS64SH(61, 2)))) { PK_TRACE_INF("WARNING: Attn/Recov Present, Abort Entry and Return"); @@ -435,10 +435,10 @@ p9_cme_stop_entry() #endif PK_TRACE("Request PCB mux via SICR[10/11]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(11)); + out32(G_CME_LCL_SICR_OR, core << SHIFT32(11)); // Poll Infinitely for PCB Mux Grant - while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core); + while((core & (in32(G_CME_LCL_SISR) >> SHIFT32(11))) != core); PK_TRACE("PCB Mux Granted on Core[%d]", core); @@ -464,8 +464,8 @@ p9_cme_stop_entry() // Note: Only Stop1 requires pulsing entry ack to pc, // thus this is NDD1 only as well. PK_TRACE("Pulse STOP entry acknowledgement to PC via SICR[0/1]"); - out32(CME_LCL_SICR_OR, core_stop1 << SHIFT32(1)); - out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1)); + out32(G_CME_LCL_SICR_OR, core_stop1 << SHIFT32(1)); + out32(G_CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1)); if (core & CME_MASK_C0) { @@ -572,16 +572,16 @@ p9_cme_stop_entry() wrteei(0); PK_TRACE("HW407385: Assert block interrupt to PC via SICR[2/3]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(3)); + out32(G_CME_LCL_SICR_OR, core << SHIFT32(3)); PK_TRACE("HW407385: Waking up the core(pm_exit=1) via SICR[4/5]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(5)); + out32(G_CME_LCL_SICR_OR, core << SHIFT32(5)); CME_PM_EXIT_DELAY PK_TRACE("HW407385: Polling for core wakeup(pm_active=0) via EINR[20/21]"); - while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); + while((in32(G_CME_LCL_EINR)) & (core << SHIFT32(21))); wrteei(1); @@ -866,11 +866,11 @@ p9_cme_stop_entry() //============================= PK_TRACE("Assert halt STOP override disable via LMCR[14/15]"); - out32(CME_LCL_LMCR_OR, (core << SHIFT32(15))); + out32(G_CME_LCL_LMCR_OR, (core << SHIFT32(15))); #if SPWU_AUTO PK_TRACE("Assert auto special wakeup disable via LMCR[12/13]"); - out32(CME_LCL_LMCR_OR, (core << SHIFT32(13))); + out32(G_CME_LCL_LMCR_OR, (core << SHIFT32(13))); #endif @@ -880,13 +880,13 @@ p9_cme_stop_entry() #endif PK_TRACE("Assert core-L2 + core-CC quiesces via SICR[6/7,8/9]"); - out32(CME_LCL_SICR_OR, (core << SHIFT32(7)) | (core << SHIFT32(9))); + out32(G_CME_LCL_SICR_OR, (core << SHIFT32(7)) | (core << SHIFT32(9))); PK_TRACE("Poll for L2 interface quiesced via SISR[30/31]"); do { - lclr_data = in32(CME_LCL_SISR); + lclr_data = in32(G_CME_LCL_SISR); } while((lclr_data & core) != core); @@ -953,17 +953,17 @@ p9_cme_stop_entry() wrteei(0); PK_TRACE("HW407385: Drop pm_exit via SICR[4/5]"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); + out32(G_CME_LCL_SICR_CLR, core << SHIFT32(5)); PK_TRACE("HW407385: Polling for core to stop(pm_active=1) via EINR[20/21]"); - while((~(in32(CME_LCL_EINR))) & (core << SHIFT32(21))); + while((~(in32(G_CME_LCL_EINR))) & (core << SHIFT32(21))); PK_TRACE("HW407385: Clear pm_active status via EISR[20/21]"); - out32(CME_LCL_EISR_CLR, core << SHIFT32(21)); + out32(G_CME_LCL_EISR_CLR, core << SHIFT32(21)); PK_TRACE("HW407385: Drop block interrupt to PC via SICR[2/3]"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(3)); + out32(G_CME_LCL_SICR_CLR, core << SHIFT32(3)); wrteei(1); @@ -1201,13 +1201,13 @@ p9_cme_stop_entry() break; } - core_catchup = (in32(CME_LCL_EISR) & BITS32(20, 2)) >> SHIFT32(21); + core_catchup = (in32(G_CME_LCL_EISR) & BITS32(20, 2)) >> SHIFT32(21); core_catchup = core_catchup & G_cme_record.core_enabled & G_cme_stop_record.core_running; if (core_catchup) { - out32(CME_LCL_EISR_CLR, core_catchup << SHIFT32(21)); + out32(G_CME_LCL_EISR_CLR, core_catchup << SHIFT32(21)); origin_core = core; origin_level = target_level; core = core_catchup; @@ -1240,13 +1240,14 @@ p9_cme_stop_entry() //=========================== #if !SKIP_ABORT + core_wakeup = core & (~G_cme_stop_record.core_blockwu); - out32(CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) | + out32(G_CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) | (core_wakeup << SHIFT32(15)) | (core_wakeup << SHIFT32(17))); sync(); wrteei(0); - out32(CME_LCL_EIMR_OR, BITS32(10, 12)); + out32(G_CME_LCL_EIMR_OR, BITS32(10, 12)); wrteei(1); #endif @@ -1292,7 +1293,7 @@ p9_cme_stop_entry() // bit2 is Special Attention // bit3 is Core Checkstop - if ((core & CME_MASK_C0) && (in32(CME_LCL_SISR) & BITS32(12, 4))) + if ((core & CME_MASK_C0) && (in32(G_CME_LCL_SISR) & BITS32(12, 4))) { PK_TRACE_INF("WARNING: Core0 Xstop/Attn/Recov Present, Abort Entry"); core -= CME_MASK_C0; @@ -1324,7 +1325,7 @@ p9_cme_stop_entry() #if !STOP_PRIME - if(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE)) + if(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE)) { PK_TRACE_DBG("Clear Poweron bit in VDMCR"); CME_PUTSCOM(PPM_VDMCR_CLR, core, BIT64(0)); @@ -1416,14 +1417,16 @@ p9_cme_stop_entry() //=========================== #if !SKIP_ABORT + core_wakeup = core & (~G_cme_stop_record.core_blockwu); - out32(CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) | + out32(G_CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) | (core_wakeup << SHIFT32(15)) | (core_wakeup << SHIFT32(17))); sync(); wrteei(0); - out32(CME_LCL_EIMR_OR, BITS32(10, 12)); + out32(G_CME_LCL_EIMR_OR, BITS32(10, 12)); wrteei(1); + #endif //=================== @@ -1475,8 +1478,8 @@ p9_cme_stop_entry() // insert tlbie quiesce before ncu purge to avoid window condition // of ncu traffic still happening when purging starts // Note: chtm purge and drop tlbie quiesce will be done in SGPE - out32(CME_LCL_SICR_OR, BIT32(18) | BIT32(21)); - out32(CME_LCL_SICR_OR, BIT32(22)); + out32(G_CME_LCL_SICR_OR, BIT32(18) | BIT32(21)); + out32(G_CME_LCL_SICR_OR, BIT32(22)); PK_TRACE("Poll for purged done via EISR[22,23]"); @@ -1486,15 +1489,15 @@ p9_cme_stop_entry() #if !SKIP_L2_PURGE_ABORT if (!core_aborted && - (in32(CME_LCL_EINR) & BITS32(12, 6))) + (in32(G_CME_LCL_EINR) & BITS32(12, 6))) { - if (in32(CME_LCL_EINR) & + if (in32(G_CME_LCL_EINR) & (((core & CME_MASK_C0) ? BIT32(12) : 0) | BIT32(14) | BIT32(16))) { core_aborted |= CME_MASK_C0; } - if (in32(CME_LCL_EINR) & + if (in32(G_CME_LCL_EINR) & (((core & CME_MASK_C1) ? BIT32(13) : 0) | BIT32(15) | BIT32(17))) { core_aborted |= CME_MASK_C1; @@ -1507,17 +1510,17 @@ p9_cme_stop_entry() //======================================= PK_TRACE_INF("Abort: L2+NCU purge aborted by core[%d]", core_aborted); - out32(CME_LCL_SICR_OR, BIT32(19) | BIT32(23)); + out32(G_CME_LCL_SICR_OR, BIT32(19) | BIT32(23)); } } #endif } - while((in32(CME_LCL_EISR) & BITS32(22, 2)) != BITS32(22, 2)); + while((in32(G_CME_LCL_EISR) & BITS32(22, 2)) != BITS32(22, 2)); PK_TRACE("Drop L2+NCU purges and their possible aborts via SICR[18,19,22,23]"); - out32(CME_LCL_SICR_CLR, (BITS32(18, 2) | BITS32(22, 2))); + out32(G_CME_LCL_SICR_CLR, (BITS32(18, 2) | BITS32(22, 2))); PK_TRACE_DBG("SE.5A: L2 and NCU Purged"); @@ -1630,7 +1633,7 @@ p9_cme_stop_entry() sync(); PK_TRACE("Clear special/regular wakeup after wakeup_notify = 1 since it is edge triggered"); - out32(CME_LCL_EISR_CLR, (core << SHIFT32(15)) | (core << SHIFT32(17))); + out32(G_CME_LCL_EISR_CLR, (core << SHIFT32(15)) | (core << SHIFT32(17))); PK_TRACE_INF("SE.5B: Core[%d] Handed off to SGPE", core); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index f3aef781..e517f36a 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -227,13 +227,13 @@ p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop) (act_stop_level << SHIFT64SH(44)) | (act_stop_level << SHIFT64SH(52)) | (act_stop_level << SHIFT64SH(60)) | - (((in32(CME_LCL_PSCRS00) & BIT32(2)) ? + (((in32(G_CME_LCL_PSCRS00) & BIT32(2)) ? SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(39)) | - (((in32(CME_LCL_PSCRS10) & BIT32(2)) ? + (((in32(G_CME_LCL_PSCRS10) & BIT32(2)) ? SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(47)) | - (((in32(CME_LCL_PSCRS20) & BIT32(2)) ? + (((in32(G_CME_LCL_PSCRS20) & BIT32(2)) ? SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(55)) | - (((in32(CME_LCL_PSCRS30) & BIT32(2)) ? + (((in32(G_CME_LCL_PSCRS30) & BIT32(2)) ? SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS))); } @@ -264,13 +264,13 @@ p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop) sync(); PK_TRACE_PERF("Core Waking up(pm_exit=1) via SICR[4/5]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(5)); + out32(G_CME_LCL_SICR_OR, core << SHIFT32(5)); CME_PM_EXIT_DELAY PK_TRACE_PERF("Polling for Core Waking up(pm_active=0) via EINR[20/21]"); - while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); + while((in32(G_CME_LCL_EINR)) & (core << SHIFT32(21))); #if defined(USE_CME_QUEUED_SCOM) @@ -280,9 +280,9 @@ p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop) #endif PK_TRACE_PERF("Release PCB Mux back on Core via SICR[10/11]"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(11)); + out32(G_CME_LCL_SICR_CLR, core << SHIFT32(11)); - while((core & ~(in32(CME_LCL_SISR) >> SHIFT32(11))) != core); + while((core & ~(in32(G_CME_LCL_SISR) >> SHIFT32(11))) != core); PK_TRACE_INF("SX.0A: PCB Mux Released on Core[%d]", core); @@ -305,21 +305,21 @@ p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop) G_cme_stop_record.core_blockpc &= ~core; PK_TRACE_DBG("Drop halt STOP override disable via LMCR[14/15]"); - out32(CME_LCL_LMCR_CLR, (core << SHIFT32(15))); + out32(G_CME_LCL_LMCR_CLR, (core << SHIFT32(15))); #if SPWU_AUTO PK_TRACE_DBG("Drop auto spwu disable, enable auto spwu via LMCR[12/13]"); - out32(CME_LCL_LMCR_CLR, core << SHIFT32(13)); + out32(G_CME_LCL_LMCR_CLR, core << SHIFT32(13)); PK_TRACE_PERF("SX.0B: Core Drop PM_EXIT via SICR[4/5]"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); + out32(G_CME_LCL_SICR_CLR, core << SHIFT32(5)); #else if ((spwu_stop = (core & spwu_stop))) { - if (in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_SPWU_CHECK_ENABLE)) + if (in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_SPWU_CHECK_ENABLE)) { CME_GETSCOM_OR(PPM_SSHSRC, spwu_stop, scom_data.value); @@ -337,9 +337,9 @@ p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop) PK_TRACE_DBG("SX.0B: Core[%d] Assert SPWU_DONE via SICR[16/17]", spwu_stop); // Note: clear pm_active so that potential stop1 wont use leftover pm_active upon drop spwu later - out32(CME_LCL_EISR_CLR, ((spwu_stop << SHIFT32(15)) | (spwu_stop << SHIFT32(21)))); // clear spwu in EISR - out32(CME_LCL_EIPR_CLR, spwu_stop << SHIFT32(15)); // flip EIPR to falling edge - out32(CME_LCL_SICR_OR, spwu_stop << SHIFT32(17)); // assert spwu_done now + out32(G_CME_LCL_EISR_CLR, ((spwu_stop << SHIFT32(15)) | (spwu_stop << SHIFT32(21)))); // clear spwu in EISR + out32(G_CME_LCL_EIPR_CLR, spwu_stop << SHIFT32(15)); // flip EIPR to falling edge + out32(G_CME_LCL_SICR_OR, spwu_stop << SHIFT32(17)); // assert spwu_done now G_cme_stop_record.core_in_spwu |= spwu_stop; #if !DISABLE_PERIODIC_CORE_QUIESCE && (NIMBUS_DD_LEVEL == 20 || NIMBUS_DD_LEVEL == 21 || CUMULUS_DD_LEVEL == 10) @@ -353,7 +353,7 @@ p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop) if ((core = (core & (~spwu_stop)))) { PK_TRACE_PERF("SX.0C: Core isnt SPWUed, Drop PM_EXIT via SICR[4/5]"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); + out32(G_CME_LCL_SICR_CLR, core << SHIFT32(5)); } #endif @@ -392,10 +392,10 @@ p9_cme_stop_exit_lv2(uint32_t core) #endif PK_TRACE("SX.20: Request PCB mux via SICR[10/11]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(11)); + out32(G_CME_LCL_SICR_OR, core << SHIFT32(11)); // Poll Infinitely for PCB Mux Grant - while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core); + while((core & (in32(G_CME_LCL_SISR) >> SHIFT32(11))) != core); PK_TRACE("SX.20: PCB Mux Granted on Core[%d]", core); @@ -441,7 +441,7 @@ p9_cme_stop_exit_catchup(uint32_t* core, uint32_t wakeup = 0; data64_t scom_data = {0}; - wakeup = (in32(CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; + wakeup = (in32(G_CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; core_catchup = (~(*core)) & ((wakeup >> 4) | wakeup) & CME_MASK_BC; // ignore wakeup being blocked, do not clear @@ -462,7 +462,7 @@ p9_cme_stop_exit_catchup(uint32_t* core, } // leave spwu alone, clear pcwu/rgwu only if not stop5+ or blocked - out32(CME_LCL_EISR_CLR, ((core_catchup << SHIFT32(13)) | (core_catchup << SHIFT32(17)))); + out32(G_CME_LCL_EISR_CLR, ((core_catchup << SHIFT32(13)) | (core_catchup << SHIFT32(17)))); // override with partial good core mask, also ignore wakeup to running cores // these are being cleared and considered done for running or disabled cores @@ -472,7 +472,7 @@ p9_cme_stop_exit_catchup(uint32_t* core, if (core_catchup) { // chtm purge done - out32(CME_LCL_EISR_CLR, (core_catchup << SHIFT32(25))); + out32(G_CME_LCL_EISR_CLR, (core_catchup << SHIFT32(25))); scom_data.words.lower = 0; scom_data.words.upper = SSH_EXIT_IN_SESSION; @@ -538,7 +538,7 @@ p9_cme_stop_exit() //-------------------------------------------------------------------------- // extract wakeup signals and clear status - wakeup = (in32(CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; + wakeup = (in32(G_CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; core = ((wakeup >> 4) | (wakeup >> 2) | wakeup) & CME_MASK_BC; // ignore wakeup being blocked, do not clear @@ -559,7 +559,7 @@ p9_cme_stop_exit() } // leave spwu alone, clear pcwu/rgwu only if not stop5+ or blocked - out32(CME_LCL_EISR_CLR, ((core << SHIFT32(13)) | (core << SHIFT32(17)))); + out32(G_CME_LCL_EISR_CLR, ((core << SHIFT32(13)) | (core << SHIFT32(17)))); PK_TRACE_INF("SX.00: Core Wakeup[%x] Raw Interrupts[%x] Actual Stop Levels[%d %d]", core, wakeup, @@ -585,7 +585,7 @@ p9_cme_stop_exit() if (spwu_wake) { - if (in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_SPWU_CHECK_ENABLE)) + if (in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_SPWU_CHECK_ENABLE)) { CME_GETSCOM_OR(PPM_SSHSRC, spwu_wake, scom_data.value); @@ -600,10 +600,10 @@ p9_cme_stop_exit() // Process special wakeup on a core that is already running PK_TRACE_DBG("SP.WU: Core[%d] Assert PM_EXIT and SPWU_DONE via SICR[4/5, 16/17]", spwu_wake); // Note: clear pm_active so that potential stop1 wont use leftover pm_active upon drop spwu later - out32(CME_LCL_SICR_OR, spwu_wake << SHIFT32(5)); // assert pm_exit - out32(CME_LCL_EISR_CLR, ((spwu_wake << SHIFT32(15)) | (spwu_wake << SHIFT32(21)))); // clear spwu in EISR - out32(CME_LCL_EIPR_CLR, spwu_wake << SHIFT32(15)); // flip EIPR to falling edge - out32(CME_LCL_SICR_OR, spwu_wake << SHIFT32(17)); // assert spwu_done now + out32(G_CME_LCL_SICR_OR, spwu_wake << SHIFT32(5)); // assert pm_exit + out32(G_CME_LCL_EISR_CLR, ((spwu_wake << SHIFT32(15)) | (spwu_wake << SHIFT32(21)))); // clear spwu in EISR + out32(G_CME_LCL_EIPR_CLR, spwu_wake << SHIFT32(15)); // flip EIPR to falling edge + out32(G_CME_LCL_SICR_OR, spwu_wake << SHIFT32(17)); // assert spwu_done now G_cme_stop_record.core_in_spwu |= spwu_wake; #if !DISABLE_PERIODIC_CORE_QUIESCE && (NIMBUS_DD_LEVEL == 20 || NIMBUS_DD_LEVEL == 21 || CUMULUS_DD_LEVEL == 10) @@ -719,7 +719,7 @@ p9_cme_stop_exit() core, target_level, deeper_level, deeper_core); PK_TRACE("Clear chtm purge done via EISR[24/25]"); - out32(CME_LCL_EISR_CLR, (core << SHIFT32(25))); + out32(G_CME_LCL_EISR_CLR, (core << SHIFT32(25))); PK_TRACE("Update STOP history: in transition of exit"); scom_data.words.lower = 0; @@ -821,16 +821,16 @@ p9_cme_stop_exit() #endif PK_TRACE("SX.40: Request PCB mux via SICR[10/11]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(11)); + out32(G_CME_LCL_SICR_OR, core << SHIFT32(11)); // Poll Infinitely for PCB Mux Grant - while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core); + while((core & (in32(G_CME_LCL_SISR) >> SHIFT32(11))) != core); PK_TRACE_PERF("SX.40: PCB Mux Granted on Core"); // Note: in this case, no need to call p9_cme_pcbmux_savior_epilogue - if(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE)) + if(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE)) { // Poweron the VDM giving it time to powerup prior to enabling PK_TRACE_DBG("Set Poweron bit in VDMCR"); @@ -1064,16 +1064,16 @@ p9_cme_stop_exit() #if !SKIP_SELF_RESTORE PK_TRACE("Assert block interrupt to PC via SICR[2/3]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(3)); + out32(G_CME_LCL_SICR_OR, core << SHIFT32(3)); PK_TRACE_PERF("SF.RS: Self Restore Prepare, Core Waking up(pm_exit=1) via SICR[4/5]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(5)); + out32(G_CME_LCL_SICR_OR, core << SHIFT32(5)); CME_PM_EXIT_DELAY PK_TRACE("Polling for core wakeup(pm_active=0) via EINR[20/21]"); - while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); + while((in32(G_CME_LCL_EINR)) & (core << SHIFT32(21))); scom_data.value = pCmeImgHdr->g_cme_cpmr_PhyAddr & BITS64(13, 30); //HRMOR[13:42] @@ -1211,11 +1211,11 @@ p9_cme_stop_exit() //========================== PK_TRACE("Allow threads to run(pm_exit=0)"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); + out32(G_CME_LCL_SICR_CLR, core << SHIFT32(5)); PK_TRACE("Poll for core stop again(pm_active=1)"); - while((~(in32(CME_LCL_EINR))) & (core << SHIFT32(21))) + while((~(in32(G_CME_LCL_EINR))) & (core << SHIFT32(21))) { core_spattn = (in32_sh(CME_LCL_SISR) >> SHIFT64SH(33)) & CME_MASK_BC; @@ -1256,10 +1256,10 @@ p9_cme_stop_exit() CME_PUTSCOM(IMA_EVENT_MASK, core, scom_data.value & ~BIT64(34)); PK_TRACE("Drop block interrupt to PC via SICR[2/3]"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(3)); + out32(G_CME_LCL_SICR_CLR, core << SHIFT32(3)); PK_TRACE("Clear pm_active status via EISR[20/21]"); - out32(CME_LCL_EISR_CLR, core << SHIFT32(21)); + out32(G_CME_LCL_EISR_CLR, core << SHIFT32(21)); #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit_marks.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit_marks.h index d072a944..a0a53e36 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit_marks.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit_marks.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,6 @@ enum CME_SX_MARKS { BEGINSCOPE_STOP_EXIT = 0x8, ENDSCOPE_STOP_EXIT = 0x10, - SX_STOP3 = 0x68, SX_POWERON = 0xe0, SX_CHIPLET_RESET = 0xe8, SX_CHIPLET_RESET_SCAN0 = 0xf0, @@ -47,16 +46,16 @@ enum CME_SX_MARKS SX_CATCHUP_B = 0x108, SX_ARRAY_INIT = 0x110, SX_FUNC_INIT = 0x118, - SX_STARTCLOCKS = 0x120, - SX_STARTCLOCKS_ALIGN = 0x128, - SX_STARTCLOCKS_REGION = 0x130, - SX_STARTCLOCKS_DONE = 0x138, - SX_SCOM_INITS = 0x140, - SX_BCE_CHECK = 0x148, - SX_RUNTIME_INITS = 0x150, - SX_SELF_RESTORE = 0x168, - SX_SRESET_THREADS = 0x1e0, - SX_ENABLE_ANALOG = 0x1e8 + SX_ENABLE_ANALOG = 0x120, + SX_STARTCLOCKS = 0x128, + SX_STARTCLOCKS_ALIGN = 0x130, + SX_STARTCLOCKS_REGION = 0x138, + SX_STARTCLOCKS_DONE = 0x140, + SX_SCOM_INITS = 0x148, + SX_BCE_CHECK = 0x150, + SX_RUNTIME_INITS = 0x168, + SX_SELF_RESTORE = 0x1e0, + SX_SRESET_THREADS = 0x1e8 }; @@ -66,7 +65,6 @@ const std::vector<CME_SX_MARKS> MARKS = { BEGINSCOPE_STOP_EXIT, ENDSCOPE_STOP_EXIT, - SX_STOP3, SX_POWERON, SX_CHIPLET_RESET, SX_CHIPLET_RESET_SCAN0, @@ -75,6 +73,7 @@ const std::vector<CME_SX_MARKS> MARKS = SX_CATCHUP_B, SX_ARRAY_INIT, SX_FUNC_INIT, + SX_ENABLE_ANALOG, SX_STARTCLOCKS, SX_STARTCLOCKS_ALIGN, SX_STARTCLOCKS_REGION, @@ -83,14 +82,12 @@ const std::vector<CME_SX_MARKS> MARKS = SX_BCE_CHECK, SX_RUNTIME_INITS, SX_SELF_RESTORE, - SX_SRESET_THREADS, - SX_ENABLE_ANALOG + SX_SRESET_THREADS }; const std::map<CME_SX_MARKS, std::string> mMARKS = boost::assign::map_list_of (BEGINSCOPE_STOP_EXIT, "BEGINSCOPE_STOP_EXIT") (ENDSCOPE_STOP_EXIT, "ENDSCOPE_STOP_EXIT") - (SX_STOP3, "SX_STOP3") (SX_POWERON, "SX_POWERON") (SX_CHIPLET_RESET, "SX_CHIPLET_RESET") (SX_CHIPLET_RESET_SCAN0, "SX_CHIPLET_RESET_SCAN0") @@ -99,6 +96,7 @@ const std::map<CME_SX_MARKS, std::string> mMARKS = boost::assign::map_list_of (SX_CATCHUP_B, "SX_CATCHUP_B") (SX_ARRAY_INIT, "SX_ARRAY_INIT") (SX_FUNC_INIT, "SX_FUNC_INIT") + (SX_ENABLE_ANALOG, "SX_ENABLE_ANALOG") (SX_STARTCLOCKS, "SX_STARTCLOCKS") (SX_STARTCLOCKS_ALIGN, "SX_STARTCLOCKS_ALIGN") (SX_STARTCLOCKS_REGION, "SX_STARTCLOCKS_REGION") @@ -107,9 +105,7 @@ const std::map<CME_SX_MARKS, std::string> mMARKS = boost::assign::map_list_of (SX_BCE_CHECK, "SX_BCE_CHECK") (SX_RUNTIME_INITS, "SX_RUNTIME_INITS") (SX_SELF_RESTORE, "SX_SELF_RESTORE") - (SX_SRESET_THREADS, "SX_SRESET_THREADS") - (SX_ENABLE_ANALOG, "SX_ENABLE_ANALOG"); - + (SX_SRESET_THREADS, "SX_SRESET_THREADS"); } #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c index cb42cf86..71fdeee6 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c @@ -56,7 +56,7 @@ p9_cme_stop_init() // partial_good and entry_first: unmask entry // partial_good and !entry_first: unmask exit // !partial_good: dont unmask - cme_flags = (in32(CME_LCL_FLAGS) & 0xF); + cme_flags = (in32(G_CME_LCL_FLAGS) & 0xF); entry_first = ( (cme_flags >> 2) & cme_flags & CME_MASK_BC); exit_first = (~(cme_flags >> 2) & cme_flags & CME_MASK_BC); @@ -64,21 +64,21 @@ p9_cme_stop_init() G_cme_stop_record.core_stopgpe = 0; // use SISR[2:3] PM_BLOCK_INTERRUPTS to init block wakeup status - G_cme_stop_record.core_blockpc = ((in32(CME_LCL_SISR) & BITS32(2, 2)) >> SHIFT32(3)); + G_cme_stop_record.core_blockpc = ((in32(G_CME_LCL_SISR) & BITS32(2, 2)) >> SHIFT32(3)); G_cme_stop_record.core_blockwu = G_cme_stop_record.core_blockpc; G_cme_stop_record.core_blockey = 0; G_cme_stop_record.core_suspendwu = G_cme_stop_record.core_blockpc; G_cme_stop_record.core_suspendey = 0; G_cme_stop_record.core_vdm_droop = 0; - if (in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_BLOCK_ENTRY_STOP11)) + if (in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_BLOCK_ENTRY_STOP11)) { G_cme_stop_record.core_blockey = CME_MASK_BC; G_cme_stop_record.core_suspendey = CME_MASK_BC; } // use SISR[16:17] SPECIAL_WKUP_DONE to init special wakeup status - G_cme_stop_record.core_in_spwu = ((in32(CME_LCL_SISR) & BITS32(16, 2)) >> SHIFT32(17)); + G_cme_stop_record.core_in_spwu = ((in32(G_CME_LCL_SISR) & BITS32(16, 2)) >> SHIFT32(17)); PK_TRACE_DBG("Setup: cme_flags[%x] entry_first[%x] exit_first[%x]", cme_flags, entry_first, exit_first); @@ -137,24 +137,24 @@ p9_cme_stop_init() #if HW386841_NDD1_DSL_STOP1_FIX PK_TRACE("Disable the Auto-STOP1 function for Nimbus DD1 via LMCR[18,19]"); - out32(CME_LCL_LMCR_OR, BITS32(18, 2)); + out32(G_CME_LCL_LMCR_OR, BITS32(18, 2)); #endif PK_TRACE("Drop STOP override mode and active mask via LMCR[16,17]"); - out32(CME_LCL_LMCR_CLR, BITS32(16, 2)); + out32(G_CME_LCL_LMCR_CLR, BITS32(16, 2)); PK_TRACE_DBG("Setup: SPWU Interrupt Polority[%d]", G_cme_stop_record.core_in_spwu); - out32(CME_LCL_EIPR_CLR, (G_cme_stop_record.core_in_spwu << SHIFT32(15))); - out32(CME_LCL_EIPR_OR, (((~G_cme_stop_record.core_in_spwu) & CME_MASK_BC) << SHIFT32(15))); + out32(G_CME_LCL_EIPR_CLR, (G_cme_stop_record.core_in_spwu << SHIFT32(15))); + out32(G_CME_LCL_EIPR_OR, (((~G_cme_stop_record.core_in_spwu) & CME_MASK_BC) << SHIFT32(15))); PK_TRACE("Assert auto spwu disable, disable auto spwu via LMCR[12/13]"); - out32(CME_LCL_LMCR_OR, BITS32(12, 2)); + out32(G_CME_LCL_LMCR_OR, BITS32(12, 2)); PK_TRACE_DBG("Setup: Umask STOP Interrupts Now Based on Entry_First Flag"); // unmask db1 for block stop protocol out32_sh(CME_LCL_EIMR_CLR, (CME_MASK_BC << SHIFT64SH(41))); - out32(CME_LCL_EIMR_CLR, + out32(G_CME_LCL_EIMR_CLR, ((CME_MASK_BC << SHIFT32(19)) | // DB2 (entry_first << SHIFT32(21)) | // PM_ACTIVE (exit_first << SHIFT32(13)) | // PC_INTR_PENDING @@ -170,7 +170,7 @@ p9_cme_stop_init() //-------------------------------------------------------------------------- PK_TRACE_INF("Setup: CME STOP READY"); - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_STOP_READY)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_STOP_READY)); #if EPM_P9_TUNING asm volatile ("tw 0, 31, 0"); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index 09ba46b9..878a0182 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -44,7 +44,7 @@ void p9_cme_stop_pcwu_handler(void) { uint32_t core_mask = 0; - uint32_t core = (in32(CME_LCL_EISR) & BITS32(12, 2)) >> SHIFT32(13); + uint32_t core = (in32(G_CME_LCL_EISR) & BITS32(12, 2)) >> SHIFT32(13); data64_t scom_data = {0}; ppm_pig_t pig = {0}; @@ -54,7 +54,7 @@ p9_cme_stop_pcwu_handler(void) // consider wakeup is done on a running core // also ignore the decrementor request that already sent to sgpe core &= ~(G_cme_stop_record.core_running | G_cme_stop_record.core_blockpc); - out32(CME_LCL_EISR_CLR, (G_cme_stop_record.core_running << SHIFT32(13))); + out32(G_CME_LCL_EISR_CLR, (G_cme_stop_record.core_running << SHIFT32(13))); for (core_mask = 2; core_mask; core_mask--) { @@ -85,7 +85,7 @@ p9_cme_stop_pcwu_handler(void) { PK_TRACE_INF("PCWU Launching exit thread"); - out32(CME_LCL_EIMR_OR, BITS32(12, 10)); + out32(G_CME_LCL_EIMR_OR, BITS32(12, 10)); g_eimr_override |= BITS64(12, 10); G_cme_stop_record.exit_ongoing = 1; wrteei(1); @@ -119,7 +119,7 @@ p9_cme_stop_spwu_handler(void) int spwu_rise = 0; uint32_t core_mask = 0; uint32_t core_index = 0; - uint32_t raw_spwu = (in32(CME_LCL_EISR) & BITS32(14, 2)) >> SHIFT32(15); + uint32_t raw_spwu = (in32(G_CME_LCL_EISR) & BITS32(14, 2)) >> SHIFT32(15); uint64_t scom_data = 0; MARK_TRAP(STOP_SPWU_HANDLER) @@ -136,7 +136,7 @@ p9_cme_stop_spwu_handler(void) // if falling edge == spwu drop: if (G_cme_stop_record.core_in_spwu & core_mask) { - if (in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_SPWU_CHECK_ENABLE)) + if (in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_SPWU_CHECK_ENABLE)) { CME_GETSCOM(PPM_SSHSRC, core_mask, scom_data); @@ -149,13 +149,13 @@ p9_cme_stop_spwu_handler(void) } PK_TRACE("Falling edge of spwu, first clearing EISR"); - out32(CME_LCL_EISR_CLR, BIT32((14 + core_index))); + out32(G_CME_LCL_EISR_CLR, BIT32((14 + core_index))); // if spwu asserts again before we drop spwu_done, do nothing, else: - if ((~(in32(CME_LCL_EINR))) & BIT32((14 + core_index))) + if ((~(in32(G_CME_LCL_EINR))) & BIT32((14 + core_index))) { PK_TRACE("SPWU drop confirmed, now dropping spwu_done"); - out32(CME_LCL_SICR_CLR, BIT32((16 + core_index))); + out32(G_CME_LCL_SICR_CLR, BIT32((16 + core_index))); CME_GETSCOM(PPM_GPMMR, core_mask, scom_data); @@ -163,14 +163,14 @@ p9_cme_stop_spwu_handler(void) if (scom_data & BIT64(1)) { PK_TRACE("SPWU asserts again, re-asserting spwu_done"); - out32(CME_LCL_SICR_OR, BIT32((16 + core_index))); + out32(G_CME_LCL_SICR_OR, BIT32((16 + core_index))); } // if spwu truly dropped: else { PK_TRACE("Flip EIPR to raising edge and drop pm_exit"); - out32(CME_LCL_EIPR_OR, BIT32((14 + core_index))); - out32(CME_LCL_SICR_CLR, BIT32((4 + core_index))); + out32(G_CME_LCL_EIPR_OR, BIT32((14 + core_index))); + out32(G_CME_LCL_SICR_CLR, BIT32((4 + core_index))); // Core is now out of spwu, allow pm_active // block entry mode is handled via eimr override @@ -199,7 +199,7 @@ p9_cme_stop_spwu_handler(void) { PK_TRACE_INF("SPWU Launching exit thread"); - out32(CME_LCL_EIMR_OR, BITS32(12, 10)); + out32(G_CME_LCL_EIMR_OR, BITS32(12, 10)); g_eimr_override |= BITS64(12, 10); G_cme_stop_record.exit_ongoing = 1; wrteei(1); @@ -225,7 +225,7 @@ p9_cme_stop_rgwu_handler(void) MARK_TRAP(STOP_RGWU_HANDLER) PK_TRACE_INF("RGWU Handler Trigger"); - out32(CME_LCL_EIMR_OR, BITS32(12, 10)); + out32(G_CME_LCL_EIMR_OR, BITS32(12, 10)); g_eimr_override |= BITS64(12, 10); G_cme_stop_record.exit_ongoing = 1; wrteei(1); @@ -252,7 +252,7 @@ p9_cme_stop_enter_handler(void) PK_TRACE_INF("PM_ACTIVE Handler Trigger"); // Abort Protection - out32(CME_LCL_EIMR_OR, BITS32(12, 10)); + out32(G_CME_LCL_EIMR_OR, BITS32(12, 10)); g_eimr_override |= BITS64(12, 10); G_cme_stop_record.entry_ongoing = 1; wrteei(1); @@ -274,7 +274,7 @@ p9_cme_stop_db2_handler(void) { cppm_cmedb2_t db2 = {0}; ppm_pig_t pig = {0}; - uint32_t core = (in32(CME_LCL_EISR) & BITS32(18, 2)) >> SHIFT32(19); + uint32_t core = (in32(G_CME_LCL_EISR) & BITS32(18, 2)) >> SHIFT32(19); uint32_t core_mask; MARK_TRAP(STOP_DB2_HANDLER) @@ -286,7 +286,7 @@ p9_cme_stop_db2_handler(void) { CME_GETSCOM(CPPM_CMEDB2, core_mask, db2.value); CME_PUTSCOM_NOP(CPPM_CMEDB2, core_mask, 0); - out32(CME_LCL_EISR_CLR, (core_mask << SHIFT32(19))); + out32(G_CME_LCL_EISR_CLR, (core_mask << SHIFT32(19))); PK_TRACE_DBG("DB2 Handler MessageID %d Triggered By Core %d", db2.fields.cme_message_numbern, core_mask); @@ -306,7 +306,7 @@ p9_cme_stop_db2_handler(void) #ifdef USE_CME_RESCLK_FEATURE // Quad going into Stop11, need to potentially disable Resclks - if((in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_RCLK_OPERABLE)) + if((in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_RCLK_OPERABLE)) && G_cme_pstate_record.qmFlag) { @@ -315,7 +315,7 @@ p9_cme_stop_db2_handler(void) // prevent Pstate changes from accidentally re-enabling // in the meantime before interlock with PGPE - out32(CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_RCLK_OPERABLE)); + out32(G_CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_RCLK_OPERABLE)); // in case we abort, need this flag to get into reenable below G_ndd20_disable_stop8_abort_stop11_rclk_handshake_flag = 1; } @@ -336,7 +336,7 @@ p9_cme_stop_db2_handler(void) // Quad aborted Stop11, need to regressively enable Resclks // IF wakeup from fully entered Stop11, this is done by QM - if(((in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_RCLK_OPERABLE)) || + if(((in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_RCLK_OPERABLE)) || G_ndd20_disable_stop8_abort_stop11_rclk_handshake_flag) && G_cme_pstate_record.qmFlag) { @@ -344,7 +344,7 @@ p9_cme_stop_db2_handler(void) G_cme_pstate_record.resclkData.common_resclk_idx); // reenable pstate from changing resonant clock - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_RCLK_OPERABLE)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_RCLK_OPERABLE)); // clear abort flag to start clean slate G_ndd20_disable_stop8_abort_stop11_rclk_handshake_flag = 0; } @@ -414,15 +414,15 @@ p9_cme_stop_db1_handler(void) #if HW386841_NDD1_DSL_STOP1_FIX // Set AUTO_STOP1_DISABLE - out32(CME_LCL_LMCR_OR, BIT32(18)); + out32(G_CME_LCL_LMCR_OR, BIT32(18)); #endif // Set PM_BLOCK_INTERRUPTS - out32(CME_LCL_SICR_OR, BITS32(2, 2)); + out32(G_CME_LCL_SICR_OR, BITS32(2, 2)); // Block Exit Enabled - out32(CME_LCL_FLAGS_OR, BITS32(8, 2)); + out32(G_CME_LCL_FLAGS_OR, BITS32(8, 2)); } // entry @@ -442,12 +442,12 @@ p9_cme_stop_db1_handler(void) #if HW386841_NDD1_DSL_STOP1_FIX // Set AUTO_STOP1_DISABLE - out32(CME_LCL_LMCR_OR, BIT32(18)); + out32(G_CME_LCL_LMCR_OR, BIT32(18)); #endif // Block Entry Enabled - out32(CME_LCL_FLAGS_OR, BITS32(10, 2)); + out32(G_CME_LCL_FLAGS_OR, BITS32(10, 2)); } } // unblock/unsuspend msgs(0x2-0x7) @@ -472,15 +472,15 @@ p9_cme_stop_db1_handler(void) #if HW386841_NDD1_DSL_STOP1_FIX // Clear AUTO_STOP1_DISABLE - out32(CME_LCL_LMCR_CLR, BIT32(18)); + out32(G_CME_LCL_LMCR_CLR, BIT32(18)); #endif // Clear PM_BLOCK_INTERRUPTS - out32(CME_LCL_SICR_CLR, BITS32(2, 2)); + out32(G_CME_LCL_SICR_CLR, BITS32(2, 2)); // Block Exit Disabled - out32(CME_LCL_FLAGS_CLR, BITS32(8, 2)); + out32(G_CME_LCL_FLAGS_CLR, BITS32(8, 2)); } // entry @@ -500,12 +500,12 @@ p9_cme_stop_db1_handler(void) #if HW386841_NDD1_DSL_STOP1_FIX // Clear AUTO_STOP1_DISABLE - out32(CME_LCL_LMCR_CLR, BIT32(18)); + out32(G_CME_LCL_LMCR_CLR, BIT32(18)); #endif // Block Entry Disabled - out32(CME_LCL_FLAGS_CLR, BITS32(10, 2)); + out32(G_CME_LCL_FLAGS_CLR, BITS32(10, 2)); } } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c index 55f7db99..e85942c6 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c @@ -35,7 +35,7 @@ extern CmeRecord G_cme_record; // bit1 is Recoverable Error // bit2 is Special Attention // bit3 is Core Checkstop -#define bad_error_present (((in32 (CME_LCL_SISR) & ( BIT32(12) | BITS32(14,2)))) || \ +#define bad_error_present (((in32 (G_CME_LCL_SISR) & (BIT32(12) | BITS32(14,2)))) || \ ((in32_sh(CME_LCL_SISR) & (BIT64SH(60) | BITS64SH(62,2))))) void @@ -47,14 +47,14 @@ p9_cme_stop_core_error_handler(uint32_t core, uint32_t core_error, uint32_t pani G_cme_stop_record.error_code[core_error & 1] = panic_code; // set the WKUP_FAIL_STATUS breadcrumbs - out32(CME_LCL_SICR_OR, core_error << SHIFT32(15)); + out32(G_CME_LCL_SICR_OR, core_error << SHIFT32(15)); // this pulses the FIR trigger using CME Local Debug register // to optionally set a recoverable or xstop on error // Note: the following to due to OR/CLR interface is lack in hw - uint32_t cme_lcl_debug = in32(CME_LCL_DBG); - out32(CME_LCL_DBG, cme_lcl_debug | BIT32(16)); - out32(CME_LCL_DBG, cme_lcl_debug); + uint32_t cme_lcl_debug = in32(G_CME_LCL_DBG); + out32(G_CME_LCL_DBG, cme_lcl_debug | BIT32(16)); + out32(G_CME_LCL_DBG, cme_lcl_debug); } void @@ -97,11 +97,11 @@ p9_cme_stop_eval_eimr_override() if (G_cme_stop_record.core_vdm_droop) { - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_DROOP_SUSPEND_ENTRY)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_DROOP_SUSPEND_ENTRY)); } else { - out32(CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_DROOP_SUSPEND_ENTRY)); + out32(G_CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_DROOP_SUSPEND_ENTRY)); } } @@ -142,11 +142,11 @@ p9_cme_core_livelock_buster() if (!core_quiesce_cpmmr_disable) { - out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_CORE_QUIESCE_ACTIVE)); + out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_CORE_QUIESCE_ACTIVE)); } else { - out32(CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_CORE_QUIESCE_ACTIVE)); + out32(G_CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_CORE_QUIESCE_ACTIVE)); } // only run workaround if @@ -163,7 +163,7 @@ p9_cme_core_livelock_buster() if((G_cme_record.core_enabled == CME_MASK_BC) && (core_instr_running != 0) && - (!(in32(CME_LCL_SISR) & BITS32(16, 2))) && + (!(in32(G_CME_LCL_SISR) & BITS32(16, 2))) && (!core_quiesce_cpmmr_disable) && (!bad_error_present)) { @@ -202,26 +202,26 @@ void periodic_core_quiesce_workaround(uint32_t core_instruction_running) //0) in case in stop0/1 that we dont know about PK_TRACE("PCQW: Assert block interrupt to PC via SICR[2/3]"); - out32(CME_LCL_SICR_OR, core_instruction_running << SHIFT32(3)); + out32(G_CME_LCL_SICR_OR, core_instruction_running << SHIFT32(3)); PK_TRACE("PCQW: Waking up the core(pm_exit=1) via SICR[4/5]"); - out32(CME_LCL_SICR_OR, core_instruction_running << SHIFT32(5)); + out32(G_CME_LCL_SICR_OR, core_instruction_running << SHIFT32(5)); CME_PM_EXIT_DELAY PK_TRACE("PCQW: Polling for core wakeup(pm_active=0) via EINR[20/21]"); - while((in32(CME_LCL_EINR)) & (core_instruction_running << SHIFT32(21))); + while((in32(G_CME_LCL_EINR)) & (core_instruction_running << SHIFT32(21))); //1) Acquire Pcb Mux - core_accessible = ((~in32(CME_LCL_SISR)) >> SHIFT32(11)) & core_instruction_running; + core_accessible = ((~in32(G_CME_LCL_SISR)) >> SHIFT32(11)) & core_instruction_running; PK_TRACE("PCQW: Request PCB Mux via SICR[10/11]"); - out32(CME_LCL_SICR_OR, core_accessible << SHIFT32(11)); + out32(G_CME_LCL_SICR_OR, core_accessible << SHIFT32(11)); // Poll Infinitely for PCB Mux Grant - while((core_accessible & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core_accessible); + while((core_accessible & (in32(G_CME_LCL_SISR) >> SHIFT32(11))) != core_accessible); PK_TRACE("PCQW: PCB Mux Granted"); @@ -287,7 +287,7 @@ void periodic_core_quiesce_workaround(uint32_t core_instruction_running) //4) Loop on RAS_STATUS Scom Addr(20:31) = x0A02 // until bit(1 + 8*T) THREAD_QUIESCE are all active b1 - time_stamp[0] = in32(CME_LCL_TBR); + time_stamp[0] = in32(G_CME_LCL_TBR); #if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1 @@ -315,7 +315,7 @@ void periodic_core_quiesce_workaround(uint32_t core_instruction_running) { CME_GETSCOM_AND(RAS_STATUS, core, scom_data.value); - time_stamp[1] = in32(CME_LCL_TBR); + time_stamp[1] = in32(G_CME_LCL_TBR); if (time_stamp[1] > time_stamp[0]) { @@ -411,17 +411,17 @@ void periodic_core_quiesce_workaround(uint32_t core_instruction_running) //7) Drop pm_exit PK_TRACE("PCQW: Drop pm_exit via SICR[4/5]"); - out32(CME_LCL_SICR_CLR, core_instruction_running << SHIFT32(5)); + out32(G_CME_LCL_SICR_CLR, core_instruction_running << SHIFT32(5)); PK_TRACE("PCQW: Drop block interrupt to PC via SICR[2/3]"); - out32(CME_LCL_SICR_CLR, core_instruction_running << SHIFT32(3)); + out32(G_CME_LCL_SICR_CLR, core_instruction_running << SHIFT32(3)); //8) Release Pcb Mux on Both Cores PK_TRACE("PCQW: Release PCB Mux back on Both Cores via SICR[10/11]"); - out32(CME_LCL_SICR_CLR, core_accessible << SHIFT32(11)); + out32(G_CME_LCL_SICR_CLR, core_accessible << SHIFT32(11)); - while((core_accessible & ~(in32(CME_LCL_SISR) >> SHIFT32(11))) != core_accessible); + while((core_accessible & ~(in32(G_CME_LCL_SISR) >> SHIFT32(11))) != core_accessible); PK_TRACE("PCQW: PCB Mux Released on Both Cores"); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c index 8ddd904c..1d15d753 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c @@ -98,6 +98,9 @@ p9_hcd_core_chiplet_reset(uint32_t core) // to get the core to scan at 4:1, need to put a scan ratio of 2:1 if run at pll speed. PK_TRACE("Set scan ratio to 2:1 in non-bypass mode via OPCG_ALIGN[47-51]"); + // Marker for scan0 + MARK_TRAP(SX_CHIPLET_RESET_SCAN0) + // this register requires unicast, dual cast with eq check will fail for(core_mask = 2; core_mask; core_mask--) { @@ -110,8 +113,6 @@ p9_hcd_core_chiplet_reset(uint32_t core) #endif CME_PUTSCOM(C_OPCG_ALIGN, core_mask, scom_data.value); - // Marker for scan0 - MARK_TRAP(SX_CHIPLET_RESET_SCAN0) #if !SKIP_SCAN0 p9_hcd_core_scan0(core_mask, SCAN0_REGION_ALL, SCAN0_TYPE_GPTR_REPR_TIME); p9_hcd_core_scan0(core_mask, SCAN0_REGION_ALL, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME); @@ -120,7 +121,6 @@ p9_hcd_core_chiplet_reset(uint32_t core) } } - /// content of p9_hcd_core_dcc_skewadjust below: PK_TRACE("Drop core DCC bypass via NET_CTRL[1]"); CME_PUTSCOM(CPPM_NC1INDIR_CLR, core, BIT64(1)); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c index ccd27bfa..087f8715 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,11 +30,11 @@ void p9_hcd_core_pcb_arb(uint32_t core, uint8_t req_rel) { uint32_t sisr = 0; - out32(req_rel ? CME_LCL_SICR_OR : CME_LCL_SICR_CLR, core << SHIFT32(11)); + out32(req_rel ? G_CME_LCL_SICR_OR : G_CME_LCL_SICR_CLR, core << SHIFT32(11)); do { - sisr = in32(CME_LCL_SISR) >> SHIFT32(11); + sisr = in32(G_CME_LCL_SISR) >> SHIFT32(11); if((req_rel && (core & sisr == core)) || ((!req_rel) && (core & (~sisr) == core))) { diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c index 3154fb47..73aaef57 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c @@ -218,5 +218,5 @@ p9_hcd_core_startclocks(uint32_t core) CME_PUTSCOM(C_CPLT_CTRL0_CLEAR, core, BIT64(2)); PK_TRACE("Drop Core-L2/CC/TLBIE Quiesces via CME_LCL_SICR[6,8]/[7,9][21]"); - out32(CME_LCL_SICR_CLR, ((core << SHIFT32(7)) | (core << SHIFT32(9)) | BIT32(21))); + out32(G_CME_LCL_SICR_CLR, ((core << SHIFT32(7)) | (core << SHIFT32(9)) | BIT32(21))); } diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c index 24e3a381..f4c09943 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c @@ -1398,7 +1398,7 @@ void p9_pgpe_pstate_send_suspend_stop() p9_pgpe_optrace(PRC_PM_SUSP); int rc; - G_sgpe_suspend_stop.fields.msg_num = MSGID_PGPE_SGPE_SUSPEND_STOP; + G_sgpe_suspend_stop.fields.msg_num = 0; G_sgpe_suspend_stop.fields.command = SUSPEND_STOP_SUSPEND_ENTRY_EXIT; G_sgpe_suspend_stop.fields.return_code = 0x0; G_ipc_msg_pgpe_sgpe.cmd_data = &G_sgpe_suspend_stop; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C index 8a51798c..982a0eb8 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2017 */ +/* COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -63,7 +63,7 @@ extern "C" void p9_hcd_cache_dcc_skewadjust_setup(uint32_t quad) do { - ccsr.value = in32(OCB_CCSR); + ccsr.value = in32(G_OCB_CCSR); } while (ccsr.fields.change_in_progress); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c index cbe1bb02..f6c09e1e 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c @@ -60,7 +60,7 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8) // read partial good exes for LCO setup below do { - qcsr.value = in32(OCB_QCSR); + qcsr.value = in32(G_OCB_QCSR); } while (qcsr.fields.change_in_progress); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c index 06b3464a..32938927 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c @@ -172,17 +172,17 @@ void pk_unified_irq_prty_mask_handler(void) // First, clear all those IRQs that could possibly interrupt this instance. // This includes all those IRQs which belong to this instance as well as // those high-prty IRQs shared with the other instances. - out32(OCB_OIMR0_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS >> 32)); - out32(OCB_OIMR1_CLR, (uint32_t)IRQ_VEC_ALL_OUR_IRQS); + out32(G_OCB_OIMR0_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS >> 32)); + out32(G_OCB_OIMR1_CLR, (uint32_t)IRQ_VEC_ALL_OUR_IRQS); // Second, mask IRQs belonging to this task and lower prty tasks. // Note, that we do not modify the permanently disabled IRQs, such as the // _RESERVED_ ones. Nor do we touch other instances' IRQs. Iow, the // IDX_PRTY_LVL_DISABLED mask is NOT part of the mask we apply below. - out32(OCB_OIMR0_OR, (uint32_t)((ext_irq_vectors_sgpe[iPrtyLvl][IDX_MASK_VEC] | - g_oimr_override) >> 32) ); - out32(OCB_OIMR1_OR, (uint32_t)(ext_irq_vectors_sgpe[iPrtyLvl][IDX_MASK_VEC] | - g_oimr_override) ); + out32(G_OCB_OIMR0_OR, (uint32_t)((ext_irq_vectors_sgpe[iPrtyLvl][IDX_MASK_VEC] | + g_oimr_override) >> 32) ); + out32(G_OCB_OIMR1_OR, (uint32_t)(ext_irq_vectors_sgpe[iPrtyLvl][IDX_MASK_VEC] | + g_oimr_override) ); } else diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h index 8dd4771d..6e739424 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h @@ -46,6 +46,11 @@ // - The variable names and actions in this file must perfectly match associated // definitions in p9_sgpe_irq.c +extern uint32_t G_OCB_OIMR0_CLR; +extern uint32_t G_OCB_OIMR0_OR; +extern uint32_t G_OCB_OIMR1_CLR; +extern uint32_t G_OCB_OIMR1_OR; + // Priority Levels #define IDX_PRTY_LVL_HIPRTY 0 #define IDX_PRTY_LVL_IPI3_HIGH 1 @@ -106,14 +111,14 @@ pk_irq_vec_restore(PkMachineContext* context) if (g_oimr_stack_ctr >= 0) { - out32(OCB_OIMR0_CLR, (uint32_t)((IRQ_VEC_ALL_OUR_IRQS | - g_oimr_override_stack[g_oimr_stack_ctr]) >> 32)); - out32(OCB_OIMR1_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS | - g_oimr_override_stack[g_oimr_stack_ctr])); - out32(OCB_OIMR0_OR, + out32(G_OCB_OIMR0_CLR, (uint32_t)((IRQ_VEC_ALL_OUR_IRQS | + g_oimr_override_stack[g_oimr_stack_ctr]) >> 32)); + out32(G_OCB_OIMR1_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS | + g_oimr_override_stack[g_oimr_stack_ctr])); + out32(G_OCB_OIMR0_OR, (uint32_t)((ext_irq_vectors_sgpe[g_oimr_stack[g_oimr_stack_ctr]][IDX_MASK_VEC] | g_oimr_override) >> 32)); - out32(OCB_OIMR1_OR, + out32(G_OCB_OIMR1_OR, (uint32_t)(ext_irq_vectors_sgpe[g_oimr_stack[g_oimr_stack_ctr]][IDX_MASK_VEC] | g_oimr_override)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C index 873cf238..825ae9c0 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C @@ -27,6 +27,46 @@ #include <fapi2.H> +//We define a global literal for these register addresses +////This way compiler put them in .sdata area, and the address +////can be loaded with one instruction using r13 as offset into +////sdata area. The change helped save about 448 bytes of code space. +////Note, some register's address were not moved to using global literals +////because in some cases they registers are accessed few times or they are +////used inside a loop. In both cases, either no code reduction was observed +////or resulted in code increase. +uint32_t G_OCB_CCSR = OCB_CCSR; +uint32_t G_OCB_QCSR = OCB_QCSR; +uint32_t G_OCB_QSSR = OCB_QSSR; +uint32_t G_OCB_QSSR_CLR = OCB_QSSR_CLR; +uint32_t G_OCB_QSSR_OR = OCB_QSSR_OR; +uint32_t G_OCB_OCCFLG = OCB_OCCFLG; +uint32_t G_OCB_OCCFLG_CLR = OCB_OCCFLG_CLR; +uint32_t G_OCB_OCCFLG_OR = OCB_OCCFLG_OR; +uint32_t G_OCB_OCCFLG2 = OCB_OCCFLG2; +uint32_t G_OCB_OCCS2 = OCB_OCCS2; +uint32_t G_OCB_OISR0_CLR = OCB_OISR0_CLR; +uint32_t G_OCB_OISR1 = OCB_OISR1; +uint32_t G_OCB_OISR1_CLR = OCB_OISR1_CLR; +uint32_t G_OCB_OIMR0_CLR = OCB_OIMR0_CLR; +uint32_t G_OCB_OIMR0_OR = OCB_OIMR0_OR; +uint32_t G_OCB_OIMR1_CLR = OCB_OIMR1_CLR; +uint32_t G_OCB_OIMR1_OR = OCB_OIMR1_OR ; +uint32_t G_OCB_OPIT0PRA = OCB_OPIT0PRA; +uint32_t G_OCB_OPIT2PRA = OCB_OPIT2PRA; +uint32_t G_OCB_OPIT3PRA = OCB_OPIT3PRA; +uint32_t G_OCB_OPIT6PRB = OCB_OPIT6PRB; +uint32_t G_OCB_OPIT0PRA_CLR = OCB_OPIT0PRA_CLR; +uint32_t G_OCB_OPIT1PRA_CLR = OCB_OPIT1PRA_CLR; +uint32_t G_OCB_OPIT2PRA_CLR = OCB_OPIT2PRA_CLR; +uint32_t G_OCB_OPIT3PRA_CLR = OCB_OPIT3PRA_CLR; +uint32_t G_OCB_OPIT4PRA_CLR = OCB_OPIT4PRA_CLR; +uint32_t G_OCB_OPIT5PRA_CLR = OCB_OPIT5PRA_CLR; +uint32_t G_OCB_OPIT6PRB_CLR = OCB_OPIT6PRB_CLR; +uint32_t G_OCB_OPIT7PRB_CLR = OCB_OPIT7PRB_CLR; +uint32_t G_OCB_OCCLFIR_AND = OCB_OCCLFIR_AND; +uint32_t G_GPE_GPE3TSEL = GPE_GPE3TSEL; + EXTERNAL_IRQ_TABLE_START IRQ_HANDLER_DEFAULT //OCCHW_IRQ_DEBUGGER @@ -150,7 +190,7 @@ main(int argc, char** argv) PK_PANIC(SGPE_BAD_DD_LEVEL); } - if (in32(OCB_OCCS2) & BIT32(SPGE_DEBUG_TRAP_ENABLE)) + if (in32(G_OCB_OCCS2) & BIT32(SPGE_DEBUG_TRAP_ENABLE)) { PK_TRACE_INF("BREAK: Trap at SGPE Booted"); asm volatile ("trap"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index 9cb875b0..d4ef5dff 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -71,6 +71,39 @@ extern "C" { #endif +extern uint32_t G_OCB_CCSR; +extern uint32_t G_OCB_QCSR; +extern uint32_t G_OCB_QSSR; +extern uint32_t G_OCB_QSSR_CLR; +extern uint32_t G_OCB_QSSR_OR; +extern uint32_t G_OCB_OCCFLG; +extern uint32_t G_OCB_OCCFLG_CLR; +extern uint32_t G_OCB_OCCFLG_OR; +extern uint32_t G_OCB_OCCFLG2; +extern uint32_t G_OCB_OCCS2; +extern uint32_t G_OCB_OISR0_CLR; +extern uint32_t G_OCB_OISR1; +extern uint32_t G_OCB_OISR1_CLR; +extern uint32_t G_OCB_OIMR0_CLR; +extern uint32_t G_OCB_OIMR0_OR; +extern uint32_t G_OCB_OIMR1_CLR; +extern uint32_t G_OCB_OIMR1_OR; +extern uint32_t G_OCB_OPIT0PRA; +extern uint32_t G_OCB_OPIT2PRA; +extern uint32_t G_OCB_OPIT3PRA; +extern uint32_t G_OCB_OPIT6PRB; +extern uint32_t G_OCB_OPIT0PRA_CLR; +extern uint32_t G_OCB_OPIT1PRA_CLR; +extern uint32_t G_OCB_OPIT2PRA_CLR; +extern uint32_t G_OCB_OPIT3PRA_CLR; +extern uint32_t G_OCB_OPIT4PRA_CLR; +extern uint32_t G_OCB_OPIT5PRA_CLR; +extern uint32_t G_OCB_OPIT6PRB_CLR; +extern uint32_t G_OCB_OPIT7PRB_CLR; +extern uint32_t G_OCB_OCCLFIR_AND; +extern uint32_t G_GPE_GPE3TSEL; + + #define DEBUG_TRACE_CONTROL 0x100107D0 #define L3TRA_TRACE_TRCTRL_CONFIG 0x10010402 #define L3TRA_TRACE_TRDATA_CONFIG_0 0x10010403 @@ -181,7 +214,7 @@ extern "C" { #define PK_OPTIONAL_DEBUG_HALT(panic_code) \ - if (in32(OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) {PK_PANIC(panic_code);} + if (in32(G_OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) {PK_PANIC(panic_code);} #define SGPE_STOP_QUAD_ERROR_HANDLER(quad_error, panic_code) \ diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index 1659055f..2c92bdb4 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -69,7 +69,7 @@ p9_sgpe_stop_entry() MARK_TAG(BEGINSCOPE_STOP_ENTRY, 0) //================================ - if( in32(OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ)) + if( in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ)) { PK_TRACE_ERR("SGPE STOP ENTRY ERROR INJECT TRAP"); PK_PANIC(SGPE_STOP_ENTRY_TRAP_INJECT); @@ -154,7 +154,7 @@ p9_sgpe_stop_entry() G_sgpe_stop_record.group.quad[VECTOR_ENTRY] |= BIT32(qloop); ocb_qssr_t qssr = {0}; - qssr.value = in32(OCB_QSSR); + qssr.value = in32(G_OCB_QSSR); // check qssr for already stopped ex G_sgpe_stop_record.group.ex01[qloop] = @@ -420,7 +420,7 @@ p9_sgpe_stop_entry() } PK_TRACE("Update QSSR: stop_entry_ongoing"); - out32(OCB_QSSR_OR, BIT32(qloop + 20)); + out32(G_OCB_QSSR_OR, BIT32(qloop + 20)); //==================================================== MARK_TAG(SE_STOP_L2_CLKS, ((ex << 6) | (32 >> qloop))) @@ -555,8 +555,8 @@ p9_sgpe_stop_entry() } PK_TRACE("Update QSSR: l2_stopped, drop stop_entry_ongoing"); - out32(OCB_QSSR_CLR, BIT32(qloop + 20)); - out32(OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1))); + out32(G_OCB_QSSR_CLR, BIT32(qloop + 20)); + out32(G_OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1))); PK_TRACE_DBG("SE.8C: L2 Clock Sync Dropped"); @@ -643,7 +643,7 @@ p9_sgpe_stop_entry() GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); PK_TRACE("Update QSSR: stop_entry_ongoing"); - out32(OCB_QSSR_OR, BIT32(qloop + 20)); + out32(G_OCB_QSSR_OR, BIT32(qloop + 20)); PK_TRACE_INF("SE.11A: Quad[%d] EX_PG[%d] Shutting Cache Down", qloop, ex); @@ -721,14 +721,14 @@ p9_sgpe_stop_entry() #if !SKIP_L3_PURGE_ABORT - if ((in32(OCB_OISR1) & (BITS32(15, 2) | BIT32(19))) && + if ((in32(G_OCB_OISR1) & (BITS32(15, 2) | BIT32(19))) && // Skip L3 Purge Abort check if in Block Wakeup mode (!(G_sgpe_stop_record.group.quad[VECTOR_BLOCKX] & BIT32(qloop)))) { PK_TRACE("Abort: interrupt detected"); - if ((in32(OCB_OPITNPRA(2)) & BITS32((qloop << 2), 4)) || - (in32(OCB_OPITNPRA(3)) & BITS32((qloop << 2), 4))) + if ((in32(G_OCB_OPIT2PRA) & BITS32((qloop << 2), 4)) || + (in32(G_OCB_OPIT3PRA) & BITS32((qloop << 2), 4))) { PK_TRACE("Abort: core interrupt detected"); @@ -746,7 +746,7 @@ p9_sgpe_stop_entry() } } - if ((in32(OCB_OPIT6PRB) & BIT32(qloop)) && + if ((in32(G_OCB_OPIT6PRB) & BIT32(qloop)) && (in32(OCB_OPIT6QN(qloop)) & TYPE6_PAYLOAD_EXIT_EVENT)) { PK_TRACE_DBG("Abort: quad wakeup detected"); @@ -913,7 +913,7 @@ p9_sgpe_stop_entry() // 4. optionally finishes the entry (if not done above) if ((!ipc_quad_entry) && - (in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && + (in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED && G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) // entry into STOP11 { @@ -1323,10 +1323,10 @@ p9_sgpe_stop_entry() GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); PK_TRACE("Update QSSR: quad_stopped"); - out32(OCB_QSSR_OR, BIT32(qloop + 14)); + out32(G_OCB_QSSR_OR, BIT32(qloop + 14)); PK_TRACE("Update QSSR: drop stop_entry_ongoing"); - out32(OCB_QSSR_CLR, BIT32(qloop + 20)); + out32(G_OCB_QSSR_CLR, BIT32(qloop + 20)); G_sgpe_stop_record.state[qloop].act_state_q = STOP_LEVEL_11; G_sgpe_stop_record.group.quad[VECTOR_ACTIVE] &= ~BIT32(qloop); @@ -1343,7 +1343,7 @@ p9_sgpe_stop_entry() #if !SKIP_IPC - if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && + if ((in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED && G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) { diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index f8df2305..bca3a1de 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -146,7 +146,7 @@ p9_sgpe_stop_exit_lv8(uint32_t qloop) if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000) { - PK_TRACE_ERR("ERROR: Failed to Obtain Cache %d Clk Ctrl Atomic Lock. Register Content: %x", + PK_TRACE_ERR("ERROR: Fail to Obtain Cache %d Clk Ctrl Atomic Lock. Register Content: %x", qloop, scom_data.words.upper); SGPE_STOP_QUAD_ERROR_HANDLER(qloop, SGPE_STOP_EXIT_GET_CLK_LOCK_FAILED); return; @@ -193,7 +193,7 @@ p9_sgpe_stop_exit_lv8(uint32_t qloop) } PK_TRACE("Update QSSR: drop l2_stopped"); - out32(OCB_QSSR_CLR, (ex << SHIFT32((qloop << 1) + 1))); + out32(G_OCB_QSSR_CLR, (ex << SHIFT32((qloop << 1) + 1))); } @@ -252,7 +252,7 @@ p9_sgpe_stop_exit_end(uint32_t qloop) } PK_TRACE("Update QSSR: drop stop_exit_ongoing"); - out32(OCB_QSSR_CLR, BIT32(qloop + 26)); + out32(G_OCB_QSSR_CLR, BIT32(qloop + 26)); } //------------------------------------------------------------------------- @@ -309,8 +309,8 @@ p9_sgpe_stop_exit_handoff_cme(uint32_t cindex) // clear possible phantom interrupts after handoff to cme // there shouldnt be any valid entry or exit to process - out32(OCB_OPITNPRA_CLR(2), BIT32(cindex)); - out32(OCB_OPITNPRA_CLR(3), BIT32(cindex)); + out32(G_OCB_OPIT2PRA_CLR, BIT32(cindex)); + out32(G_OCB_OPIT3PRA_CLR, BIT32(cindex)); // From IPC prospective, core is active when handoff to cme // and if core from quad is active, the quad is active @@ -360,7 +360,7 @@ p9_sgpe_stop_exit() G_sgpe_stop_record.group.ex01[4] = 0; G_sgpe_stop_record.group.ex01[5] = 0; - if(in32(OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ)) + if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ)) { PK_TRACE_ERR("SGPE STOP EXIT ERROR INJECT TRAP"); PK_PANIC(SGPE_STOP_EXIT_TRAP_INJECT); @@ -398,7 +398,7 @@ p9_sgpe_stop_exit() } PK_TRACE("Update QSSR: stop_exit_ongoing"); - out32(OCB_QSSR_OR, BIT32(qloop + 26)); + out32(G_OCB_QSSR_OR, BIT32(qloop + 26)); for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) { @@ -443,7 +443,7 @@ p9_sgpe_stop_exit() // PGPE, as part of its processing this IPC, // will write the QPPM_DPLL_FREQ register before responding. - if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && + if ((in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED && G_sgpe_stop_record.group.quad[VECTOR_EXIT]) { @@ -872,7 +872,7 @@ p9_sgpe_stop_exit() // Setting up cme_flags do { - ccsr.value = in32(OCB_CCSR); + ccsr.value = in32(G_OCB_CCSR); } while (ccsr.fields.change_in_progress); @@ -944,7 +944,7 @@ p9_sgpe_stop_exit() #endif - if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && (in32(OCB_OCCS2) & BIT32(PGPE_PSTATE_PROTOCOL_ACTIVE))) + if ((in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && (in32(G_OCB_OCCS2) & BIT32(PGPE_PSTATE_PROTOCOL_ACTIVE))) { GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CSAR_OR, (ec_index + cloop)), BIT64(CPPM_CSAR_ENABLE_PSTATE_REGISTRATION_INTERLOCK)); @@ -969,7 +969,7 @@ p9_sgpe_stop_exit() continue; } - if (in32(OCB_OCCS2) & BIT32(CME_DEBUG_TRAP_ENABLE)) + if (in32(G_OCB_OCCS2) & BIT32(CME_DEBUG_TRAP_ENABLE)) { PK_TRACE_INF("BREAK: Trap Before CME Boot"); asm volatile ("trap"); @@ -994,7 +994,7 @@ p9_sgpe_stop_exit() GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); PK_TRACE("Update QSSR: drop quad_stopped"); - out32(OCB_QSSR_CLR, BIT32(qloop + 14)); + out32(G_OCB_QSSR_CLR, BIT32(qloop + 14)); G_sgpe_stop_record.state[qloop].act_state_q = 0; p9_sgpe_stop_exit_end(qloop); @@ -1003,7 +1003,7 @@ p9_sgpe_stop_exit() #if !SKIP_IPC - if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && + if ((in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED && G_sgpe_stop_record.group.quad[VECTOR_EXIT]) { diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit_marks.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit_marks.h index 45cd050f..fcf0755d 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit_marks.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit_marks.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -52,9 +52,9 @@ enum SGPE_SX_MARKS SX_L2_STARTCLOCKS_ALIGN = 0x130, SX_L2_STARTCLOCKS_REGION = 0x138, SX_SCOM_INITS = 0x140, - SX_CME_BOOT = 0x148, - SX_RUNTIME_INITS = 0x150, - SX_ENABLE_ANALOG = 0x168, + SX_RUNTIME_INITS = 0x148, + SX_ENABLE_ANALOG = 0x150, + SX_CME_BOOT = 0x168, SX_LESSTHAN8_WAIT = 0x1e0 }; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c index 48bc69e8..bada474a 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c @@ -81,7 +81,7 @@ void p9_sgpe_stop_cme_scominit(uint32_t quad, uint32_t cme, uint32_t cme_flags) //CME_LFIR[0,1,2,3,4] should generate CME PCB Error Packet(type5 owned by PGPE) //(1,0,0)(Act0,Act1,Mask) = CME PCB Error Packet - PK_TRACE("Setup CME FIR Act0/Act1/Mask for CME_LFIR[0,1,2,3,4]") + PK_TRACE("Setup CME FIR Act0/Act1/Mask for CME_LFIR[0,1,2,3,4]"); GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LFIRACT0, quad, cme), scom_data.value); scom_data.value |= BITS64(0, 5); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LFIRACT0, quad, cme), scom_data.value); @@ -284,19 +284,19 @@ p9_sgpe_stop_init() // read partial good cores do { - ccsr.value = in32(OCB_CCSR); + ccsr.value = in32(G_OCB_CCSR); } while (ccsr.fields.change_in_progress); // read partial good exes do { - qcsr.value = in32(OCB_QCSR); + qcsr.value = in32(G_OCB_QCSR); } while (qcsr.fields.change_in_progress); // read initial stop states - qssr.value = in32(OCB_QSSR); + qssr.value = in32(G_OCB_QSSR); PK_TRACE_DBG("Setup: CCSR[%x] QCSR[%x] QSSR[%x]", ccsr.value, qcsr.value, qssr.value); @@ -476,15 +476,15 @@ p9_sgpe_stop_init() //-------------------------------------------------------------------------- PK_TRACE_INF("Setup: Clear Type 0,2,3,6 and ipi_lo_3 interrupts"); - out32(OCB_OISR1_CLR, (BIT32(13) | BITS32(15, 2) | BIT32(19) | BIT32(29))); - out32(OCB_OPITNPRA_CLR(0), BITS32(0, 24)); - out32(OCB_OPITNPRA_CLR(1), BITS32(0, 24)); - out32(OCB_OPITNPRA_CLR(2), BITS32(0, 24)); - out32(OCB_OPITNPRA_CLR(3), BITS32(0, 24)); - out32(OCB_OPITNPRA_CLR(4), BITS32(0, 24)); - out32(OCB_OPITNPRA_CLR(5), BITS32(0, 24)); - out32(OCB_OPIT6PRB_CLR, BITS32(0, 6)); - out32(OCB_OPIT7PRB_CLR, BITS32(0, 6)); + out32(G_OCB_OISR1_CLR, (BIT32(13) | BITS32(15, 2) | BIT32(19) | BIT32(29))); + out32(G_OCB_OPIT0PRA_CLR, BITS32(0, 24)); + out32(G_OCB_OPIT1PRA_CLR, BITS32(0, 24)); + out32(G_OCB_OPIT2PRA_CLR, BITS32(0, 24)); + out32(G_OCB_OPIT3PRA_CLR, BITS32(0, 24)); + out32(G_OCB_OPIT4PRA_CLR, BITS32(0, 24)); + out32(G_OCB_OPIT5PRA_CLR, BITS32(0, 24)); + out32(G_OCB_OPIT6PRB_CLR, BITS32(0, 6)); + out32(G_OCB_OPIT7PRB_CLR, BITS32(0, 6)); #if !SKIP_CME_BOOT_IPL_HB @@ -573,7 +573,7 @@ p9_sgpe_stop_init() GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CMEDB2, cindex), 0); GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CMEDB3, cindex), 0); - if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && (in32(OCB_OCCS2) & BIT32(PGPE_PSTATE_PROTOCOL_ACTIVE))) + if ((in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) && (in32(G_OCB_OCCS2) & BIT32(PGPE_PSTATE_PROTOCOL_ACTIVE))) { GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CSAR_OR, cindex), BIT64(CPPM_CSAR_ENABLE_PSTATE_REGISTRATION_INTERLOCK)); } @@ -640,23 +640,23 @@ p9_sgpe_stop_init() #endif PK_TRACE("Configure and Enable Fit Timer"); - out32(GPE_GPE3TSEL, BIT32(4)); + out32(G_GPE_GPE3TSEL, BIT32(4)); ppe42_fit_setup((PkIrqHandler)p9_sgpe_fit_handler, 0); PK_TRACE("Clear OCC LFIR[gpe3_halted] and OISR[gpe3_error and xstop] bits upon SGPE boot"); - GPE_PUTSCOM(OCB_OCCLFIR_AND, ~BIT64(25)); - out32(OCB_OISR0_CLR, (BIT32(8) | BIT32(16))); - out32(OCB_OIMR0_CLR, (BIT32(8) | BIT32(16))); + GPE_PUTSCOM(G_OCB_OCCLFIR_AND, ~BIT64(25)); + out32(G_OCB_OISR0_CLR, (BIT32(8) | BIT32(16))); + out32(G_OCB_OIMR0_CLR, (BIT32(8) | BIT32(16))); PK_TRACE_INF("Setup: Unmask Type 0, 2,3,6 and ipi_lo_3 interrupts"); - out32(OCB_OIMR1_CLR, BIT32(13) | (BITS32(15, 2) | BIT32(19) | BIT32(29))); + out32(G_OCB_OIMR1_CLR, BIT32(13) | (BITS32(15, 2) | BIT32(19) | BIT32(29))); //-------------------------------------------------------------------------- // SGPE Init Completed //-------------------------------------------------------------------------- PK_TRACE_INF("Setup: SGPE STOP READY"); - out32(OCB_OCCFLG_OR, BIT32(SGPE_ACTIVE)); + out32(G_OCB_OCCFLG_OR, BIT32(SGPE_ACTIVE)); #if EPM_P9_TUNING asm volatile ("tw 0, 31, 0"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c index c09440d6..0a691912 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c @@ -78,9 +78,9 @@ p9_sgpe_fit_handler() { PK_TRACE("FIT: Handler Fired"); - uint32_t tpending = in32(OCB_OPITNPRA(PIG_TYPE3)) | - in32(OCB_OPITNPRA(PIG_TYPE0)) | - in32(OCB_OPIT6PRB); + uint32_t tpending = in32(G_OCB_OPIT0PRA) | + in32(G_OCB_OPIT3PRA) | + in32(G_OCB_OPIT6PRB); // reset counter if current processing stop8+ if (G_sgpe_stop_record.wof.status_stop & STATUS_STOP_PROCESSING) @@ -100,7 +100,7 @@ p9_sgpe_fit_handler() { PK_TRACE_INF("FIT: Stop8+ Stravation Detected"); G_sgpe_stop_record.fit.starve_counter = 0; - out32(OCB_OIMR1_OR, BIT32(15)); + out32(G_OCB_OIMR1_OR, BIT32(15)); g_oimr_override |= BIT64(47); } } @@ -114,11 +114,11 @@ p9_sgpe_pgpe_halt_handler(void* arg, PkIrqId irq) PkMachineContext ctx; g_oimr_override |= BIT64(7); - out32(OCB_OIMR0_OR, BIT32(7)); + out32(G_OCB_OIMR0_OR, BIT32(7)); PK_TRACE_INF("WARNING: PGPE Halted Due to Error"); PK_OPTIONAL_DEBUG_HALT(SGPE_PGPE_ERROR_DETECTED); - out32(OCB_OISR0_CLR, BIT32(7)); + out32(G_OCB_OISR0_CLR, BIT32(7)); G_sgpe_stop_record.wof.update_pgpe = IPC_SGPE_PGPE_UPDATE_PGPE_HALTED; @@ -133,11 +133,11 @@ p9_sgpe_checkstop_handler(void* arg, PkIrqId irq) PkMachineContext ctx; g_oimr_override |= BIT64(16); - out32(OCB_OIMR0_OR, BIT32(16)); + out32(G_OCB_OIMR0_OR, BIT32(16)); PK_TRACE_INF("WARNING: System Checkstop Detected"); PK_OPTIONAL_DEBUG_HALT(SGPE_SYSTEM_CHECKSTOP_DETECTED); - out32(OCB_OISR0_CLR, BIT32(16)); + out32(G_OCB_OISR0_CLR, BIT32(16)); pk_irq_vec_restore(&ctx); } @@ -345,7 +345,7 @@ p9_sgpe_pig_cpayload_parser(const uint32_t type) if (G_sgpe_stop_record.group.cack[block_index] == G_sgpe_stop_record.group.creq[block_index]) { - out32(OCB_OCCFLG_CLR, BIT32(SGPE_IGNORE_STOP_CONTROL)); + out32(G_OCB_OCCFLG_CLR, BIT32(SGPE_IGNORE_STOP_CONTROL)); } } // unblock entry/exit/both @@ -373,7 +373,7 @@ p9_sgpe_pig_cpayload_parser(const uint32_t type) G_sgpe_stop_record.group.core[block_index] = 0; G_sgpe_stop_record.group.qswu[block_index] = 0; - out32(OCB_OCCFLG_CLR, BIT32(SGPE_IGNORE_STOP_CONTROL)); + out32(G_OCB_OCCFLG_CLR, BIT32(SGPE_IGNORE_STOP_CONTROL)); } } } @@ -406,14 +406,14 @@ p9_sgpe_pig_cpayload_parser(const uint32_t type) { tpayload = in32(OCB_OPIT2CN(cindex)); - if ((in32(OCB_OPITNPRA(PIG_TYPE2)) & BIT32(cindex)) && + if ((in32(G_OCB_OPIT2PRA) & BIT32(cindex)) && (!(tpayload & TYPE2_PAYLOAD_EXIT_EVENT)) && (tpayload & TYPE2_PAYLOAD_STOP_LEVEL)) { PK_TRACE_INF("WARNING: Leftover dec wakeup following by new TYPE2 entry PIG"); cpayload = tpayload; } - else if (in32(OCB_OPITNPRA(PIG_TYPE3)) & BIT32(cindex)) + else if (in32(G_OCB_OPIT3PRA) & BIT32(cindex)) { PK_TRACE_INF("WARNING: Leftover dec wakeup following by new TYPE3 PIG"); continue; @@ -796,7 +796,7 @@ p9_sgpe_pig_thread_lanucher() { // block both type3, type0, type6 // so another doesnt interrupt until next round - out32(OCB_OIMR1_OR, (BIT32(13) | BIT32(16) | BIT32(19))); + out32(G_OCB_OIMR1_OR, (BIT32(13) | BIT32(16) | BIT32(19))); g_oimr_override |= (BIT64(45) | BIT64(48) | BIT64(51)); if ((G_sgpe_stop_record.group.core[VECTOR_PIGX]) || @@ -895,12 +895,12 @@ p9_sgpe_ipi3_low_handler(void* arg, PkIrqId irq) uint32_t req_list = 0; uint32_t qloop = 0; uint32_t action = 0; - uint32_t occflg = in32(OCB_OCCFLG) & BITS32(SGPE_IGNORE_STOP_CONTROL, 4); + uint32_t occflg = in32(G_OCB_OCCFLG) & BITS32(SGPE_IGNORE_STOP_CONTROL, 4); data64_t scom_data = {0}; PK_TRACE_INF("IPI-IRQ: %d", irq); // Clear ipi3_lo interrupt - out32(OCB_OISR1_CLR, BIT32(29)); + out32(G_OCB_OISR1_CLR, BIT32(29)); // occflg[9]control + [11]exit/[12]entry(filter bit[10] here) // bit[9] must be on to perform any operations below @@ -1019,7 +1019,7 @@ p9_sgpe_ipi3_low_handler(void* arg, PkIrqId irq) G_sgpe_stop_record.group.qswu[VECTOR_BLOCKX] = 0; } - out32(OCB_OCCFLG_CLR, BIT32(SGPE_IGNORE_STOP_CONTROL)); + out32(G_OCB_OCCFLG_CLR, BIT32(SGPE_IGNORE_STOP_CONTROL)); } if ((occflg & BIT32(SGPE_IGNORE_STOP_ENTRIES)) && @@ -1046,7 +1046,7 @@ p9_sgpe_ipi3_low_handler(void* arg, PkIrqId irq) G_sgpe_stop_record.group.qswu[VECTOR_BLOCKE] = 0; } - out32(OCB_OCCFLG_CLR, BIT32(SGPE_IGNORE_STOP_CONTROL)); + out32(G_OCB_OCCFLG_CLR, BIT32(SGPE_IGNORE_STOP_CONTROL)); } } @@ -1128,12 +1128,12 @@ p9_sgpe_pig_type6_handler(void* arg, PkIrqId irq) PK_TRACE_DBG("PIG-TYPE6: %d", irq); // Clear type6 interrupt - out32(OCB_OISR1_CLR, BIT32(19)); + out32(G_OCB_OISR1_CLR, BIT32(19)); // read type6 interrupt pending status // then clear interrupt pending status - qpending = in32(OCB_OPIT6PRB); - out32(OCB_OPIT6PRB_CLR, qpending); + qpending = in32(G_OCB_OPIT6PRB); + out32(G_OCB_OPIT6PRB_CLR, qpending); PK_TRACE("Quads Pending: %x", qpending); // clear group before analyzing input |
