PSTATE: PGPE updates for CME Registration

Change-Id: I54daa693410184b67a2c4df9029727ffca6d3b64
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41873
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

4 files changed, 33 insertions, 23 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
index 952014bd..a1c558c3 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
@@ -170,18 +170,18 @@ void p9_pgpe_irq_handler_pcb_type1(void* arg, PkIrqId irq)
     ocb_opit1cn_t opit1cn;
     uint32_t c;
     uint32_t coresPendPSReq = 0;
-    uint32_t opit4pra;
+    uint32_t opit1pra;
 
     //Incrementally build a snapshot of core requests
-    opit4pra = in32(OCB_OPIT1PRA);
-    coresPendPSReq = opit4pra;
+    opit1pra = in32(OCB_OPIT1PRA);
+    coresPendPSReq = opit1pra;
 
     //Keep looping until no more core requests
-    while(opit4pra)
+    while(opit1pra)
     {
-        out32(OCB_OPIT1PRA_CLR, opit4pra);
-        coresPendPSReq |= opit4pra;
-        opit4pra = in32(OCB_OPIT1PRA);
+        out32(OCB_OPIT1PRA_CLR, opit1pra);
+        coresPendPSReq |= opit1pra;
+        opit1pra = in32(OCB_OPIT1PRA);
     }
 
     if (G_pgpe_pstate_record.pstatesStatus == PSTATE_ACTIVE &&
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 084fde9e..05e1ed7d 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -66,12 +66,12 @@ void p9_pgpe_suspend_stop_callback(ipc_msg_t* msg, void* arg);
 void p9_pgpe_pstate_init()
 {
     uint32_t q;
-    ocb_qcsr_t qcsr;
-    qcsr.value = in32(OCB_QCSR);
 
     G_pgpe_pstate_record.pstatesStatus = PSTATE_INIT;
     G_pgpe_pstate_record.wofEnabled = 0;
     G_pgpe_pstate_record.wofPending = 0;
+    G_pgpe_pstate_record.quadsActive =
+        0;//We only mark qCME active upon a registration msg whether before or after PGPE boot
 
     for (q = 0; q < MAX_QUADS; q++)
     {
@@ -85,12 +85,6 @@ void p9_pgpe_pstate_init()
         G_pgpe_pstate_record.globalPSCurr  = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
         G_pgpe_pstate_record.quadPSNext[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
         G_pgpe_pstate_record.globalPSNext  = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
-
-        //Set quads active equal to configured quads
-        if (qcsr.fields.ex_config & (0xC00 >> (q << 1)))
-        {
-            G_pgpe_pstate_record.quadsActive |= (0x80 >> q);
-        }
     }
 
     G_pgpe_pstate_record.pQuadState0 = (quad_state0_t*)G_pgpe_header_data->g_quad_status_addr;
@@ -1162,6 +1156,28 @@ void p9_pgpe_pstate_stop()
     PK_TRACE_DBG("Stop Done");
 }
 
+void p9_pgpe_pstate_setup_process_pcb_type4()
+{
+    uint32_t opit4pr, q, opit4prQuad;
+    opit4pr = in32(OCB_OPIT4PRA); //Read current opit4pr
+
+    for (q = 0; q < MAX_QUADS; q++)
+    {
+        opit4prQuad = (opit4pr >> ((MAX_QUADS - q + 1) << 2)) & 0xf;
+
+        if (opit4prQuad)
+        {
+            G_pgpe_pstate_record.quadsActive |= (0x80 >> q);
+            PK_TRACE_DBG("Quad %x Registered at boot\n", q);
+        }
+    }
+
+    //Enable PCB_INTR_TYPE4
+    out32(OCB_OPIT4PRA_CLR, opit4pr);
+    out32(OCB_OISR1_CLR, BIT32(17));
+    g_oimr_override &= ~BIT64(49);
+    out32(OCB_OIMR1_CLR, BIT32(17));
+}
 
 void p9_pgpe_pstate_updt_actual_quad(uint32_t q)
 {
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.h
index 15387ff3..afb269e3 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.h
@@ -138,5 +138,6 @@ void p9_pgpe_pstate_process_quad_entry(uint32_t quadsAffected);
 void p9_pgpe_pstate_process_quad_exit(uint32_t quadsAffected);
 void p9_pgpe_pstate_start(uint32_t pstate_start_origin);
 void p9_pgpe_pstate_stop();
+void p9_pgpe_pstate_setup_process_pcb_type4();
 void p9_pgpe_pstate_updt_actual_quad(uint32_t q);
 #endif //
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
index c885f735..99cac9c1 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
@@ -82,14 +82,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
         p9_pgpe_pstate_start(PSTATE_START_OCC_FLAG);
     }
 
-    //Enable PCB_INTR_TYPE4
-    uint32_t opit4pr;
-    opit4pr = in32(OCB_OPIT4PRA);
-    out32(OCB_OPIT4PRA_CLR, opit4pr);
-    out32(OCB_OISR1_CLR, BIT32(17));
-    g_oimr_override &= ~BIT64(49);
-    out32(OCB_OIMR1_CLR, BIT32(17));
-
+    p9_pgpe_pstate_setup_process_pcb_type4(); //Setup pcb_type4 and check for qCME registration
 
     // Set OCC Scratch2[PGPE_ACTIVE]
     uint32_t occScr2 = in32(OCB_OCCS2);