diff options
| author | Yue Du <daviddu@us.ibm.com> | 2017-02-09 17:07:44 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:12:25 -0500 |
| commit | 5236343c0ffb914e3434430d7ce3a2fff9a562cb (patch) | |
| tree | d26430f09689e2891dece4a2117437e402db71d0 | |
| parent | 7d0ced5efbe69cba7092d5e2055979ec66a628c1 (diff) | |
| download | talos-hcode-5236343c0ffb914e3434430d7ce3a2fff9a562cb.tar.gz talos-hcode-5236343c0ffb914e3434430d7ce3a2fff9a562cb.zip | |
Hcode: Create centralized memory map headers
findings and todos:
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
redundant cpmr linker
not sure which one is in use
cme/link.cmd
cme/linkcpmr.cmd
cme/stop_cme/link_cpmr.cmd
sgpe/stop_gpe/link.cmd
sgpe/stop_gpe/linkqpmr.cmd
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
redundant asm of cpmr and qpmr headers:
not sure which one is in use
file names are inconsistant and confusing
cme/p9_cpmr_header.S
cme/stop_cme/p9_cme_cpmr.S
cme/stop_cme/p9_cme_header.S
sgpe/p9_sgpe_qpmr.S
sgpe/stop_gpe/p9_sgpe_qpmr.S
sgpe/stop_gpe/p9_sgpe_image_header.S
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
redundant edit programs
not sure which ones are still useful
contents are overlapping and out updated
(i.e. cme one still try to edit build date/ver)
cme/p9_cpmr_img_edit.C
cme/stop_cme/p9_cme_img_edit.c
cme/stop_cme/p9_cme_edit.mk
sgpe/p9_sgpe_img_edit.c
sgpe/stop_gpe/p9_sgpe_img_edit.c
sgpe/stop_gpe/p9_sgpe_edit.mk
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
previous local makefiles
not sure if still useful
optional to keep or delete
cme/Makefile
cme/img_defs.mk
sgpe/Makefile
sgpe/img_defs.mk
sgpe/stop_gpe/Makefile
sgpe/stop_gpe/img_defs.mk
sgpe/boot/Makefile
sgpe/boot/img_defs.mk
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
Change-Id: I94fbd28fc3e3c125e43232ea556a4e70b293db6d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36253
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
47 files changed, 1051 insertions, 724 deletions
diff --git a/import/chips/p9/common/pmlib/include/cmehw_common.h b/import/chips/p9/common/pmlib/include/cmehw_common.h index 51b0f4d4..65abb697 100644 --- a/import/chips/p9/common/pmlib/include/cmehw_common.h +++ b/import/chips/p9/common/pmlib/include/cmehw_common.h @@ -31,14 +31,6 @@ #define in32_sh(addr) in32(addr+4) #define out32_sh(addr, data) out32(addr+4, data) -/// CME Core Related Configuration - -enum CME_CORE_CONFIGS -{ - MAX_THREADS_PER_CORE = 4, - MAX_CORES_PER_CME = 2 -}; - /// Core Masks enum CME_CORE_MASKS diff --git a/import/chips/p9/common/pmlib/include/p9_stop_common.h b/import/chips/p9/common/pmlib/include/p9_stop_common.h index 0206360a..c2da418a 100644 --- a/import/chips/p9/common/pmlib/include/p9_stop_common.h +++ b/import/chips/p9/common/pmlib/include/p9_stop_common.h @@ -130,22 +130,3 @@ enum P9_STOP_STATE_HISTORY_BIT_MASK SSH_REQ_ENABLE = BIT32(12), SSH_ACT_ENABLE = BIT32(13) }; - -/// Homer Layout -enum P9_HOMER_REGION_CONSTANTS -{ - OCC_SRAM_BASE = 0xFFF00000, - SGPE_IMAGE_SRAM_BASE = 0xFFF30000, - SGPE_HEADER_IMAGE_OFFSET = 0x180, - CME_SRAM_BASE = 0xFFFF8000, - // QPMR_BASE (HOMER_BASE + 1MB) - QPMR_BASE_HOMER_OFFSET = 0x100000, - // CPMR_BASE (HOMER_BASE + 2MB) - CPMR_BASE_HOMER_OFFSET = 0x200000, - // CME_IMAGE_BASE (CPMR_BASE + 6KB + 256KB(8KB + 256B(~56KB) + 192KB)) - CME_IMAGE_CPMR_OFFSET = 0x41800, - // CME_HEADER_BASE (CME_IMAGE_BASE + 384B) - CME_HEADER_IMAGE_OFFSET = 0x180, - // CME_BCE_IRR_HOMER_BASE (HOMER_BASE + 3MB - 128B) - CME_BCE_IRR_HOMER_OFFSET = 0x2FFF80 -}; diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_header_defs.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_header_defs.H index 25fe03e2..4197ca2e 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_header_defs.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_header_defs.H @@ -23,8 +23,8 @@ /* */ /* IBM_PROLOG_END_TAG */ /// -/// @file p9_occ_sram_defs.H -/// @brief Constants defining the layout of the OCC SRAM +/// @file p9_hcd_header_defs.H +/// @brief defines header constants based on file types /// /// This header contains those cpp manifest constants required for processing /// the linker scripts used to generate OCC code images. As these are used @@ -32,11 +32,12 @@ /// into a namespace. Prefixing these with the region name is the attempt /// to make these globally unique when this header is included in C++ code. /// -// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner: Prem Jha <premjha2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 2 -// *HWP Consumed by: PM +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM // #ifndef __HCD_HEADER_DEFS_H__ @@ -103,54 +104,49 @@ .endm // *INDENT-ON* -#undef CONST_UINT8_T -#undef CONST_UINT32_T -#undef CONST_UINT64_T - -#define CONST_UINT8_T(name, expr) .set name, expr -#define CONST_UINT16_T(name, expr) .set name, expr -#define CONST_UINT32_T(name, expr) .set name, expr -#define CONST_UINT64_T(name, expr) .set name, expr - #define ULL(x) x +#define HCD_CONST(name, expr) .set name, expr; +#define HCD_CONST64(name, expr) .set name, expr; #define HCD_HDR_UINT64(symbol, value) hcd_header_uint64 symbol value #define HCD_HDR_UINT32(symbol, value) hcd_header_uint32 symbol value #define HCD_HDR_UINT16(symbol, value) hcd_header_uint16 symbol value #define HCD_HDR_UINT8(symbol, value) hcd_header_uint8 symbol value #define HCD_HDR_UINT8_VEC(symbol, number, value) hcd_header_uint8_vec symbol number value - -#define HCD_HDR_ATTN(symbol, number) hcd_header_attn symbol number +#define HCD_HDR_ATTN(symbol, number) hcd_header_attn symbol number #define HCD_HDR_ATTN_PAD(align) hcd_header_attn_pad align #define HCD_HDR_PAD(align) hcd_header_pad align -#define HCD_MAGIC_NUMBER(symbol, value) .set symbol, value -#else // __ASSEMBLER__ +#else // NOT __ASSEMBLER__ -#undef CONST_UINT8_T -#undef CONST_UINT32_T -#undef CONST_UINT64_T +#ifdef __LINKERSCRIPT__ -#define CONST_UINT8_T(name, expr) static const uint8_t name = expr; -#define CONST_UINT16_T(name, expr) static const uint16_t name = expr; -#define CONST_UINT32_T(name, expr) static const uint32_t name = expr; -#define CONST_UINT64_T(name, expr) static const uint64_t name = expr; + #define ULL(x) x + #define POUND_DEFINE #define + #define HCD_CONST(name, expr) POUND_DEFINE name expr + #define HCD_CONST64(name, expr) POUND_DEFINE name expr -#define ULL(x) x##ull +#else -#define HCD_HDR_UINT64(symbol, value) uint64_t symbol -#define HCD_HDR_UINT32(symbol, value) uint32_t symbol -#define HCD_HDR_UINT16(symbol, value) uint16_t symbol -#define HCD_HDR_UINT8(symbol, value) uint8_t symbol -#define HCD_HDR_UINT8_VEC(symbol, number, value) uint8_t symbol[number] -#define HCD_HDR_ATTN(symbol, number) uint32_t symbol[number] -#define HCD_HDR_ATTN_PAD(align) -#define HCD_HDR_PAD(align) -#define HCD_MAGIC_NUMBER(symbol, value) static const uint64_t symbol = value + #define ULL(x) x##ull + #define HCD_CONST(name, expr) enum { name = expr }; + #define HCD_CONST64(name, expr) enum { name = expr }; + #define HCD_HDR_UINT64(symbol, value) uint64_t symbol + #define HCD_HDR_UINT32(symbol, value) uint32_t symbol + #define HCD_HDR_UINT16(symbol, value) uint16_t symbol + #define HCD_HDR_UINT8(symbol, value) uint8_t symbol + #define HCD_HDR_UINT8_VEC(symbol, number, value) uint8_t symbol[number] + #define HCD_HDR_ATTN(symbol, number) uint32_t symbol[number] + #define HCD_HDR_ATTN_PAD(align) + #define HCD_HDR_PAD(align) + +#endif // __LINKERSCRIPT__ #endif // __ASSEMBLER__ +// Stringification + #define STR_HELPER(x) #x #define STR(x) STR_HELPER(x) -#endif // __HCD_HEADER_DEFS_H__ +#endif // __HCD_HEADER_DEFS_H__ diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H new file mode 100644 index 00000000..419e4779 --- /dev/null +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -0,0 +1,480 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_base.H +/// @brief defines region constants shared by different memory components. +/// + +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot:Phyp + +#ifndef __HCD_MEMMAP_BASE_H__ +#define __HCD_MEMMAP_BASE_H__ + +#include <p9_hcd_header_defs.H> + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +// ------------------------------------------------------------------- + +/// Image Magic Numbers + +HCD_CONST64(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)) // CPMR_1.0 +HCD_CONST64(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)) // CME__1.0 + +HCD_CONST64(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)) // QPMR_1.0 +HCD_CONST64(SGPE_MAGIC_NUMBER, ULL(0x534750455f312e30)) // SGPE_1.0 + +HCD_CONST64(PPMR_MAGIC_NUMBER, ULL(0x50504d525f312e30)) // PPMR_1.0 +HCD_CONST64(PGPE_MAGIC_NUMBER, ULL(0x504750455F312E30)) // PGPE_1.0 + +HCD_CONST(CME_BUILD_VERSION, 0x001) // CME__1.0 +HCD_CONST(SGPE_BUILD_VERSION, 0x001) // SGPE_1.0 +HCD_CONST(PGPE_BUILD_VERSION, 0x001) // PGPE_1.0 + +/// Size constants + +HCD_CONST(HALF_KB, 512) +HCD_CONST(ONE_KB, 1024) +HCD_CONST(HALF_MB, (1024 * 512)) +HCD_CONST(ONE_MB, (1024 * 1024)) +HCD_CONST(TWO_MB, (2 * 1024 * 1024)) + +/// Memory constants + +HCD_CONST(CME_SRAM_SIZE, (32 * ONE_KB)) +HCD_CONST(OCC_SRAM_SIZE, (768 * ONE_KB)) + +HCD_CONST(HOMER_MEMORY_SIZE, (4 * ONE_MB)) +HCD_CONST(HOMER_OPMR_REGION_NUM, 0) +HCD_CONST(HOMER_QPMR_REGION_NUM, 1) +HCD_CONST(HOMER_CPMR_REGION_NUM, 2) +HCD_CONST(HOMER_PPMR_REGION_NUM, 3) + +/// Chip constants + +HCD_CONST(MAX_THREADS_PER_CORE, 4) +HCD_CONST(MAX_CORES_PER_CHIP, 24) + +HCD_CONST(MAX_CMES_PER_CHIP, 12) +HCD_CONST(MAX_EXES_PER_CHIP, 12) + +HCD_CONST(MAX_QUADS_PER_CHIP, 6) +HCD_CONST(MAX_CACHES_PER_CHIP, 6) + +HCD_CONST(MAX_CORES_PER_CME, 2) +HCD_CONST(MAX_CORES_PER_EX, 2) + +HCD_CONST(MAX_CMES_PER_QUAD, 2) +HCD_CONST(MAX_EXES_PER_QUAD, 2) + +HCD_CONST(CACHE0_CHIPLET_ID, 0x10) +HCD_CONST(CACHE_CHIPLET_ID_MIN, 0x10) +HCD_CONST(CACHE_CHIPLET_ID_MAX, 0x15) + +HCD_CONST(CORE0_CHIPLET_ID, 0x20) +HCD_CONST(CORE_CHIPLET_ID_MIN, 0x20) +HCD_CONST(CORE_CHIPLET_ID_MAX, 0x37) + +HCD_CONST(MAX_QUAD_ID_SUPPORTED, 5) +HCD_CONST(MAX_CORE_ID_SUPPORTED, 23) +HCD_CONST(MAX_THREAD_ID_SUPPORTED, 3) + +/// Image build constants + +HCD_CONST(HARDWARE_IMG_SIZE, ONE_MB) + +HCD_CONST(FUSED_CORE_MODE, 0xBB) +HCD_CONST(NONFUSED_CORE_MODE, 0xAA) + +HCD_CONST(SELF_RESTORE_BLR_INST, 0x4e800020) +HCD_CONST(CORE_RESTORE_PAD_OPCODE, 0x00000200) //ATTN Opcode + +HCD_CONST(SCOM_RESTORE_PAD_OPCODE, 0x00000000) //zero pads +HCD_CONST(SCOM_RESTORE_ENTRY_SIZE, 16) //4B pad,4B address,8B data + +HCD_CONST(CME_BLOCK_READ_LEN, 32) +HCD_CONST(CME_BLK_SIZE_SHIFT, 0x05) + +HCD_CONST(RING_ALIGN_BOUNDARY, 0x08) +HCD_CONST64(DARN_BAR_EN_POS, ULL(0x8000000000000000)) + +//--------------------------------------------------------------------------------------- + +/// OPMR + +HCD_CONST(OCC_HOST_AREA_SIZE, ONE_MB) +HCD_CONST(OPMR_OCC_IMAGE_SIZE, HALF_MB) +HCD_CONST(OPMR_HOST_AREA_SIZE, HALF_MB) + +//--------------------------------------------------------------------------------------- + +/// QPMR Header + +HCD_CONST(QPMR_HOMER_OFFSET, (HOMER_QPMR_REGION_NUM* ONE_MB)) +HCD_CONST(QPMR_HEADER_SIZE, 512) + +HCD_CONST(QPMR_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(QPMR_BOOT_COPIER_OFFSET_BYTE, 0x08) +HCD_CONST(QPMR_BOOT_LOADER_OFFSET_BYTE, 0x10) +HCD_CONST(QPMR_BOOT_LOADER_LENGTH_BYTE, 0x14) +HCD_CONST(QPMR_BUILD_DATE_BYTE, 0x18) +HCD_CONST(QPMR_BUILD_VER_BYTE, 0x1C) +HCD_CONST(QPMR_SGPE_HCODE_OFFSET_BYTE, 0x28) +HCD_CONST(QPMR_SGPE_HCODE_LENGTH_BYTE, 0x2C) +HCD_CONST(QPMR_QUAD_COMMON_RINGS_OFFSET_BYTE, 0x30) +HCD_CONST(QPMR_QUAD_COMMON_RINGS_LENGTH_BYTE, 0x34) +HCD_CONST(QPMR_QUAD_OVERRIDE_RINGS_OFFSET_BYTE, 0x38) +HCD_CONST(QPMR_QUAD_OVERRIDE_RINGS_LENGTH_BYTE, 0x3C) +HCD_CONST(QPMR_QUAD_SPECIFIC_RINGS_OFFSET_BYTE, 0x40) +HCD_CONST(QPMR_QUAD_SPECIFIC_RINGS_LENGTH_BYTE, 0x44) +HCD_CONST(QPMR_QUAD_SCOM_RESTORE_OFFSET_BYTE, 0x48) +HCD_CONST(QPMR_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x4C) +HCD_CONST(QPMR_24x7_DATA_OFFSET_BYTE, 0x50) +HCD_CONST(QPMR_24x7_DATA_LENGTH_BYTE, 0x54) +HCD_CONST(QPMR_STOP_FFDC_OFFSET_BYTE, 0x58) +HCD_CONST(QPMR_STOP_FFDC_LENGTH_BYTE, 0x5C) + +/// SGPE Boot + +HCD_CONST(SGPE_BOOT_COPIER_QPMR_OFFSET, QPMR_HEADER_SIZE) +HCD_CONST(SGPE_BOOT_COPIER_SIZE, ONE_KB) + +HCD_CONST(SGPE_BOOT_LOADER_QPMR_OFFSET, + (SGPE_BOOT_COPIER_QPMR_OFFSET + SGPE_BOOT_COPIER_SIZE)) +HCD_CONST(SGPE_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(SGPE_BOOT_LOADER_RESET_ADDR_VAL, 0x40) + +HCD_CONST(SGPE_INSTRUMENTATION_SIZE, (2 * ONE_KB)) + +/// SGPE Image + +HCD_CONST(SGPE_IMAGE_QPMR_OFFSET, + (SGPE_BOOT_LOADER_QPMR_OFFSET + SGPE_BOOT_LOADER_SIZE)) +HCD_CONST(SGPE_IMAGE_SIZE, (80 * ONE_KB)) +HCD_CONST(SGPE_INT_VECTOR_SIZE, 384) +HCD_CONST(SGPE_HCODE_RESET_ADDR_VAL, 0x40) + +/// SGPE Header + +HCD_CONST(SGPE_HEADER_QPMR_OFFSET, + (SGPE_IMAGE_QPMR_OFFSET + SGPE_INT_VECTOR_SIZE)) +HCD_CONST(SGPE_HEADER_IMAGE_OFFSET, SGPE_INT_VECTOR_SIZE) +HCD_CONST(SGPE_HEADER_SIZE, 128) + +HCD_CONST(SGPE_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(SGPE_SYSTEM_RESET_ADDR_BYTE, 0x08) +HCD_CONST(SGPE_IVPR_ADDR_BYTE, 0x10) +HCD_CONST(SGPE_BUILD_DATE_BYTE, 0x18) +HCD_CONST(SGPE_BUILD_VER_BYTE, 0x1C) +HCD_CONST(SGPE_STOP_FLAGS_BYTE, 0x20) +HCD_CONST(SGPE_LOCATION_ID_BYTE, 0x24) +HCD_CONST(SGPE_QUAD_COMMON_RING_SRAM_OFF_BYTE, 0x28) +HCD_CONST(SGPE_QUAD_OVERRIDE_RING_SRAM_OFF_BYTE, 0x2C) +HCD_CONST(SGPE_QUAD_SPECIFIC_RING_SRAM_OFF_BYTE, 0x30) +HCD_CONST(SGPE_QUAD_SCOM_RESTORE_SRAM_OFF_BYTE, 0x34) +HCD_CONST(SGPE_QUAD_SCOM_RESTORE_MEM_OFF_BYTE, 0x38) +HCD_CONST(SGPE_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x3C) +HCD_CONST(SGPE_24x7_DATA_OFFSET_BYTE, 0x40) +HCD_CONST(SGPE_24x7_DATA_LENGTH_BYTE, 0x44) +HCD_CONST(PGPE_24x7_CTRL_BYTE, 0x48) + +HCD_CONST(SGPE_RESET_ADDR_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_SYSTEM_RESET_ADDR_BYTE)) +HCD_CONST(SGPE_BUILD_DATE_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_DATE_BYTE)) +HCD_CONST(SGPE_BUILD_VER_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_VER_BYTE)) + +HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000) +HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000) +HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000) +HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) +HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS, 0x00008000) + +/// SGPE Hcode + +HCD_CONST(SGPE_HCODE_IMAGE_OFFSET, (SGPE_INT_VECTOR_SIZE + SGPE_HEADER_SIZE)) +HCD_CONST(SGPE_HCODE_SIZE, ((45 * ONE_KB) + HALF_KB)) //RTC158543 +HCD_CONST(SGPE_DEBUG_PTRS_OFFSET, 0x200) +HCD_CONST(SGPE_DEBUG_PTRS_SIZE, 0x24) +HCD_CONST(SGPE_DBG_PTR_AREA_SIZE, 64) + +/// Quad Scan + +// 400B * 9 rings * 3 types (base, RL, CC) +HCD_CONST(QUAD_COMMON_RING_SIZE, (13 * ONE_KB)) +// 300B * 9 rings +HCD_CONST(QUAD_OVERRIDE_RING_SIZE, (3 * ONE_KB)) +// 1KB/ring * 5 rings/cache +HCD_CONST(QUAD_SPECIFIC_RING_SIZE_PER_QUAD, ((3 * ONE_KB) + HALF_KB)) +HCD_CONST(QUAD_SPECIFIC_RING_SIZE_TOTAL, (19 * ONE_KB)) //checkme? + +/// Quad Scom + +HCD_CONST(QUAD_SCOM_RESTORE_QPMR_OFFSET, (128 * ONE_KB)) +HCD_CONST(QUAD_SCOM_RESTORE_HOMER_OFFSET, + (QUAD_SCOM_RESTORE_QPMR_OFFSET + QPMR_HOMER_OFFSET)) + +HCD_CONST(MAX_L2_SCOM_ENTRIES, 16) +HCD_CONST(MAX_L3_SCOM_ENTRIES, 16) +HCD_CONST(MAX_EQ_SCOM_ENTRIES, 15) +HCD_CONST(QUAD_SCOM_RESTORE_REGS_PER_QUAD, + (MAX_EQ_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES + 1)) + +HCD_CONST(QUAD_SCOM_RESTORE_SIZE_PER_QUAD, + (SCOM_RESTORE_ENTRY_SIZE* QUAD_SCOM_RESTORE_REGS_PER_QUAD)) + +HCD_CONST(QUAD_SCOM_RESTORE_SIZE_TOTAL, (6 * ONE_KB)) //rounded to 6KB + +//--------------------------------------------------------------------------------------- + +/// CPMR Header + +HCD_CONST(CPMR_HOMER_OFFSET, (HOMER_CPMR_REGION_NUM* ONE_MB)) +HCD_CONST(CPMR_HEADER_SIZE, 256) + +HCD_CONST(CPMR_ATTN_WORD0_BYTE, 0x00) +HCD_CONST(CPMR_ATTN_WORD1_BYTE, 0x04) +HCD_CONST(CPMR_MAGIC_NUMBER_BYTE, 0x08) +HCD_CONST(CPMR_BUILD_DATE_BYTE, 0x10) +HCD_CONST(CPMR_BUILD_VER_BYTE, 0x14) +HCD_CONST(CPMR_CME_HCODE_OFFSET_BYTE, 0x20) +HCD_CONST(CPMR_CME_HCODE_LENGTH_BYTE, 0x24) +HCD_CONST(CPMR_CORE_COMMON_RING_OFFSET_BYTE, 0x28) +HCD_CONST(CPMR_CORE_COMMON_RING_LENGTH_BYTE, 0x2C) +HCD_CONST(CPMR_CME_LOCAL_PSTATE_OFFSET_BYTE, 0x30) +HCD_CONST(CPMR_CME_LOCAL_PSTATE_LENGTH_BYTE, 0x34) +HCD_CONST(CPMR_CORE_SPECIFIC_RING_OFFSET_BYTE, 0x38) +HCD_CONST(CPMR_CORE_SPECIFIC_RING_LENGTH_BYTE, 0x3C) +HCD_CONST(CPMR_CORE_SCOM_RESTORE_OFFSET_BYTE, 0x40) +HCD_CONST(CPMR_CORE_SCOM_RESTORE_LENGTH_BYTE, 0x44) +HCD_CONST(CPMR_SELF_RESTORE_OFFSET_BYTE, 0x48) +HCD_CONST(CPMR_SELF_RESTORE_LENGTH_BYTE, 0x4C) + +/// Self Restore + +HCD_CONST(SELF_RESTORE_CPMR_OFFSET, CPMR_HEADER_SIZE) +HCD_CONST(SELF_RESTORE_INT_SIZE, (8 * ONE_KB)) +HCD_CONST(THREAD_LAUNCHER_SIZE, 256) +HCD_CONST(SELF_RESTORE_CODE_SIZE, + (SELF_RESTORE_INT_SIZE + THREAD_LAUNCHER_SIZE)) + +HCD_CONST(CORE_RESTORE_THREAD_AREA_SIZE, (ONE_KB)) +HCD_CONST(CORE_RESTORE_CORE_AREA_SIZE, (ONE_KB)) +HCD_CONST(CORE_RESTORE_SIZE_PER_THREAD, + (CORE_RESTORE_THREAD_AREA_SIZE + CORE_RESTORE_CORE_AREA_SIZE)) +HCD_CONST(SELF_RESTORE_CORE_REGS_SIZE, + (CORE_RESTORE_SIZE_PER_THREAD* + MAX_THREADS_PER_CORE* MAX_CORES_PER_CHIP)) + +HCD_CONST(SELF_RESTORE_SIZE_TOTAL, + (SELF_RESTORE_CODE_SIZE + SELF_RESTORE_CORE_REGS_SIZE)) + + +/// Core Scom + +HCD_CONST(CORE_SCOM_RESTORE_CPMR_OFFSET, (256 * ONE_KB)) +HCD_CONST(CORE_SCOM_RESTORE_HOMER_OFFSET, + (CORE_SCOM_RESTORE_CPMR_OFFSET + CPMR_HOMER_OFFSET)) + +HCD_CONST(MAX_CORE_SCOM_ENTRIES, 15) +HCD_CONST(CORE_SCOM_RESTORE_REGS_PER_CORE, (MAX_CORE_SCOM_ENTRIES + 1)) + +HCD_CONST(CORE_SCOM_RESTORE_SIZE_PER_CORE, + (SCOM_RESTORE_ENTRY_SIZE* CORE_SCOM_RESTORE_REGS_PER_CORE)) // 16*16=256 +HCD_CONST(CORE_SCOM_RESTORE_SIZE_PER_CME, + (CORE_SCOM_RESTORE_SIZE_PER_CORE* MAX_CORES_PER_CME)) // 256*2=512 + +HCD_CONST(CORE_SCOM_RESTORE_SIZE_TOTAL, + (CORE_SCOM_RESTORE_SIZE_PER_CME* MAX_CMES_PER_CHIP)) // 512*12=6K + +/// CME Image + +HCD_CONST(CME_IMAGE_CPMR_OFFSET, + (CORE_SCOM_RESTORE_CPMR_OFFSET + CORE_SCOM_RESTORE_SIZE_TOTAL)) +//HCD_CONST(CME_IMAGE_SIZE, 0) +HCD_CONST(CME_INT_VECTOR_SIZE, 384) + +/// CME Header + +HCD_CONST(CME_HEADER_CPMR_OFFSET, + (CME_IMAGE_CPMR_OFFSET + CME_INT_VECTOR_SIZE)) +HCD_CONST(CME_HEADER_IMAGE_OFFSET, CME_INT_VECTOR_SIZE) +HCD_CONST(CME_HEADER_SIZE, 128) + +HCD_CONST(CME_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(CME_HCODE_OFFSET_BYTE, 0x08) +HCD_CONST(CME_HCODE_LENGTH_BYTE, 0x0C) +HCD_CONST(CME_CORE_COMMON_RING_OFFSET_BYTE, 0x10) +HCD_CONST(CME_CORE_OVERRIDE_RING_OFFSET_BYTE, 0x14) +HCD_CONST(CME_CORE_COMMON_RING_LENGTH_BYTE, 0x18) +HCD_CONST(CME_LOCAL_PSTATE_OFFSET_BYTE, 0x1C) +HCD_CONST(CME_LOCAL_PSTATE_LENGTH_BYTE, 0x20) +HCD_CONST(CME_CORE_SPECIFIC_RING_OFFSET_BYTE, 0x24) +HCD_CONST(CME_CORE_SPECIFIC_RING_LENGTH_BYTE, 0x28) +HCD_CONST(CME_CORE_SCOM_RESTORE_OFFSET_BYTE, 0x2C) +HCD_CONST(CME_CORE_SCOM_RESTORE_LENGTH_BYTE, 0x30) +HCD_CONST(CME_STOP_FLAGS_BYTE, 0x34) +HCD_CONST(CME_LOCATION_ID_BYTE, 0x38) +HCD_CONST(CME_QM_FLAGS_BYTE, 0x3A) +HCD_CONST(CME_HOMER_ADDRESS_BYTE, 0x40) + +HCD_CONST(CME_HCODE_OFF_IMAGE_OFFSET, (CME_HEADER_IMAGE_OFFSET + CME_HCODE_OFFSET_BYTE)) +HCD_CONST(CME_HCODE_LEN_IMAGE_OFFSET, (CME_HEADER_IMAGE_OFFSET + CME_HCODE_LENGTH_BYTE)) + +HCD_CONST(CME_STOP_3_TO_2_BIT_POS, 0x80000000) +HCD_CONST(CME_STOP_4_TO_2_BIT_POS, 0x40000000) +HCD_CONST(CME_STOP_5_TO_4_BIT_POS, 0x20000000) +HCD_CONST(CME_STOP_8_TO_5_BIT_POS, 0x10000000) +HCD_CONST(CME_STOP_11_TO_8_BIT_POS, 0x08000000) +HCD_CONST(CME_SKIP_CORE_POWEROFF_BIT_POS, 0x00000001) + +/// CME Hcode + +HCD_CONST(CME_HCODE_IMAGE_OFFSET, (CME_INT_VECTOR_SIZE + CME_HEADER_SIZE)) +//HCD_CONST(CME_HCODE_SIZE, 0) +HCD_CONST(CME_DEBUG_PTRS_OFFSET, 0x200) +HCD_CONST(CME_DEBUG_PTRS_SIZE, 0x24) +HCD_CONST(CME_INSTRUMENTATION_SIZE, HALF_KB) +HCD_CONST(CME_SRAM_HCODE_OFFSET, 0) + +/// Core Scan + +HCD_CONST(CORE_COMMON_RING_SIZE, (2 * ONE_KB)) +HCD_CONST(CORE_OVERRIDE_RING_SIZE, (1 * ONE_KB)) +HCD_CONST(CORE_SPECIFIC_RING_SIZE_PER_CORE, (1 * ONE_KB)) +HCD_CONST(CORE_SPECIFIC_RING_SIZE_TOTAL, (32 * ONE_KB)) // rounded to 32K + +/// Quad P-State + +HCD_CONST(CME_QUAD_PSTATE_SIZE, HALF_KB) + +// CME Hcode + Core Scan + Pstate + +HCD_CONST(CME_REGION_SIZE, (64 * ONE_KB)) + +//--------------------------------------------------------------------------------------- + +/// PPMR Header + +HCD_CONST(PPMR_HOMER_OFFSET, (HOMER_PPMR_REGION_NUM* ONE_MB)) +HCD_CONST(PPMR_HEADER_SIZE, 512) + +HCD_CONST(PPMR_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(PPMR_BOOT_COPIER_OFFSET_BYTE, 0x08) +HCD_CONST(PPMR_BOOT_LOADER_OFFSET_BYTE, 0x10) +HCD_CONST(PPMR_BOOT_LOADER_LENGTH_BYTE, 0x14) +HCD_CONST(PPMR_BUILD_DATE_BYTE, 0x18) +HCD_CONST(PPMR_BUILD_VER_BYTE, 0x1C) +HCD_CONST(PPMR_PGPE_HCODE_OFFSET_BYTE, 0x28) +HCD_CONST(PPMR_PGPE_HCODE_LENGTH_BYTE, 0x2C) +HCD_CONST(PPMR_GLOBAL_PSTATE_OFFSET_BYTE, 0x30) +HCD_CONST(PPMR_GLOBAL_PSTATE_LENGTH_BYTE, 0x34) +HCD_CONST(PPMR_LOCAL_PSTATE_OFFSET_BYTE, 0x38) +HCD_CONST(PPMR_LOCAL_PSTATE_LENGTH_BYTE, 0x3C) +HCD_CONST(PPMR_OCC_PSTATE_OFFSET_BYTE, 0x40) +HCD_CONST(PPMR_OCC_PSTATE_LENGTH_BYTE, 0x44) +HCD_CONST(PPMR_PSTATE_TABLE_OFFSET_BYTE, 0x48) +HCD_CONST(PPMR_PSTATE_TABLE_LENGTH_BYTE, 0x4C) +HCD_CONST(PPMR_PGPE_SRAM_IMAGE_SIZE_BYTE, 0x50) +HCD_CONST(PPMR_PGPE_BOOT_PROG_CODE_BYTE, 0x54) + +/// PGPE Boot + +HCD_CONST(PGPE_BOOT_COPIER_PPMR_OFFSET, PPMR_HEADER_SIZE) +HCD_CONST(PGPE_BOOT_COPIER_SIZE, ONE_KB) + +HCD_CONST(PGPE_BOOT_LOADER_PPMR_OFFSET, + (PGPE_BOOT_COPIER_PPMR_OFFSET + PGPE_BOOT_COPIER_SIZE)) +HCD_CONST(PGPE_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(PGPE_BOOT_LOADER_RESET_ADDR_VAL, 0x40) + +HCD_CONST(PGPE_INSTRUMENTATION_SIZE, (2 * ONE_KB)) + +/// PGPE Image + +HCD_CONST(PGPE_IMAGE_PPMR_OFFSET, + (PGPE_BOOT_LOADER_PPMR_OFFSET + PGPE_BOOT_LOADER_SIZE)) +HCD_CONST(PGPE_IMAGE_SIZE, (48 * ONE_KB)) //RTC 158543 +HCD_CONST(PGPE_INT_VECTOR_SIZE, 384) +HCD_CONST(PGPE_HCODE_RESET_ADDR_VAL, 0x40) + +/// PGPE Header + +HCD_CONST(PGPE_HEADER_IMAGE_OFFSET, PGPE_INT_VECTOR_SIZE) +HCD_CONST(PGPE_HEADER_PPMR_OFFSET, + (PGPE_IMAGE_PPMR_OFFSET + PGPE_INT_VECTOR_SIZE)) +HCD_CONST(PGPE_HEADER_SIZE, 128) + +HCD_CONST(PGPE_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(PGPE_SYSTEM_RESET_ADDR_BYTE, 0x08) +HCD_CONST(PGPE_SHARED_SRAM_ADDR_BYTE, 0x0C) +HCD_CONST(PGPE_IVPR_ADDR_BYTE, 0x10) +HCD_CONST(PGPE_SHARED_SRAM_LENGTH_BYTE, 0x14) +HCD_CONST(PGPE_BUILD_DATE_BYTE, 0x18) +HCD_CONST(PGPE_BUILD_VER_BYTE, 0x1C) +HCD_CONST(PGPE_PGPE_FLAGS_BYTE, 0x20) +HCD_CONST(PGPE_GLOBAL_PSTATE_SRAM_ADDR_BYTE, 0x28) +HCD_CONST(PGPE_GLOBAL_PSTATE_MEM_OFFSET_BYTE, 0x30) +HCD_CONST(PGPE_GLOBAL_PSTATE_PPB_SIZE_BYTE, 0x34) +HCD_CONST(PGPE_GEN_PSTATE_TABLE_MEM_OFFSET_BYTE, 0x38) +HCD_CONST(PGPE_GEN_PSTATE_TABLE_SIZE_BYTE, 0x3C) +HCD_CONST(PGPE_OCC_PSTATE_TABLE_MEM_OFFSET_BYTE, 0x40) +HCD_CONST(PGPE_OCC_PSTATE_TABLE_SIZE_BYTE, 0x44) +HCD_CONST(PGPE_BEACON_ADDR_BYTE, 0x48) +HCD_CONST(PGPE_ACTUAL_QUAD_STATUS_ADDR_BYTE, 0x4C) +HCD_CONST(PGPE_WOF_TABLE_ADDR_BYTE, 0x50) +HCD_CONST(PGPE_WOF_TABLE_LENGTH_BYTE, 0x54) + +HCD_CONST(PGPE_RESET_ADDR_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_SYSTEM_RESET_ADDR_BYTE)) +HCD_CONST(PGPE_BUILD_DATE_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_BUILD_DATE_BYTE)) +HCD_CONST(PGPE_BUILD_VER_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_BUILD_VER_BYTE)) + +/// PGPE Hcode + +//HCD_CONST(PGPE_HCODE_SIZE, (32 * ONE_KB)) //RTC 158543 +HCD_CONST(PGPE_DBG_PTR_AREA_SIZE, 64) +HCD_CONST(PGPE_GLOBAL_PSTATE_PARAM_BLOCK_SIZE, (4 * ONE_KB)) + +/// Pstate Parameter Block + Pstate Table + +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET, (128 * ONE_KB)) +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_SIZE, (8 * ONE_KB)) +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_REGION_SIZE, (16 * ONE_KB)) + +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET, (144 * ONE_KB)) +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_SIZE, (8 * ONE_KB)) +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE, (16 * ONE_KB)) + +HCD_CONST(OCC_WOF_TABLES_PPMR_OFFSET, (768 * ONE_KB)) +HCD_CONST(OCC_WOF_TABLES_SIZE, (256 * ONE_KB)) + +HCD_CONST(PGPE_IMAGE_RESERVE_SIZE, + (OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - PGPE_IMAGE_PPMR_OFFSET - PGPE_IMAGE_SIZE)) + +#endif /* __HCD_MEMMAP_BASE_H__ */ diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H new file mode 100644 index 00000000..2e4bd09e --- /dev/null +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_cme_sram.H +/// @brief defines region constants of cme sram. +/// + +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot: Phyp + +#ifndef __P9_HCD_MEMMAP_CME_SRAM_H__ +#define __P9_HCD_MEMMAP_CME_SRAM_H__ + +#include <p9_hcd_header_defs.H> +#include <p9_hcd_memmap_base.H> + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +// ------------------------------------------------------------------- + +HCD_CONST(CME_SRAM_BASE_ADDR, 0xFFFF8000) +HCD_CONST(CME_SRAM_HEADER_ADDR, + (CME_SRAM_BASE_ADDR + CME_INT_VECTOR_SIZE)) + +#endif /* __P9_HCD_MEMMAP_CME_SRAM_H__ */ diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H new file mode 100644 index 00000000..c8afefd4 --- /dev/null +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H @@ -0,0 +1,88 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_homer.H +/// @brief defines region constants of homer. +/// + +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot:Phyp + +#ifndef __P9_HCD_MEMMAP_HOMER_H__ +#define __P9_HCD_MEMMAP_HOMER_H__ + +#include <p9_hcd_header_defs.H> +#include <p9_hcd_memmap_base.H> + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +//-------------------------------------------------------------------- + +/// HOMER + +HCD_CONST(HOMER_BASE_ADDR, 0x80000000) + +/// QPMR + +HCD_CONST(HOMER_QPMR_BASE_ADDR, (HOMER_BASE_ADDR + (QPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_QPMR_HEADER_ADDR, HOMER_QPMR_BASE_ADDR) +HCD_CONST(HOMER_SGPE_BOOT_LOADER_OFFSET_ADDR, + (HOMER_QPMR_HEADER_ADDR + QPMR_BOOT_LOADER_OFFSET_BYTE)) +HCD_CONST(HOMER_SGPE_BOOT_LOADER_LENGTH_ADDR, + (HOMER_QPMR_HEADER_ADDR + QPMR_BOOT_LOADER_LENGTH_BYTE)) +HCD_CONST(HOMER_SGPE_BOOT_COPIER_ADDR, + (HOMER_QPMR_HEADER_ADDR + QPMR_HEADER_SIZE)) + + +/// CPMR + +HCD_CONST(HOMER_CPMR_BASE_ADDR, (HOMER_BASE_ADDR + (CPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_CPMR_HEADER_ADDR, HOMER_CPMR_BASE_ADDR) + + +/// PPMR + +HCD_CONST(HOMER_PPMR_BASE_ADDR, (HOMER_BASE_ADDR + (PPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_PPMR_HEADER_ADDR, HOMER_PPMR_BASE_ADDR) +HCD_CONST(HOMER_PGPE_BOOT_LOADER_OFFSET_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_BOOT_LOADER_OFFSET_BYTE)) +HCD_CONST(HOMER_PGPE_BOOT_LOADER_LENGTH_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_BOOT_LOADER_LENGTH_BYTE)) +HCD_CONST(HOMER_PGPE_BOOT_COPIER_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_HEADER_SIZE)) + +HCD_CONST(HOMER_OCC_PSTATE_PARAM_BLOCK_ADDR, + (HOMER_PPMR_BASE_ADDR + OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET)); +HCD_CONST(HOMER_PGPE_PSTATE_OUTPUT_TABLES_ADDR, + (HOMER_PPMR_BASE_ADDR + PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET)); +HCD_CONST(HOMER_OCC_WOF_TABLES_ADDR, + (HOMER_PPMR_BASE_ADDR + OCC_WOF_TABLES_PPMR_OFFSET)); + +#endif /* __P9_HCD_MEMMAP_HOMER_H__ */ diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H new file mode 100644 index 00000000..3d7a1a36 --- /dev/null +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H @@ -0,0 +1,133 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_occ_sram.H +/// @brief defines region constants of occ sram. +/// + +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot: Phyp + +#ifndef __P9_HCD_MEMMAP_OCC_SRAM_H__ +#define __P9_HCD_MEMMAP_OCC_SRAM_H__ + +#include <p9_hcd_header_defs.H> +#include <p9_hcd_memmap_base.H> + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +// ------------------------------------------------------------------- + +/// OCC SRAM + +HCD_CONST(OCC_SRAM_BASE_ADDR, 0xFFF00000) +HCD_CONST(OCC_SRAM_IPC_REGION_SIZE, (4 * ONE_KB)) +HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE, (60 * ONE_KB)) +HCD_CONST(OCC_SRAM_GPE1_REGION_SIZE, (64 * ONE_KB)) +HCD_CONST(OCC_SRAM_PGPE_REGION_SIZE, (64 * ONE_KB)) +HCD_CONST(OCC_SRAM_SGPE_REGION_SIZE, (64 * ONE_KB)) +HCD_CONST(OCC_SRAM_OCC_REGION_SIZE, (512 * ONE_KB)) + +HCD_CONST(OCC_SRAM_BEFORE_PGPE_REGION_SIZE_TOTAL, + (OCC_SRAM_IPC_REGION_SIZE + OCC_SRAM_GPE0_REGION_SIZE + OCC_SRAM_GPE1_REGION_SIZE)) + +//-------------------------------------------------------------------------------------- + +/// PGPE Base + +HCD_CONST(OCC_SRAM_PGPE_BASE_ADDR, + (OCC_SRAM_BASE_ADDR + OCC_SRAM_BEFORE_PGPE_REGION_SIZE_TOTAL)) +HCD_CONST(OCC_SRAM_PGPE_END_ADDR, + (OCC_SRAM_PGPE_BASE_ADDR + OCC_SRAM_PGPE_REGION_SIZE)) +HCD_CONST(OCC_SRAM_PGPE_HCODE_RESET_ADDR, + (OCC_SRAM_PGPE_BASE_ADDR + PGPE_HCODE_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_PGPE_HEADER_ADDR, + (OCC_SRAM_PGPE_BASE_ADDR + PGPE_INT_VECTOR_SIZE)) + + +/// PGPE Boot + +HCD_CONST(OCC_SRAM_PGPE_COPY_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_PGPE_COPY_PPMR_HEADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_PGPE_BOOT_LOADER_ADDR, + (OCC_SRAM_PGPE_END_ADDR - OCC_SRAM_PGPE_COPY_BOOT_LOADER_SIZE)) +HCD_CONST(OCC_SRAM_PGPE_BOOT_LOADER_RESET_ADDR, + (OCC_SRAM_PGPE_BOOT_LOADER_ADDR + PGPE_BOOT_LOADER_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_PGPE_PPMR_HEADER_ADDR, + (OCC_SRAM_PGPE_BOOT_LOADER_ADDR - OCC_SRAM_PGPE_COPY_PPMR_HEADER_SIZE)) + +/// PGPE Copy + +HCD_CONST(OCC_SRAM_PGPE_HCODE_OFFSET_ADDR, + (OCC_SRAM_PGPE_PPMR_HEADER_ADDR + PPMR_PGPE_HCODE_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_PGPE_HCODE_LENGTH_ADDR, + (OCC_SRAM_PGPE_PPMR_HEADER_ADDR + PPMR_PGPE_HCODE_LENGTH_BYTE)) + +//-------------------------------------------------------------------------------------- + +/// SGPE Base + +HCD_CONST(OCC_SRAM_SGPE_BASE_ADDR, + (OCC_SRAM_BASE_ADDR + OCC_SRAM_BEFORE_PGPE_REGION_SIZE_TOTAL + OCC_SRAM_PGPE_REGION_SIZE)) +HCD_CONST(OCC_SRAM_SGPE_END_ADDR, + (OCC_SRAM_SGPE_BASE_ADDR + OCC_SRAM_SGPE_REGION_SIZE)) +HCD_CONST(OCC_SRAM_SGPE_HCODE_RESET_ADDR, + (OCC_SRAM_SGPE_BASE_ADDR + SGPE_HCODE_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_SGPE_HEADER_ADDR, + (OCC_SRAM_SGPE_BASE_ADDR + SGPE_INT_VECTOR_SIZE)) + +/// SGPE Boot + +HCD_CONST(OCC_SRAM_SGPE_COPY_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_SGPE_COPY_QPMR_HEADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_SGPE_BOOT_LOADER_ADDR, + (OCC_SRAM_SGPE_END_ADDR - OCC_SRAM_SGPE_COPY_BOOT_LOADER_SIZE)) +HCD_CONST(OCC_SRAM_SGPE_BOOT_LOADER_RESET_ADDR, + (OCC_SRAM_SGPE_BOOT_LOADER_ADDR + SGPE_BOOT_LOADER_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_SGPE_QPMR_HEADER_ADDR, + (OCC_SRAM_SGPE_BOOT_LOADER_ADDR - OCC_SRAM_SGPE_COPY_QPMR_HEADER_SIZE)) + +/// SGPE Copy + +HCD_CONST(OCC_SRAM_SGPE_HCODE_OFFSET_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_SGPE_HCODE_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_SGPE_HCODE_LENGTH_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_SGPE_HCODE_LENGTH_BYTE)) +HCD_CONST(OCC_SRAM_QUAD_COMMON_RINGS_OFFSET_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_COMMON_RINGS_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_QUAD_COMMON_RINGS_LENGTH_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_COMMON_RINGS_LENGTH_BYTE)) +HCD_CONST(OCC_SRAM_QUAD_SPECIFIC_RINGS_OFFSET_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_SPECIFIC_RINGS_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_QUAD_SPECIFIC_RINGS_LENGTH_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_SPECIFIC_RINGS_LENGTH_BYTE)) + + +#endif /* __P9_HCD_MEMMAP_OCC_SRAM_H__ */ diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 41b8fd88..a7e4fbb9 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -36,6 +36,11 @@ #define __HW_IMG_DEFINE #include <p9_hcd_header_defs.H> +#include <p9_hcd_memmap_base.H> +#include <p9_hcd_memmap_homer.H> +#include <p9_hcd_memmap_occ_sram.H> +#include <p9_hcd_memmap_cme_sram.H> + #include <p9_pstates_cmeqm.h> #include <p9_pstates_common.h> #include <p9_pstates_occ.h> @@ -53,21 +58,6 @@ namespace p9_hcodeImageBuild #endif //__PPE_PLAT #endif //__cplusplus #endif //__ASSEMBLER__ -// Constants used in both C++ and Assembler/Linker code -CONST_UINT32_T(CPMR_HEADER_SIZE, 256); -CONST_UINT32_T(QPMR_HEADER_SIZE, 512); -CONST_UINT32_T(PPMR_HEADER_SIZE, 512); -CONST_UINT32_T(PGPE_IVPR_ADDR, 0xfff20000); - -//#pragma message (STR(CPMR_HEADER_SIZE)) - -// Define the Magic Numbers for the various images -HCD_MAGIC_NUMBER(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)); // CPMR_1.0 -HCD_MAGIC_NUMBER(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)); // CME__1.0 -HCD_MAGIC_NUMBER(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)); // QPMR_1.0 -HCD_MAGIC_NUMBER(SGPE_MAGIC_NUMBER, ULL(0x534750455f312e30 )); // SGPE_1.0 -HCD_MAGIC_NUMBER(PPMR_MAGIC_NUMBER, ULL(0x50504d525f312e30)); // PPMR_1.0 -HCD_MAGIC_NUMBER(PGPE_MAGIC_NUMBER , ULL(0x504750455F312E30)); // PGPE_1.0 /** * @brief models QPMR header in HOMER @@ -323,7 +313,7 @@ typedef struct HCD_HDR_UINT64(g_pgpe_magic_number, PGPE_MAGIC_NUMBER); // PGPE_1.0 HCD_HDR_UINT32(g_pgpe_sys_reset_addr, 0 ); // Fully qualified OCC address where pk_init resides HCD_HDR_UINT32(g_pgpe_shared_sram_addr, 0 ); // SRAM address where shared SRAM begins -HCD_HDR_UINT32(g_pgpe_ivpr_addr, PGPE_IVPR_ADDR ); // Beginning of PGPE region in OCC SRAM +HCD_HDR_UINT32(g_pgpe_ivpr_addr, 0 ); // Beginning of PGPE region in OCC SRAM HCD_HDR_UINT32(g_pgpe_shared_sram_len, 0 ); // Length of shared SRAM area HCD_HDR_UINT32(g_pgpe_build_date, 0 ); // Build date for PGPE Image HCD_HDR_UINT32(g_pgpe_build_ver, 0 ); // Build Version @@ -355,172 +345,6 @@ HCD_HDR_UINT32(g_wof_table_length, 0 ); #ifndef __ASSEMBLER__ /** - * @brief summarizes constants associated with hcode image build. - */ -enum -{ - HALF_KB = 512, - ONE_KB = 1024, - ONE_MB = 1024 * 1024, - HARDWARE_IMG_SIZE = ONE_MB, - OCC_HOST_AREA_SIZE = ONE_MB, - HOMER_OCC_REGION_NUM = 0, - HOMER_QPMR_REGION_NUM = 1, - HOMER_CMPR_REGION_NUM = 2, - HOMER_PPMR_REGION_NUM = 3, - MAX_CORES_PER_CHIP = 24, - THREADS_PER_CORE = 4, - MAX_CME_PER_CHIP = 12, - MAX_CACHE_CHIPLETS = 6, - CACH0_CHIPLET_ID = 0x10, - MAX_CORES_PER_EX = 2, - CORE0_CHIPLET_ID = 0x20, - PAD_OPCODE = 0x00000200, //ATTN Opcode - BLR_INST = 0x4e800020, //blr instruction - THREAD_RESTORE_AREA_SIZE = 2048, - PPE_RESERVE_AREA = 0x200, - FUSED_MODE = 0xBB, - NONFUSED_MODE = 0xAA, - PK_DBG_PTR_AREA_SIZE = 64, - SCOM_ENTRY_SIZE = 16, // 4B pad, 4B address, 8B data - SCOM_RESTORE_PER_CHIPLET = 64, // size in words (16B * 16)/4 - - //---- QPMR ---- - QPMR_OFFSET = HOMER_QPMR_REGION_NUM * ONE_MB, - - //** Boot Loaders - SGPE_LVL_1_BOOT_LOAD_SIZE = ONE_KB, - SGPE_LVL_2_BOOT_LOAD_SIZE = ONE_KB, - - //** Hcode - SGPE_INT_VECT = 384, - SGPE_IMG_HEADER = sizeof(sgpeHeader_t), - SGPE_DBG_PTR_AREA_SIZE = 64, - SGPE_HCODE_SIZE = (45 * ONE_KB) + HALF_KB, // @todo RTC 158543 Reallocate space - - SGPE_IMAGE_SIZE = 80 * ONE_KB, - - SGPE_ALLOCATED_SIZE = SGPE_HCODE_SIZE, // @todo RTC 158543 Reallocate space (collapse??) - - //** Scan - SGPE_COMMON_RING_SIZE = 13 * ONE_KB, // 400B * 9 rings * 3 types (base, RL, CC) - SGPE_OVERRIDE_RING_SIZE = 3 * ONE_KB, // 300B * 9 rings - - CACHE_INST_SPECIFIC_SIZE = (3 * ONE_KB) + HALF_KB, // per cache, 1KB/ring x 5 rings/cache - SGPE_INSTRUMENTATION_SIZE = 2 * ONE_KB, - MAX_CACHE_CHIPLET = 6, - MAX_QUAD_SPEC_RING_SIZE = 19 * ONE_KB, - - //** SCOM - NUM_CACHE_SCOM_REGS = 47 + 1, // 16 L2 repr, 16 L3 repr, 15 non-repr, 1 NULL - CACHE_SCOM_RESTORE_SIZE = 6 * ONE_KB, //4488B rounded to 6KB - - CACHE_SCOM_START = 128 * ONE_KB, // HOMER offset from QPMR - - //** OCC SRAM Allocation - SGPE_MAX_AREA_SIZE = 80 * ONE_KB, // Allocation within the OCC SRAM - SGPE_RESERVE_SIZE = SGPE_MAX_AREA_SIZE - - ( SGPE_HCODE_SIZE + - SGPE_COMMON_RING_SIZE + - CACHE_SCOM_RESTORE_SIZE + - SGPE_OVERRIDE_RING_SIZE + - CACHE_SCOM_RESTORE_SIZE), - - //---- CPMR ---- - CPMR_OFFSET = HOMER_CMPR_REGION_NUM * ONE_MB, - - //** Self Restore - THREAD_LAUNCHER_SIZE = 256, - CORE_INT_AREA = 8 * ONE_KB, - SELF_REST_SIZE = CORE_INT_AREA + THREAD_LAUNCHER_SIZE, - CORE_RESTORE_SIZE = ((2 * ONE_KB) * THREADS_PER_CORE) * MAX_CORES_PER_CHIP, - - //** SCOM - CORE_SCOM_START = (256 * ONE_KB), - CORE_SCOM_RESTORE_SIZE = SCOM_ENTRY_SIZE * 16, // (15 registers + 1 NULL) per core - CME_SCOM_AREA = CORE_SCOM_RESTORE_SIZE * 2, // 2 cores - SCOM_AREA_PER_CME = HALF_KB, // 256(ea ) * 2( CORES PER CME) (???) - - //** Hcode - CORE_SCOM_PER_CME = 512, - CORE_SCOM_RES_SIZE = MAX_CME_PER_CHIP * SCOM_AREA_PER_CME, - CME_INT_VECTOR_SIZE = 384, - CME_IMG_HEADER_SIZE = 64, - CPMR_CME_HCODE_OFFSET = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - CME_REGION_SIZE = (64 * ONE_KB), // CME hcode and data's footprint in HOMER - CME_SRAM_SIZE = (32 * ONE_KB ), - - //** Scan - CORE_COMMON_RING_SIZE = 2 * ONE_KB, // common ring( 2KB) + common overrides (1KB) - MAX_SIZE_CME_INST_RING = 1 * ONE_KB, - CORE_OVERRIDE_RING = 1 * ONE_KB, // common for all cores - QUAD_PSTATE_SIZE = HALF_KB, // common for all cores - CME_INSTRUMENTATION_SIZE = HALF_KB, // per CME - INSTRUMENTATION_COUNTERS = HALF_KB, // (???) - CME_SRAM_HCODE_OFFSET = 0x00, //(???) - CME_REGION_START = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - CME_BLOCK_READ_LEN = 32, - CME_BLK_SIZE_SHIFT = 0x05, - - //CME Image Flags - CME_STOP_3_TO_2_BIT_POS = 0x80000000, - CME_STOP_4_TO_2_BIT_POS = 0x40000000, - CME_STOP_5_TO_4_BIT_POS = 0x20000000, - CME_STOP_8_TO_5_BIT_POS = 0x10000000, - CME_STOP_11_TO_8_BIT_POS = 0x08000000, - CME_SKIP_CORE_POWEROFF_BIT_POS = 0x00000001, - - //SGPE Image Flags - SGPE_STOP_4_TO_2_BIT_POS = 0x80000000, - SGPE_STOP_5_TO_4_BIT_POS = 0x40000000, - SGPE_STOP_8_TO_5_BIT_POS = 0x20000000, - SGPE_STOP_11_TO_8_BIT_POS = 0x10000000, - SGPE_PROC_FAB_ADDR_BAR_MODE_POS = 0x00008000, - - // PPMR - //** Boot Loaders - PPMR_OFFSET = HOMER_PPMR_REGION_NUM * ONE_MB, - PPMR_HEADER_LEN = 512, - PGPE_LVL_1_BOOT_LOAD_SIZE = ONE_KB, - PGPE_LVL_2_BOOT_LOAD_SIZE = ONE_KB, - PGPE_MAX_AREA_SIZE = 48 * ONE_KB, // @todo RTC 158543 Reallocate space - - PGPE_HOMER_SRAM_ALLOC = 128 * ONE_KB, - PGPE_HOMER_SRAM_RESERVE = PGPE_HOMER_SRAM_ALLOC - - (PPMR_HEADER_LEN + - PGPE_LVL_1_BOOT_LOAD_SIZE + - PGPE_LVL_2_BOOT_LOAD_SIZE + - PGPE_MAX_AREA_SIZE), - - PGPE_INT_VECTOR = 384, - PGPE_HCODE_SIZE = 32 * ONE_KB, - PGPE_PARAM_BLOCK_SIZE = 8 * ONE_KB, - - // @todo: get these from the p9_homer_map.h file - HOMER_OOC_PARAM_BLOCK_ADDR = 0x00320000, // PPMR + 128KB - HOMER_PSTATE_OUTPUT_TABLE_ADDR = 0x00324000, // PPMR + 144KB - HOMER_WOF_TABLE_ADDR = 0x003C0000, // PPMR + 768KB (the last 256KB) - - OCC_PARAM_BLOCK_ALLOC = 16 * ONE_KB, - OCC_PARAM_BLOCK_SIZE = 8 * ONE_KB, - - PSTATE_OUTPUT_TABLE_ALLOC = 16 * ONE_KB, - PSTATE_OUTPUT_TABLE_SIZE = 8 * ONE_KB, - - WOF_TABLES_BLOCK_ALLOC = 256 * ONE_KB, - - OCI_SRAM_ADDR_BASE = 0xFFF20000, // @todo: what is this for? - OCI_PBA_ADDR_BASE = 0x80300000, - IGNORE_CHIPLET_INSTANCE = 0xFF, - - //RING LAYOUT - RING_ALIGN_BOUNDARY = 0x08, - - //MISC - DARN_BAR_EN_POS = 0x8000000000000000ll, -}; - -/** * @brief enumerates all return codes associated with hcode image build. */ enum ImgBldRetCode_t @@ -599,13 +423,13 @@ typedef struct typedef struct { CoreSpecRingList_t coreSpecRings; - uint8_t instanceRingPayLoad[ MAX_SIZE_CME_INST_RING - sizeof(CoreSpecRingList_t)]; + uint8_t instanceRingPayLoad[ CORE_SPECIFIC_RING_SIZE_PER_CORE - sizeof(CoreSpecRingList_t)]; } CoreSpecRingCme_t; typedef union { CoreSpecRingCme_t instRingIndex; - uint8_t instScanRings[ MAX_SIZE_CME_INST_RING ]; + uint8_t instScanRings[ CORE_SPECIFIC_RING_SIZE_PER_CORE ]; } CoreSpecRingLayout_t; /** @@ -669,13 +493,13 @@ typedef struct typedef struct { QuadCmnRingsList_t quadCmnRingList; - uint8_t cmnRingPayLoad[SGPE_COMMON_RING_SIZE - sizeof(QuadCmnRingsList_t)]; + uint8_t cmnRingPayLoad[QUAD_COMMON_RING_SIZE - sizeof(QuadCmnRingsList_t)]; } QuadCmnRingsSgpe_t; typedef union { QuadCmnRingsSgpe_t cmnRingIndex; - uint8_t cmnScanRings[SGPE_COMMON_RING_SIZE]; + uint8_t cmnScanRings[QUAD_COMMON_RING_SIZE]; } CmnRingLayoutSgpe_t; /** @@ -699,14 +523,14 @@ typedef struct typedef struct { - QuadSpecRingsList_t quadSpecRings[MAX_CACHE_CHIPLET]; - uint8_t quadSpecRingPayLoad[ MAX_QUAD_SPEC_RING_SIZE - (MAX_CACHE_CHIPLET * sizeof(QuadSpecRingsList_t))]; + QuadSpecRingsList_t quadSpecRings[MAX_QUADS_PER_CHIP]; + uint8_t quadSpecRingPayLoad[ QUAD_SPECIFIC_RING_SIZE_TOTAL - (MAX_QUADS_PER_CHIP * sizeof(QuadSpecRingsList_t))]; } QuadSpecRing_t; typedef union { QuadSpecRing_t instRingIndex; - uint8_t instScanRings[ MAX_QUAD_SPEC_RING_SIZE ]; + uint8_t instScanRings[ QUAD_SPECIFIC_RING_SIZE_TOTAL ]; } InstRingLayoutSgpe_t; /** @@ -715,18 +539,18 @@ typedef union typedef struct { uint8_t qpmrHeader[sizeof(QpmrHeaderLayout_t)]; - uint8_t l1BootLoader[SGPE_LVL_1_BOOT_LOAD_SIZE]; - uint8_t l2BootLoader[SGPE_LVL_2_BOOT_LOAD_SIZE]; + uint8_t l1BootLoader[SGPE_BOOT_COPIER_SIZE]; + uint8_t l2BootLoader[SGPE_BOOT_LOADER_SIZE]; uint8_t sgpeSramImage[SGPE_IMAGE_SIZE]; } SgpeLayout_t; typedef union CPMRSelfRestoreLayout { - uint8_t region[SELF_REST_SIZE]; + uint8_t region[SELF_RESTORE_CODE_SIZE]; struct { cpmrHeader_t CPMRHeader; - uint8_t exe[SELF_REST_SIZE - sizeof(cpmrHeader_t)]; + uint8_t exe[SELF_RESTORE_CODE_SIZE - sizeof(cpmrHeader_t)]; } elements; } CPMRSelfRestoreLayout_t; @@ -736,9 +560,9 @@ typedef union CPMRSelfRestoreLayout typedef struct { CPMRSelfRestoreLayout_t CPMR_SR; - uint8_t coreSelfRestore[CORE_RESTORE_SIZE]; - uint8_t reserve[CORE_SCOM_START - (SELF_REST_SIZE + CORE_RESTORE_SIZE)]; - uint8_t coreScom[CORE_SCOM_RES_SIZE]; + uint8_t coreSelfRestore[SELF_RESTORE_CORE_REGS_SIZE]; + uint8_t reserve[CORE_SCOM_RESTORE_CPMR_OFFSET - SELF_RESTORE_SIZE_TOTAL]; + uint8_t coreScom[CORE_SCOM_RESTORE_SIZE_TOTAL]; } SelfRestoreLayout_t; typedef struct @@ -752,15 +576,15 @@ typedef struct */ typedef struct { - uint8_t ppmrHeader[PPMR_HEADER_LEN]; - uint8_t l1BootLoader[PGPE_LVL_1_BOOT_LOAD_SIZE]; - uint8_t l2BootLoader[PGPE_LVL_2_BOOT_LOAD_SIZE]; - uint8_t pgpeSramImage[PGPE_MAX_AREA_SIZE]; // Includes the Global Pstate Parameter Block - uint8_t ppmr_reserved0[PGPE_HOMER_SRAM_RESERVE]; + uint8_t ppmrHeader[PPMR_HEADER_SIZE]; + uint8_t l1BootLoader[PGPE_BOOT_COPIER_SIZE]; + uint8_t l2BootLoader[PGPE_BOOT_LOADER_SIZE]; + uint8_t pgpeSramImage[PGPE_IMAGE_SIZE]; // Includes the Global Pstate Parameter Block + uint8_t ppmr_reserved0[PGPE_IMAGE_RESERVE_SIZE]; uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB - uint8_t occParmBlockReserve[OCC_PARAM_BLOCK_ALLOC - sizeof(OCCPstateParmBlock)]; + uint8_t occParmBlockReserve[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE - sizeof(OCCPstateParmBlock)]; uint8_t pstateTable[sizeof(GeneratedPstateInfo)]; // PPMR + 144KB - uint8_t pstateTableReserve[PSTATE_OUTPUT_TABLE_ALLOC - sizeof(GeneratedPstateInfo)]; + uint8_t pstateTableReserve[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE - sizeof(GeneratedPstateInfo)]; } PPMRLayout_t; /** @@ -769,8 +593,8 @@ typedef struct typedef struct { SgpeLayout_t sgpeRegion; - uint8_t qpmrReserve1[CACHE_SCOM_START - sizeof(SgpeLayout_t)]; - uint8_t cacheScomRegion[CACHE_SCOM_RESTORE_SIZE]; + uint8_t qpmrReserve1[QUAD_SCOM_RESTORE_QPMR_OFFSET - sizeof(SgpeLayout_t)]; + uint8_t cacheScomRegion[QUAD_SCOM_RESTORE_SIZE_TOTAL]; } QPMRLayout_t; /** diff --git a/import/chips/p9/procedures/ppe_closed/cme/link.cmd b/import/chips/p9/procedures/ppe_closed/cme/link.cmd index 121c73e4..3c266aab 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/link.cmd +++ b/import/chips/p9/procedures/ppe_closed/cme/link.cmd @@ -23,15 +23,21 @@ /* */ /* IBM_PROLOG_END_TAG */ -// Need to do this so that elf32-powerpc is not modified! -#undef powerpc - #ifndef INITIAL_STACK_SIZE #define INITIAL_STACK_SIZE 256 #endif OUTPUT_FORMAT(elf32-powerpc); -#include "p9_cme_img_layout.h" + +// Need to do this so that memmap header uses defines for linkerscript +#define __LINKERSCRIPT__ +#include "p9_hcd_memmap_cme_sram.H" + +#define SRAM_START CME_SRAM_BASE_ADDR +#define SRAM_LENGTH CME_SRAM_SIZE +#define PPE_HEADER_IMAGE_OFFSET CME_HEADER_IMAGE_OFFSET +#define PPE_DEBUG_PTRS_OFFSET CME_DEBUG_PTRS_OFFSET +#define PPE_DEBUG_PTRS_SIZE CME_DEBUG_PTRS_SIZE MEMORY { @@ -54,7 +60,7 @@ SECTIONS .vectors _VECTOR_START : { *(.vectors) } > sram - _CME_IMG_HEADER = _VECTOR_START + CME_HEADER_OFFSET; + _CME_IMG_HEADER = _VECTOR_START + PPE_HEADER_IMAGE_OFFSET; /////////////////////////////////////////////////////////////////////////// // // CME Image Header diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c index c9d0a024..bb978c3b 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c @@ -170,7 +170,7 @@ main(int argc, char** argv) PK_TRACE("Kernel init completed"); // reading header attributes and initialize the queued scom mode - cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_BASE + CME_HEADER_IMAGE_OFFSET); + cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR); G_cme_stop_record.header_flags = pCmeImgHdr->g_cme_mode_flags; if (G_cme_stop_record.header_flags & QUEUED_SCAN_DISABLE) diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cpmr_img_edit.C b/import/chips/p9/procedures/ppe_closed/cme/p9_cpmr_img_edit.C index 1f9f24ef..c4ae3e34 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cpmr_img_edit.C +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cpmr_img_edit.C @@ -22,37 +22,18 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + #include <stdio.h> #include <stdint.h> #include <netinet/in.h> #include <time.h> #include <stddef.h> /* offsetof */ -#include <p9_cme_img_layout.h> #include <pk_debug_ptrs.h> #include <p9_hcode_image_defines.H> using namespace p9_hcodeImageBuild; -enum -{ - HCODE_OFFSET_POS = 0x190, - HCODE_LEN_POS = 0x194, - CME_HCODE_OFFSET = 0x200, - CME_BUILD_DATE_POS = 0x188, - CME_BUILD_VER_POS = 0x18C, - CME_BUILD_VER = 0x001, - CPMR_ATTN_WORD0 = 0x00, - CPMR_ATTN_WORD1 = 0x03, - CPMR_BUILD_DATE_POS = 0x10, - CPMR_BUILD_VER_POS = 0x14, - CPMR_HCODE_OFFSET_POS = 0x20, - CPMR_HCODE_LEN_POS = 0x24, - CPMR_SELFREST_OFF_POS = 0x48, - CPMR_SELFREST_OFF_VAL = 0x100, - CPMR_SELFREST_LEN_POS = 0x4C, -}; - int main(int narg, char* argv[]) { if (narg < 4) @@ -106,7 +87,7 @@ int main(int narg, char* argv[]) printf(" Self Restore size : %d (0x%X)\n", selfRestSize, selfRestSize); // cme build date yyyymmdd - fseek ( pImage, CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_build_date) , SEEK_SET ); + fseek ( pImage, CME_HEADER_IMAGE_OFFSET + offsetof(cmeHeader_t, g_cme_build_date) , SEEK_SET ); fseek ( pCpmr, offsetof(cpmrHeader_t, cpmrbuildDate) , SEEK_SET ); uint32_t temp = (((headerTime->tm_year + 1900) << 16) | ((headerTime->tm_mon + 1) << 8) | @@ -119,47 +100,47 @@ int main(int narg, char* argv[]) fwrite(&temp, sizeof(cpmrHeader.cpmrbuildDate), 1, pCpmr ); // cme build version - fseek ( pImage, CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_build_ver) , SEEK_SET ); + fseek ( pImage, CME_HEADER_IMAGE_OFFSET + offsetof(cmeHeader_t, g_cme_build_ver) , SEEK_SET ); fseek ( pCpmr, offsetof(cpmrHeader_t, cpmrVersion) , SEEK_SET ); - temp = htonl(CME_BUILD_VER); + temp = htonl(CME_BUILD_VERSION); fwrite(&temp, sizeof(cmeHeader.g_cme_build_ver), 1, pImage ); fwrite(&temp, sizeof(cpmrHeader.cpmrVersion), 1, pCpmr ); - printf(" CME_HEADER_OFFSET : %X\n", CME_HEADER_OFFSET); + printf(" CME_HEADER_IMAGE_OFFSET : %X\n", CME_HEADER_IMAGE_OFFSET); // cme hcode offset - fseek ( pImage, HCODE_OFFSET_POS , SEEK_SET ); - temp = CME_HCODE_OFFSET; + fseek ( pImage, CME_HCODE_OFF_IMAGE_OFFSET , SEEK_SET ); + temp = CME_HCODE_IMAGE_OFFSET; temp = htonl(temp); fwrite(&(temp), sizeof(uint32_t), 1, pImage ); // cme hcode length - fseek ( pImage , HCODE_LEN_POS , SEEK_SET ); + fseek ( pImage , CME_HCODE_LEN_IMAGE_OFFSET , SEEK_SET ); temp = htonl( Imagesize ); fwrite(&temp, sizeof(uint32_t), 1, pImage ); fwrite(&temp, sizeof(uint32_t), 1, pCpmr ); // self restore offset+ length - fseek ( pCpmr , CPMR_SELFREST_OFF_POS , SEEK_SET ); - temp = htonl( CPMR_SELFREST_OFF_VAL ); + fseek ( pCpmr , CPMR_SELF_RESTORE_OFFSET_BYTE , SEEK_SET ); + temp = htonl( SELF_RESTORE_CPMR_OFFSET ); fwrite(&temp, sizeof(uint32_t), 1, pCpmr ); - fseek ( pCpmr , CPMR_SELFREST_LEN_POS , SEEK_SET ); + fseek ( pCpmr , CPMR_SELF_RESTORE_LENGTH_BYTE , SEEK_SET ); temp = htonl( selfRestSize ); fwrite(&temp, sizeof(uint32_t), 1, pCpmr ); - printf(" CME Hcode Offset Address: %X\n", CME_HEADER_OFFSET + offsetof(cmeHeader_t, + printf(" CME Hcode Offset Address: %X\n", CME_HEADER_IMAGE_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_offset)); - fseek ( pImage, CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_offset) , SEEK_SET ); - temp = CME_HCODE_OFFSET; + fseek ( pImage, CME_HEADER_IMAGE_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_offset) , SEEK_SET ); + temp = CME_HCODE_IMAGE_OFFSET; temp = htonl(temp); fwrite(&temp, sizeof(cmeHeader.g_cme_hcode_offset), 1, pImage ); fwrite(&temp, sizeof(cpmrHeader.cmeImgOffset), 1, pCpmr ); // cme hcode length - printf(" CME HCode Length Address: %X\n", CME_HEADER_OFFSET + offsetof(cmeHeader_t, + printf(" CME HCode Length Address: %X\n", CME_HEADER_IMAGE_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_length)); - fseek ( pImage, CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_length) , SEEK_SET ); + fseek ( pImage, CME_HEADER_IMAGE_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_length) , SEEK_SET ); fseek ( pCpmr, offsetof(cpmrHeader_t, cmeImgLength) , SEEK_SET ); temp = htonl( Imagesize ); fwrite(&temp, sizeof(cmeHeader.g_cme_hcode_length), 1, pImage ); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c index 3c3c04e5..4f127ae5 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c @@ -22,22 +22,17 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + #include "p9_cme_copy_scan_ring.h" #include "p9_cme_stop.h" -#include "cmehw_common.h" -#include "gpehw_common.h" -#include "p9_cme_img_layout.h" -#include "p9_hcode_image_defines.H" /// @brief local constants. enum { SPR_NUM_PIR = 286, - CME_IMAGE_BASE_ADDR = SRAM_START, CME_INST_ID_MASK = 0x0000001E, COPY_DEF_CME_ADDR = 0x00000000, CME_PAGE_RD_SIZE = 0x20, - CME_IMG_HDR_ADDR = CME_IMAGE_BASE_ADDR + CME_HEADER_OFFSET, CME_FLAG_EX_ID_BIT = 26, EX_ID_SHIFT_POS = 5, }; @@ -47,9 +42,9 @@ void instance_scan_init( ) uint32_t l_cmePir = 0; uint32_t l_bcLength = 0; - cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_IMG_HDR_ADDR); + cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR); //Setting Mbase with start address of CME Inst rings in HOMER - uint32_t l_bceMbase = CPMR_CME_HCODE_OFFSET + ( pCmeImgHdr->g_cme_core_spec_ring_offset << 5 ); + uint32_t l_bceMbase = CME_IMAGE_CPMR_OFFSET + (pCmeImgHdr->g_cme_core_spec_ring_offset << 5); uint32_t l_exId = ((in32(CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS); asm volatile ( "mfspr %0, %1 \n\t" : "=r" (l_cmePir) : "i" (SPR_NUM_PIR)); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c index d203a638..fb3bcac0 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c @@ -22,22 +22,17 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + #include <stdio.h> #include <stdint.h> #include <netinet/in.h> #include <stddef.h> /* offsetof */ -#include <p9_cme_img_layout.h> #include <pk_debug_ptrs.h> #include <p9_hcode_image_defines.H> enum { - - CME_HCODE_OFFSET = 0x200, - CPMR_SELFREST_OFF_POS = 0x48, - CPMR_SELFREST_OFF_VAL = 0x100, - CPMR_SELFREST_LEN_POS = 0x4C, CME_IMAGE = 1, CPMR_IMAGE = 2, }; @@ -54,8 +49,8 @@ int main(int narg, char* argv[]) cmeHeader_t cmeHeader; int imageType = CME_IMAGE; - long int hcodeLenPos = CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_length); - long int hcodeOffsetPos = CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_offset); + long int hcodeLenPos = CME_HEADER_IMAGE_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_length); + long int hcodeOffsetPos = CME_HEADER_IMAGE_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_offset); FILE* pImage = fopen( argv[1], "r+" ); @@ -72,10 +67,10 @@ int main(int narg, char* argv[]) break; } - printf(" Debug Pointers Offset : %d (0x%X)\n", PPE_DEBUG_PTRS_OFFSET, PPE_DEBUG_PTRS_OFFSET); + printf(" Debug Pointers Offset : %d (0x%X)\n", CME_DEBUG_PTRS_OFFSET, CME_DEBUG_PTRS_OFFSET); printf(" Debug Pointers size : %ld (0x%lX)\n", sizeof(pk_debug_ptrs_t), sizeof(pk_debug_ptrs_t)); - printf(" CME Image Offset : %ld (0x%lX)\n", PPE_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t), - PPE_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t)); + printf(" CME Image Offset : %ld (0x%lX)\n", CME_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t), + CME_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t)); fseek (pImage, 0, SEEK_END); @@ -85,7 +80,7 @@ int main(int narg, char* argv[]) // For ekb build it's desired to detect the image type w/o special // make rules. Better way? - if(size < CME_HCODE_OFFSET) + if(size < CME_HCODE_IMAGE_OFFSET) { imageType = CPMR_IMAGE; hcodeLenPos = offsetof(cpmrHeader_t, cmeImgLength); @@ -100,7 +95,7 @@ int main(int narg, char* argv[]) printf(" CME Hcode Offset Address: %ld (0x%lX)\n", hcodeOffsetPos , hcodeOffsetPos); fseek ( pImage, hcodeOffsetPos , SEEK_SET ); - uint32_t temp = CME_HCODE_OFFSET; + uint32_t temp = CME_HCODE_IMAGE_OFFSET; temp = htonl(temp); fwrite(&temp, sizeof(cmeHeader.g_cme_hcode_offset), 1, pImage ); @@ -119,11 +114,11 @@ int main(int narg, char* argv[]) rewind(pSelfRest); printf(" Self Restore size %s : %d (0x%X)\n", argv[3], selfRestSize, selfRestSize); - fseek ( pImage , CPMR_SELFREST_OFF_POS , SEEK_SET ); - temp = htonl( CPMR_SELFREST_OFF_VAL ); + fseek ( pImage , CPMR_SELF_RESTORE_OFFSET_BYTE , SEEK_SET ); + temp = htonl( SELF_RESTORE_CPMR_OFFSET ); fwrite(&temp, sizeof(uint32_t), 1, pImage ); - fseek ( pImage , CPMR_SELFREST_LEN_POS , SEEK_SET ); + fseek ( pImage , CPMR_SELF_RESTORE_LENGTH_BYTE , SEEK_SET ); temp = htonl( selfRestSize ); fwrite(&temp, sizeof(uint32_t), 1, pImage ); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index 386023f9..efc86863 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -43,6 +43,7 @@ #include "ppm_firmware_registers.h" #include "cppm_firmware_registers.h" +#include "p9_hcode_image_defines.H" #include "p9_stop_common.h" // ram_vtid [0:1] 00 diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 8235ccb7..c876ebf6 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -26,7 +26,6 @@ #include "p9_cme_stop.h" #include "p9_cme_stop_exit_marks.h" #include "p9_cme_copy_scan_ring.h" -#include "p9_hcode_image_defines.H" extern CmeStopRecord G_cme_stop_record; @@ -570,7 +569,7 @@ p9_cme_stop_exit() while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); - cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_BASE + CME_HEADER_IMAGE_OFFSET); + cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR); scom_data.value = pCmeImgHdr->g_cme_cpmr_PhyAddr & BITS64(13, 30); //HRMOR[13:42] #if NIMBUS_DD_LEVEL == 1 diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scomcust.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scomcust.c index 6b8881d8..5a970f08 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scomcust.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scomcust.c @@ -25,7 +25,6 @@ #include "p9_cme_stop.h" #include "p9_cme_stop_exit_marks.h" -#include "p9_hcode_image_defines.H" int p9_hcd_core_scomcust(uint32_t core) diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c index a44f81c0..93649fbe 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c @@ -25,7 +25,6 @@ #include "p9_cme_stop.h" #include "p9_cme_stop_exit_marks.h" -#include "p9_hcode_image_defines.H" int p9_hcd_core_startclocks(uint32_t core) @@ -34,7 +33,7 @@ p9_hcd_core_startclocks(uint32_t core) uint32_t id_vector = 0; data64_t scom_data = {0}; - cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_BASE + CME_HEADER_IMAGE_OFFSET); + cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR); id_vector = pCmeImgHdr->g_cme_location_id; PK_TRACE("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c index 75492597..27afb2b9 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c +++ b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c @@ -24,14 +24,10 @@ /* IBM_PROLOG_END_TAG */ #include "plat_ring_traverse.h" -#include "p9_hcode_image_defines.H" -#include "pk.h" #include "p9_ringid_cme.h" #include "p9_cme_stop.h" - - void getRingProperties(const RingID i_ringId, uint32_t* o_torOffset, RINGTYPE* o_ringType) @@ -86,7 +82,7 @@ int putRing( getRingProperties(i_ringID, &l_torOffset, &l_ringType); - uint8_t* pCmeImage = (uint8_t*)(CME_SRAM_BASE); + uint8_t* pCmeImage = (uint8_t*)(CME_SRAM_BASE_ADDR); cmeHeader_t* l_cmeHeader = (cmeHeader_t*) ( pCmeImage + CME_INT_VECTOR_SIZE ); @@ -104,7 +100,7 @@ int putRing( } l_sectionAddr = - (uint32_t*)(CME_SRAM_BASE + (l_cmeHeader->g_cme_core_spec_ring_offset * 32)); + (uint32_t*)(CME_SRAM_BASE_ADDR + (l_cmeHeader->g_cme_core_spec_ring_offset * 32)); if (i_core == 2) { @@ -125,7 +121,7 @@ int putRing( } l_sectionAddr = - (uint32_t*)(CME_SRAM_BASE + l_cmeHeader->g_cme_common_ring_offset); + (uint32_t*)(CME_SRAM_BASE_ADDR + l_cmeHeader->g_cme_common_ring_offset); // TOR records of Ring TOR are 2 bytes in size. l_ringTorAddr = (uint16_t*)(l_sectionAddr) + (l_torOffset); @@ -150,7 +146,7 @@ int putRing( } l_sectionAddr = - (uint32_t*)(CME_SRAM_BASE + l_cmeHeader->g_cme_cmn_ring_ovrd_offset); + (uint32_t*)(CME_SRAM_BASE_ADDR + l_cmeHeader->g_cme_cmn_ring_ovrd_offset); // TOR records of Ring TOR are 2 bytes in size. l_ringTorAddr = (uint16_t*)(l_sectionAddr) + (l_torOffset); diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/linkcopier.cmd b/import/chips/p9/procedures/ppe_closed/pgpe/boot/linkcopier.cmd index bc761039..674a1050 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/linkcopier.cmd +++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/linkcopier.cmd @@ -23,29 +23,24 @@ /* */ /* IBM_PROLOG_END_TAG */ -// Need to do this so that elf32-powerpc is not modified! -#undef powerpc - #ifndef INITIAL_STACK_SIZE #define INITIAL_STACK_SIZE 256 #endif OUTPUT_FORMAT(elf32-powerpc); -// @todo 155077 The following value shouldn't be hardcoded here. -#define MEM_START 0x80300200 -#define MEM_LENGTH 1024 +// Need to do this so that memmap header uses defines for linkerscript +#define __LINKERSCRIPT__ +#include <p9_hcd_memmap_homer.H> + +#define MEM_START HOMER_PGPE_BOOT_COPIER_ADDR +#define MEM_LENGTH PGPE_BOOT_COPIER_SIZE MEMORY { mem : ORIGIN = MEM_START, LENGTH = MEM_LENGTH } -// This symbol is only needed by external debug tools, so add this command -// to ensure that table is pulled in by the linker even though PPE code -// never references it. -EXTERN(pk_debug_ptrs); - SECTIONS { . = MEM_START; @@ -56,16 +51,6 @@ SECTIONS .vectors _VECTOR_START : { *(.vectors) } > mem - /////////////////////////////////////////////////////////////////////////// - // Debug Pointers Table - // - // We want the debug pointers table to alway appear at - // PPE_DEBUG_PTRS_OFFSET from the IVPR address. - /////////////////////////////////////////////////////////////////////////// - - //_DEBUG_PTRS_START = _VECTOR_START + PPE_DEBUG_PTRS_OFFSET; - //.debug_ptrs _DEBUG_PTRS_START : { *(.debug_ptrs) } > mem - //////////////////////////////// // All non-vector code goes here //////////////////////////////// diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/linkloader.cmd b/import/chips/p9/procedures/ppe_closed/pgpe/boot/linkloader.cmd index d98528ab..c2b7591b 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/linkloader.cmd +++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/linkloader.cmd @@ -23,31 +23,24 @@ /* */ /* IBM_PROLOG_END_TAG */ -// Need to do this so that elf32-powerpc is not modified! -#undef powerpc - #ifndef INITIAL_STACK_SIZE #define INITIAL_STACK_SIZE 256 #endif OUTPUT_FORMAT(elf32-powerpc); -// @todo 155077 The following value shouldn't be hardcoded here. -#define SRAM_START 0xfff2fc00 -#define SRAM_LENGTH 0x10000 -#define PPE_DEBUG_PTRS_OFFSET 0x180 +// Need to do this so that memmap header uses defines for linkerscript +#define __LINKERSCRIPT__ +#include <p9_hcd_memmap_occ_sram.H> +#define SRAM_START OCC_SRAM_PGPE_BOOT_LOADER_ADDR +#define SRAM_LENGTH OCC_SRAM_PGPE_COPY_BOOT_LOADER_SIZE MEMORY { sram : ORIGIN = SRAM_START, LENGTH = SRAM_LENGTH } -// This symbol is only needed by external debug tools, so add this command -// to ensure that table is pulled in by the linker even though PPE code -// never references it. -EXTERN(pk_debug_ptrs); - SECTIONS { . = SRAM_START; @@ -58,16 +51,6 @@ SECTIONS .vectors _VECTOR_START : { *(.vectors) } > sram - /////////////////////////////////////////////////////////////////////////// - // Debug Pointers Table - // - // We want the debug pointers table to alway appear at - // PPE_DEBUG_PTRS_OFFSET from the IVPR address. - /////////////////////////////////////////////////////////////////////////// - - _DEBUG_PTRS_START = _VECTOR_START + PPE_DEBUG_PTRS_OFFSET; - .debug_ptrs _DEBUG_PTRS_START : { *(.debug_ptrs) } > sram - //////////////////////////////// // All non-vector code goes here //////////////////////////////// diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_copier.S b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_copier.S index 37ca8696..296e8914 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_copier.S +++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_copier.S @@ -24,6 +24,9 @@ /* IBM_PROLOG_END_TAG */ .nolist +#include <ppe42_asm.h> +#include <p9_hcd_memmap_homer.H> +#include <p9_hcd_memmap_occ_sram.H> #include <pgpe_boot_defines.H> .list @@ -74,13 +77,13 @@ __watchdog_interrupt: __bootCopier: ## Address where the Boot loader will be loaded in SRAM (Destination address) - _liw %GPR_BL_SRAM_ADDR, SRAM_PGPE_BOOT_LOADER_ADDR + _liw %GPR_BL_SRAM_ADDR, OCC_SRAM_PGPE_BOOT_LOADER_ADDR ## Base address of PPMR header, also the PGPE base address - _liw %GPR_PPMR_ADDR, PPMR_HEADER_ADDR + _liw %GPR_PPMR_ADDR, HOMER_PPMR_HEADER_ADDR ## Location in PPMR header where the offset of Boot loader is present - _liw %GPR_BL_HOMER, HOMER_BOOT_LOADER_OFFSET_ADDR + _liw %GPR_BL_HOMER, HOMER_PGPE_BOOT_LOADER_OFFSET_ADDR ## Fetch offset of Boot loader lwz GPR_BL_HOMER_ADDR, OFFSET(GPR_BL_HOMER) @@ -89,7 +92,7 @@ __bootCopier: add GPR_BL_HOMER_ADDR, GPR_BL_HOMER_ADDR, GPR_PPMR_ADDR ## Location in PPMR header where the length of boot loader is present - _liw %GPR_BL_HOMER, HOMER_BOOT_LOADER_LENGTH_ADDR + _liw %GPR_BL_HOMER, HOMER_PGPE_BOOT_LOADER_LENGTH_ADDR ## Boot Loader size(in Bytes) lwz GPR_BL_SIZE, OFFSET(GPR_BL_HOMER) @@ -116,7 +119,7 @@ copy_loop: BRANCH: ## branch to the system_reset location for bootLoader to be executed - _liw %GPR_TEMP, SRAM_PGPE_BOOT_LOADER_RESET_ADDR + _liw %GPR_TEMP, OCC_SRAM_PGPE_BOOT_LOADER_RESET_ADDR mtlr GPR_TEMP blr diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_defines.H b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_defines.H index 3e4f4afd..b60d61b2 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_defines.H +++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_defines.H @@ -25,54 +25,14 @@ /// \file p9_pgpe_boot_defines.H - #ifndef __HCD_GPE_BOOT_DEFINES_H__ #define __HCD_GPE_BOOT_DEFINES_H__ -#include <ppe42_asm.h> - - -// Base address of HOMER -#define HOMER_BASE_ADDR 0x80000000 - -// SRAM Base address -#define SRAM_BASE_ADDR 0xFFF00000 - -// SRAM Base address of PGPE region -#define SRAM_PGPE_BASE_ADDR 0xFFF20000 - -// Address of PGPE HCODE in HOMER, to be loaded in IVPR -#define PGPE_IVPR_OCI_ADDR 0xC0020008 - -// 48KB allocated for PGPE in SRAM -#define SRAM_PGPE_MEM_ALLOC (48 * 1024) - -// The numeric identity of PGPE - GPE2 -#define PGPE_NUM 0x2 - -// The position of the PGPE region in HOMER -#define HOMER_PGPE_REGION 0x3 // Zero origin; 1MB per region - -// Offset in PPMR header at which the BL offset is stored -#define HOMER_BOOT_LOADER_OFFSET_HDR_LOC 0x10 - -// Offset in PPMR header at which the BL length is stored -#define HOMER_BOOT_LOADER_LENGTH_HDR_LOC 0x14 - // Offset in PPMR header at which the execution status will be written #define STATE_WRITE_OFFSET 0x5A -// Reset offset -#define RESET_OFFSET 0x40 - -// Size of PPMR header (bytes) -#define PPMR_HEADER_SIZE 0x200 - -// Offset in PPMR header, where the HCODE offset resides -#define SRAM_PGPE_HCODE_OFFSET_BYTE 0x28 - -// Offset in PPMR header, where the HCODE length resides -#define SRAM_PGPE_HCODE_LENGTH_BYTE 0x50 +// Address in PPMR header in HOMER where the copie/loader status will be written +#define STATE_WRITE_ADDR (PPMR_HEADER_ADDR + STATE_WRITE_OFFSET) // Status codes for failure/success of Boot loader and copier #define BCPASS_STAT 0x4350 // Ascii of "CP" -> Boot Copier passed @@ -80,45 +40,12 @@ #define BLPASS_STAT 0x4C50 // Ascii of "LP" -> Boot Loader passed #define BLFAIL_STAT 0x4C46 // Ascii of "LF" -> Boot Loader failed - -// Absolute base address of PPMR Header in HOMER -#define PPMR_HEADER_ADDR (HOMER_BASE_ADDR + HOMER_PGPE_REGION*1024*1024) - -// Absolute address of BL offset in PPMR header in HOMER -#define HOMER_BOOT_LOADER_OFFSET_ADDR (PPMR_HEADER_ADDR + HOMER_BOOT_LOADER_OFFSET_HDR_LOC) - -// Absolute address of BL length in PPMR header in HOMER -#define HOMER_BOOT_LOADER_LENGTH_ADDR (PPMR_HEADER_ADDR + HOMER_BOOT_LOADER_LENGTH_HDR_LOC) - -// Address in PPMR header in HOMER where the copie/loader status will be written -#define STATE_WRITE_ADDR (PPMR_HEADER_ADDR + STATE_WRITE_OFFSET) - -// Base Address of Boot Loader in SRAM PGPE region -#define SRAM_PGPE_BOOT_LOADER_ADDR (SRAM_PGPE_BASE_ADDR + SRAM_PGPE_MEM_ALLOC - 1024) - -// Base address of PPMR header in SRAM PGPE Region -#define SRAM_PGPE_PPMR_ADDR (SRAM_PGPE_BOOT_LOADER_ADDR - 1024) - -// Address of reset vector in SRAM to which branch happens after BL is loaded -#define SRAM_PGPE_BOOT_LOADER_RESET_ADDR (SRAM_PGPE_BOOT_LOADER_ADDR + RESET_OFFSET) - -// Address of reset vector in SRAM to which branch happens after HCODE is loaded -#define SRAM_PGPE_HCODE_RESET_ADDR (SRAM_PGPE_BASE_ADDR + RESET_OFFSET) - -// Base address of PGPE HCODE offset in SRAM -#define SRAM_PGPE_HCODE_OFFSET_ADDR SRAM_PGPE_PPMR_ADDR + SRAM_PGPE_HCODE_OFFSET_BYTE - -// Base address of PGPE image length in SRAM -#define SRAM_PGPE_IMAGE_LENGTH_ADDR SRAM_PGPE_PPMR_ADDR + SRAM_PGPE_HCODE_LENGTH_BYTE - - // Constants used in copier and loader #define OFFSET 0 #define OFF_STAT_WR 0x54 #define PGPE_DIV_8 0x03 #define NXT_BLK_OFF 0x8 - // Register mnemonics used in Boot Copier #define GPR_BL_SRAM_ADDR r3 #define GPR_PPMR_ADDR r4 diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_loader.S b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_loader.S index 10b4d5fe..2e0cbacb 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_loader.S +++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_loader.S @@ -23,8 +23,12 @@ /* */ /* IBM_PROLOG_END_TAG */ .nolist +#include <ppe42_asm.h> +#include <p9_hcd_memmap_homer.H> +#include <p9_hcd_memmap_occ_sram.H> +#include <gpe_register_addresses.h> #include <pgpe_boot_defines.H> - .list + .list .global __vectors __vectors: @@ -78,8 +82,8 @@ __bootLoader: ## update IVPR to Boot Loader Base Addr in OCC SRAM - _liw %BL_START_SRAM_ADDRESS_REG, SRAM_PGPE_BOOT_LOADER_ADDR - _liw %GPR_TEMP, PGPE_IVPR_OCI_ADDR + _liw %BL_START_SRAM_ADDRESS_REG, OCC_SRAM_PGPE_BOOT_LOADER_ADDR + _liw %GPR_TEMP, GPE_GPE2IVPR stw BL_START_SRAM_ADDRESS_REG, OFFSET (GPR_TEMP) ## Enable Trap @@ -87,10 +91,10 @@ __bootLoader: mtdbcr GPR_TEMP ## Address of PPMR in HOMER(source address) - _liw %GPR_PPMR_HOMER_ADDR, PPMR_HEADER_ADDR + _liw %GPR_PPMR_HOMER_ADDR, HOMER_PPMR_HEADER_ADDR ## Address of PPMR in SRAM(destination Address) - _liw %GPR_PPMR_SRAM_ADDR, SRAM_PGPE_PPMR_ADDR + _liw %GPR_PPMR_SRAM_ADDR, OCC_SRAM_PGPE_PPMR_HEADER_ADDR ## Load the size of PPMR header (in double words) _liw %GPR_SIZE, PPMR_HEADER_SIZE @@ -112,13 +116,13 @@ PPMR_header_copy_loop: ######################### ## Address in SRAM where the payload will have to be copied (Destination address) - _liw %GPR_SRAM_PGPE_ADDR, SRAM_PGPE_BASE_ADDR + _liw %GPR_SRAM_PGPE_ADDR, OCC_SRAM_PGPE_BASE_ADDR ## Address in SRAM where the offset of payload will be found - _liw %GPR_SRAM_HCODE_OFF_ADDR, SRAM_PGPE_HCODE_OFFSET_ADDR + _liw %GPR_SRAM_HCODE_OFF_ADDR, OCC_SRAM_PGPE_HCODE_OFFSET_ADDR ## Base address of PPMR header in HOMER - _liw %GPR_PPMR_HOMER_ADDR, PPMR_HEADER_ADDR + _liw %GPR_PPMR_HOMER_ADDR, HOMER_PPMR_HEADER_ADDR ## Offset of HCODE from PPMR header lwz GPR_HOMER_PAYLOAD_OFF, OFFSET(GPR_SRAM_HCODE_OFF_ADDR) @@ -127,7 +131,7 @@ PPMR_header_copy_loop: add GPR_ADDR_PAYLOAD_HOMER, GPR_PPMR_HOMER_ADDR, GPR_HOMER_PAYLOAD_OFF ## Address in SRAM where the length of payload will be found - _liw %GPR_SRAM_IMG_LEN_ADDR, SRAM_PGPE_IMAGE_LENGTH_ADDR + _liw %GPR_SRAM_IMG_LEN_ADDR, OCC_SRAM_PGPE_HCODE_LENGTH_ADDR ## Size of payload (in double words) lwz GPR_SIZE, OFFSET(GPR_SRAM_IMG_LEN_ADDR) @@ -157,12 +161,12 @@ payload_copy_loop: ######################## branch: ## Reset address to which branch must take place - _liw %GPR_TEMP, SRAM_PGPE_HCODE_RESET_ADDR + _liw %GPR_TEMP, OCC_SRAM_PGPE_HCODE_RESET_ADDR mtlr GPR_TEMP ## Setup the IVPR for the Hcode - _liw %GPR_PPMR_HOMER_ADDR, SRAM_PGPE_BASE_ADDR - _liw %GPR_ADDR_PAYLOAD_HOMER, PGPE_IVPR_OCI_ADDR + _liw %GPR_PPMR_HOMER_ADDR, OCC_SRAM_PGPE_BASE_ADDR + _liw %GPR_ADDR_PAYLOAD_HOMER, GPE_GPE2IVPR stw GPR_PPMR_HOMER_ADDR, OFFSET(GPR_ADDR_PAYLOAD_HOMER) blr diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_lvl1_copier.mk b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_lvl1_copier.mk index 5fdfde07..9d6d668e 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_lvl1_copier.mk +++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_lvl1_copier.mk @@ -67,6 +67,7 @@ $(call ADD_PPEIMAGE_INCDIR, $(IMAGE), $(PGPE_SRCDIR)/boot \ $(PM_LIBDIR)/occlib \ $(HCODE_LIBDIR) \ $(HCODE_COMMON_LIBDIR) \ + $(ROOTPATH)/chips/p9/procedures/hwp/lib/ \ ) $(IMAGE)_LDFLAGS=-e __system_reset -N -gc-sections -Bstatic diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_lvl2_loader.mk b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_lvl2_loader.mk index 816b6454..53e2eedc 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_lvl2_loader.mk +++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_lvl2_loader.mk @@ -56,11 +56,19 @@ $(call ADD_PPEIMAGE_SRCDIR,$(PGPE_SRCDIR)/boot \ ) # add include paths -$(call ADD_PPEIMAGE_INCDIR, $(IMAGE), $(PGPE_SRCDIR)/boot \ - $(PK_SRCDIR)/ppe42 \ - $(HCODE_LIBDIR) \ - $(HCODE_COMMON_LIBDIR) \ - ) +$(call ADD_PPEIMAGE_INCDIR,$(IMAGE),$(PGPE_SRCDIR)/boot \ + $(PK_SRCDIR)/kernel \ + $(PK_SRCDIR)/ppe42 \ + $(PK_SRCDIR)/trace \ + $(PK_SRCDIR)/$(_PPE_TYPE) \ + $(PM_LIBDIR)/include \ + $(PM_LIBDIR)/include/registers \ + $(PM_LIBDIR)/common \ + $(PM_LIBDIR)/occlib \ + $(HCODE_LIBDIR) \ + $(HCODE_COMMON_LIBDIR) \ + $(ROOTPATH)/chips/p9/procedures/hwp/lib/ \ + ) $(IMAGE)_LDFLAGS=-e __system_reset -N -gc-sections -Bstatic diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c index d76c7b7c..ada004b6 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c @@ -31,17 +31,8 @@ enum { - PGPE_RESET_ADDR_POS = 0x0188, - PGPE_RESET_ADDRESS = 0x40, - PGPE_BUILD_DATE_POS = 0x0198, - PGPE_BUILD_VER_POS = 0x019C, - PGPE_BUILD_VER = 0x01, - PPMR_BUILD_DATE_POS = 0x18, - PPMR_BUILD_VER_POS = 0x1C, PGPE_IMAGE = 1, PPMR_IMAGE = 2, - PPMR_PGPE_HCODE_OFF_POS = 0x28, - PPMR_PGPE_HCODE_OFF_VAL = 0xA00, //512B + 1KB + 1kB }; int main(int narg, char* argv[]) @@ -110,7 +101,7 @@ int main(int narg, char* argv[]) // populating RESET address uint32_t l_reset_addr_pos = offsetof(PgpeHeader_t, g_pgpe_sys_reset_addr); fseek (pMainImage, l_reset_addr_pos, SEEK_SET); - temp = PGPE_RESET_ADDRESS; + temp = PGPE_HCODE_RESET_ADDR_VAL; temp = htonl(temp); fwrite(&(temp), sizeof(uint32_t), 1, pMainImage ); @@ -133,7 +124,7 @@ int main(int narg, char* argv[]) // build ver printf(" Build version: %X pos %X\n", temp, buildVerPos); fseek( pMainImage, buildVerPos, SEEK_SET ); - temp = htonl(PGPE_BUILD_VER); + temp = htonl(PGPE_BUILD_VERSION); fwrite(&temp, sizeof(uint32_t), 1, pMainImage ); if (imageType == PPMR_IMAGE) @@ -142,8 +133,8 @@ int main(int narg, char* argv[]) uint32_t l_hcode_offset_pos = offsetof(PpmrHeader_t, g_ppmr_hcode_offset); fseek ( pMainImage , l_hcode_offset_pos, SEEK_SET ); temp = sizeof(PpmrHeader_t) + - PGPE_LVL_1_BOOT_LOAD_SIZE + - PGPE_LVL_2_BOOT_LOAD_SIZE; + PGPE_BOOT_COPIER_SIZE + + PGPE_BOOT_LOADER_SIZE; printf(" PPMR Hcode offset: 0x%X\n", temp); temp = htonl(temp); fwrite(&temp, sizeof(uint32_t), 1, pMainImage ); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/linkcopier.cmd b/import/chips/p9/procedures/ppe_closed/sgpe/boot/linkcopier.cmd index 86defc12..b87f59b3 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/linkcopier.cmd +++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/linkcopier.cmd @@ -23,29 +23,24 @@ /* */ /* IBM_PROLOG_END_TAG */ -// Need to do this so that elf32-powerpc is not modified! -#undef powerpc - #ifndef INITIAL_STACK_SIZE #define INITIAL_STACK_SIZE 256 #endif OUTPUT_FORMAT(elf32-powerpc); -// @todo 155077 The following value shouldn't be hardcoded here. -#define MEM_START 0x80100200 -#define MEM_LENGTH 1024 +// Need to do this so that memmap header uses defines for linkerscript +#define __LINKERSCRIPT__ +#include <p9_hcd_memmap_homer.H> + +#define MEM_START HOMER_SGPE_BOOT_COPIER_ADDR +#define MEM_LENGTH SGPE_BOOT_COPIER_SIZE MEMORY { mem : ORIGIN = MEM_START, LENGTH = MEM_LENGTH } -// This symbol is only needed by external debug tools, so add this command -// to ensure that table is pulled in by the linker even though PPE code -// never references it. -EXTERN(pk_debug_ptrs); - SECTIONS { . = MEM_START; @@ -56,16 +51,6 @@ SECTIONS .vectors _VECTOR_START : { *(.vectors) } > mem - /////////////////////////////////////////////////////////////////////////// - // Debug Pointers Table - // - // We want the debug pointers table to alway appear at - // PPE_DEBUG_PTRS_OFFSET from the IVPR address. - /////////////////////////////////////////////////////////////////////////// - - //_DEBUG_PTRS_START = _VECTOR_START + PPE_DEBUG_PTRS_OFFSET; - //.debug_ptrs _DEBUG_PTRS_START : { *(.debug_ptrs) } > mem - //////////////////////////////// // All non-vector code goes here //////////////////////////////// diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/linkloader.cmd b/import/chips/p9/procedures/ppe_closed/sgpe/boot/linkloader.cmd index d6783a90..28be2510 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/linkloader.cmd +++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/linkloader.cmd @@ -23,31 +23,24 @@ /* */ /* IBM_PROLOG_END_TAG */ -// Need to do this so that elf32-powerpc is not modified! -#undef powerpc - #ifndef INITIAL_STACK_SIZE #define INITIAL_STACK_SIZE 256 #endif OUTPUT_FORMAT(elf32-powerpc); -// @todo 155077 The following value shouldn't be hardcoded here. -#define SRAM_START 0xfff3fc00 -#define SRAM_LENGTH 0x10000 -#define PPE_DEBUG_PTRS_OFFSET 0x180 +// Need to do this so that memmap header uses defines for linkerscript +#define __LINKERSCRIPT__ +#include <p9_hcd_memmap_occ_sram.H> +#define SRAM_START OCC_SRAM_SGPE_BOOT_LOADER_ADDR +#define SRAM_LENGTH OCC_SRAM_SGPE_COPY_BOOT_LOADER_SIZE MEMORY { sram : ORIGIN = SRAM_START, LENGTH = SRAM_LENGTH } -// This symbol is only needed by external debug tools, so add this command -// to ensure that table is pulled in by the linker even though PPE code -// never references it. -EXTERN(pk_debug_ptrs); - SECTIONS { . = SRAM_START; @@ -58,16 +51,6 @@ SECTIONS .vectors _VECTOR_START : { *(.vectors) } > sram - /////////////////////////////////////////////////////////////////////////// - // Debug Pointers Table - // - // We want the debug pointers table to alway appear at - // PPE_DEBUG_PTRS_OFFSET from the IVPR address. - /////////////////////////////////////////////////////////////////////////// - - _DEBUG_PTRS_START = _VECTOR_START + PPE_DEBUG_PTRS_OFFSET; - .debug_ptrs _DEBUG_PTRS_START : { *(.debug_ptrs) } > sram - //////////////////////////////// // All non-vector code goes here //////////////////////////////// diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_copier.S b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_copier.S index 4971056c..90c66de0 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_copier.S +++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_copier.S @@ -25,7 +25,8 @@ .nolist #include <ppe42_asm.h> -#include <sgpe_boot_defines.H> +#include <p9_hcd_memmap_homer.H> +#include <p9_hcd_memmap_occ_sram.H> .list .section .loader_text, "ax", @progbits @@ -76,12 +77,12 @@ __watchdog_interrupt: __bootCopier: //load r3 with BASE_ - _liw %r3, HOMER_BOOT_LOADER_LENGTH_ADDR + _liw %r3, HOMER_SGPE_BOOT_LOADER_LENGTH_ADDR - _liw %r7, HOMER_BOOT_LOADER_OFFSET_ADDR + _liw %r7, HOMER_SGPE_BOOT_LOADER_OFFSET_ADDR //load r4 with address where bootLoader will be loaded in SRAM e.g 0xFFFE8000 (Destination address) - _liw %r4, SRAM_SGPE_BOOT_LOADER_ADDR # dest + _liw %r4, OCC_SRAM_SGPE_BOOT_LOADER_ADDR # dest //load r9 with QPMR header address _liw %r9, HOMER_QPMR_HEADER_ADDR @@ -105,7 +106,7 @@ copy_loop: bdnz copy_loop # Keep repeating the address. ## Using blr command: - _liw %r6, SRAM_SGPE_BOOT_LOADER_RESET_ADDR + _liw %r6, OCC_SRAM_SGPE_BOOT_LOADER_RESET_ADDR mtlr r6 blr .epilogue __bootCopier diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S index 0bf93379..f8a5968c 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S +++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S @@ -24,7 +24,9 @@ /* IBM_PROLOG_END_TAG */ .nolist #include <ppe42_asm.h> -#include <sgpe_boot_defines.H> +#include <p9_hcd_memmap_homer.H> +#include <p9_hcd_memmap_occ_sram.H> +#include <gpe_register_addresses.h> .list .global __vectors @@ -79,8 +81,8 @@ __bootLoader: ## Setup the IVPR for the loader context - _liw %r9, SRAM_SGPE_BOOT_LOADER_ADDR - _liw %r8, SGPE_IVPR_OCI_ADDR + _liw %r9, OCC_SRAM_SGPE_BOOT_LOADER_ADDR + _liw %r8, GPE_GPE3IVPR stw r9, 0(r8) ## Enable halt on trap @@ -92,7 +94,7 @@ __bootLoader: _liw %r3, HOMER_QPMR_HEADER_ADDR ## Calculate Destination Address(in r4) - _liw %r4, SRAM_QPMR_ADDR + _liw %r4, OCC_SRAM_SGPE_QPMR_HEADER_ADDR ## Find double words(in r5). _liw %r5, QPMR_HEADER_SIZE @@ -113,13 +115,13 @@ qpmr_header_copy_loop: ## Copy SGPE Header/Exe ######################### ## Calculate Source address(in r8) - _liw %r6, SRAM_SGPE_HCODE_OFFSET_ADDR + _liw %r6, OCC_SRAM_SGPE_HCODE_OFFSET_ADDR lwz r7, 0(r6) _liw %r9, HOMER_QPMR_HEADER_ADDR - add r8,r9,r7 + add r8,r9,r7 ## Calculate Destination address - _liw %r4, SRAM_SGPE_BASE_ADDR + _liw %r4, OCC_SRAM_SGPE_BASE_ADDR ## Calculate the double word count to copy and place in R5 ## @@ -145,24 +147,24 @@ qpmr_header_copy_loop: ## Compute the ending offset of the Hcode section. Note: the beginning is ## R7 - _liw %r10, SRAM_SGPE_HCODE_LENGTH_ADDR + _liw %r10, OCC_SRAM_SGPE_HCODE_LENGTH_ADDR lwz r29, 0(r10) - add r3, r7, r29 + add r3, r7, r29 lis r31, 0xB00F ori r31, r31, 0x0001 mtsprg0 r31 ## Compute the end of the common rings section. ## If not present (eg Offset or length = 0), use the end of the Hcode section - _liw %r10, SRAM_COMMON_RINGS_OFFSET_ADDR + _liw %r10, OCC_SRAM_QUAD_COMMON_RINGS_OFFSET_ADDR lwz r28, 0(r10) bwz r28, end_common_rings - _liw %r10, SRAM_COMMON_RINGS_LENGTH_ADDR + _liw %r10, OCC_SRAM_QUAD_COMMON_RINGS_LENGTH_ADDR lwz r29, 0(r10) bwz r29, end_common_rings - add r3, r28, r29 + add r3, r28, r29 lis r31, 0xB00F ori r31, r31, 0x0002 mtsprg0 r31 @@ -171,15 +173,15 @@ end_common_rings: ## Compute the end of the specific rings section. ## If not present (eg Offset or length = 0), use the end of the common section - _liw %r10, SRAM_SPECIFIC_RINGS_OFFSET_ADDR + _liw %r10, OCC_SRAM_QUAD_SPECIFIC_RINGS_OFFSET_ADDR lwz r28, 0(r10) bwz r28, end_specific_rings - _liw %r10, SRAM_SPECIFIC_RINGS_LENGTH_ADDR + _liw %r10, OCC_SRAM_QUAD_SPECIFIC_RINGS_LENGTH_ADDR lwz r29, 0(r10) bwz r29, end_specific_rings - add r3, r28, r29 + add r3, r28, r29 lis r31, 0xB00F ori r31, r31, 0x0003 mtsprg0 r31 @@ -210,12 +212,12 @@ payload_copy_loop: mtsprg0 r31 ## Load the branch address - _liw %r6, SRAM_GPE_HCODE_RESET_ADDR + _liw %r6, OCC_SRAM_SGPE_HCODE_RESET_ADDR mtlr r6 ## Setup the IVPR for the Hcode - _liw %r9, SRAM_SGPE_BASE_ADDR - _liw %r8, SGPE_IVPR_OCI_ADDR + _liw %r9, OCC_SRAM_SGPE_BASE_ADDR + _liw %r8, GPE_GPE3IVPR stw r9, 0(r8) blr diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_lvl1_copier.mk b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_lvl1_copier.mk index db27c004..c4698390 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_lvl1_copier.mk +++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_lvl1_copier.mk @@ -67,6 +67,7 @@ $(call ADD_PPEIMAGE_INCDIR,$(IMAGE),$(SGPE_SRCDIR)/boot \ $(PM_LIBDIR)/occlib \ $(HCODE_LIBDIR) \ $(HCODE_COMMON_LIBDIR) \ + $(ROOTPATH)/chips/p9/procedures/hwp/lib/ \ ) $(IMAGE)_LDFLAGS=-e __system_reset -N -gc-sections -Bstatic diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_lvl2_loader.mk b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_lvl2_loader.mk index 20ca01bf..f4c0ad31 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_lvl2_loader.mk +++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_lvl2_loader.mk @@ -64,6 +64,7 @@ $(call ADD_PPEIMAGE_INCDIR,$(IMAGE),$(SGPE_SRCDIR)/boot \ $(PM_LIBDIR)/occlib \ $(HCODE_LIBDIR) \ $(HCODE_COMMON_LIBDIR) \ + $(ROOTPATH)/chips/p9/procedures/hwp/lib/ \ ) $(IMAGE)_LDFLAGS=-e __system_reset -N -gc-sections -Bstatic diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/p9_sgpe_img_edit.c b/import/chips/p9/procedures/ppe_closed/sgpe/p9_sgpe_img_edit.c index d6e84878..b449f850 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/p9_sgpe_img_edit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/p9_sgpe_img_edit.c @@ -27,20 +27,12 @@ #include <netinet/in.h> #include <time.h> +#include <p9_hcd_memmap_base.H> + enum { - SGPE_RESET_ADDR_POS = 0x0188, - SGPE_RESET_ADDRESS = 0x40, - SGPE_BUILD_DATE_POS = 0x0198, - SGPE_BUILD_VER_POS = 0x019C, - SGPE_BUILD_VER = 0x01, - QPMR_BUILD_DATE_POS = 0x18, - QPMR_BUILD_VER_POS = 0x1C, SGPE_IMAGE = 1, QPMR_IMAGE = 2, - QPMR_SGPE_HCODE_OFF_POS = 0x28, - QPMR_SGPE_HCODE_OFF_VAL = 0xA00, //512B + 1KB + 1kB - QPMR_SGPE_HCODE_LEN_POS = 0x28, }; int main(int narg, char* argv[]) @@ -54,8 +46,8 @@ int main(int narg, char* argv[]) } int imageType = SGPE_IMAGE; - long int buildDatePos = SGPE_BUILD_DATE_POS; - long int buildVerPos = SGPE_BUILD_VER_POS; + long int buildDatePos = SGPE_BUILD_DATE_IMAGE_OFFSET; + long int buildVerPos = SGPE_BUILD_VER_IMAGE_OFFSET; FILE* pMainImage = fopen( argv[1], "r+"); FILE* pDependImage = fopen(argv[2], "r+"); @@ -82,8 +74,8 @@ int main(int narg, char* argv[]) if(size < 1024) { imageType = QPMR_IMAGE; - buildDatePos = QPMR_BUILD_DATE_POS; - buildVerPos = QPMR_BUILD_VER_POS; + buildDatePos = QPMR_BUILD_DATE_BYTE; + buildVerPos = QPMR_BUILD_VER_BYTE; if( !pDependImage ) { @@ -103,8 +95,8 @@ int main(int narg, char* argv[]) // populating SGPE Image Header // populating RESET address - fseek (pMainImage, SGPE_RESET_ADDR_POS, SEEK_SET); - temp = SGPE_RESET_ADDRESS; + fseek (pMainImage, SGPE_RESET_ADDR_IMAGE_OFFSET, SEEK_SET); + temp = SGPE_HCODE_RESET_ADDR_VAL; temp = htonl(temp); fwrite(&(temp), sizeof(uint32_t), 1, pMainImage ); } @@ -122,19 +114,19 @@ int main(int narg, char* argv[]) // build ver fseek( pMainImage, buildVerPos, SEEK_SET ); - temp = htonl(SGPE_BUILD_VER); + temp = htonl(SGPE_BUILD_VERSION); fwrite(&temp, sizeof(uint32_t), 1, pMainImage ); if (imageType == QPMR_IMAGE) { //SGPE HCODE offset in QPMR header - fseek ( pMainImage , QPMR_SGPE_HCODE_OFF_POS, SEEK_SET ); - temp = QPMR_SGPE_HCODE_OFF_VAL; + fseek ( pMainImage , QPMR_SGPE_HCODE_OFFSET_BYTE, SEEK_SET ); + temp = SGPE_IMAGE_QPMR_OFFSET; temp = htonl(temp); fwrite(&temp, sizeof(uint32_t), 1, pMainImage ); //SGPE Hcode length in QPMR header - fseek ( pMainImage , QPMR_SGPE_HCODE_LEN_POS, SEEK_SET ); + fseek ( pMainImage , QPMR_SGPE_HCODE_LENGTH_BYTE, SEEK_SET ); temp = QPMR_SGPE_HCODE_LEN_VAL; temp = htonl(temp); fwrite(&temp, sizeof(uint32_t), 1, pMainImage ); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd index c8cf11d6..cf021a0d 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd @@ -23,21 +23,21 @@ /* */ /* IBM_PROLOG_END_TAG */ -// Need to do this so that elf32-powerpc is not modified! -#undef powerpc - #ifndef INITIAL_STACK_SIZE #define INITIAL_STACK_SIZE 256 #endif OUTPUT_FORMAT(elf32-powerpc); -// GPE3 is loaded at 0xfff30000 -#define SRAM_START 0xfff30000 -#define SRAM_LENGTH 0x10000 -#define SGPE_IMAGE_OFFSET 0x180 -#define PPE_DEBUG_PTRS_OFFSET 0x200 -#define PPE_DEBUG_PTRS_SIZE 0x24 +// Need to do this so that memmap header uses defines for linkerscript +#define __LINKERSCRIPT__ +#include "p9_hcd_memmap_occ_sram.H" + +#define SRAM_START OCC_SRAM_SGPE_BASE_ADDR +#define SRAM_LENGTH OCC_SRAM_SGPE_REGION_SIZE +#define PPE_HEADER_IMAGE_OFFSET SGPE_HEADER_IMAGE_OFFSET +#define PPE_DEBUG_PTRS_OFFSET SGPE_DEBUG_PTRS_OFFSET +#define PPE_DEBUG_PTRS_SIZE SGPE_DEBUG_PTRS_SIZE MEMORY { @@ -59,7 +59,7 @@ SECTIONS _VECTOR_START = .; .vectors _VECTOR_START : { *(.vectors) } > sram - _SGPE_IMG_HEADER = _VECTOR_START + SGPE_IMAGE_OFFSET; + _SGPE_IMG_HEADER = _VECTOR_START + PPE_HEADER_IMAGE_OFFSET; /////////////////////////////////////////////////////////////////////////// // // SGPE Image Header diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c index 8a4698b3..223a9fed 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c @@ -25,7 +25,6 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_exit_marks.h" -#include "p9_hcode_image_defines.H" int p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_ex, int is_stop8) @@ -49,7 +48,7 @@ p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_ex, int is_stop8) } // To access memory, need to set MSB of homer address - QpmrHeaderLayout_t* pQpmrHdrAddr = (QpmrHeaderLayout_t*)(QPMR_BASE_HOMER_OFFSET | BIT32(0)); + QpmrHeaderLayout_t* pQpmrHdrAddr = (QpmrHeaderLayout_t*)(HOMER_QPMR_HEADER_ADDR); SgpeScomRestore* pSgpeScomRes = (SgpeScomRestore*)(pQpmrHdrAddr->quadScomOffset + (uint32_t)pQpmrHdrAddr + qoffset); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c index 6998ec3a..233c535f 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c @@ -25,7 +25,6 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_exit_marks.h" -#include "p9_hcode_image_defines.H" extern SgpeStopRecord G_sgpe_stop_record; @@ -40,7 +39,7 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8) uint32_t ex_index = 0; data64_t scom_data = {0}; ocb_qcsr_t qcsr = {0}; - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET); + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR); if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT64(17)) { diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c index fa07fbab..bd24b033 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c @@ -25,7 +25,6 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_exit_marks.h" -#include "p9_hcode_image_defines.H" int p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) @@ -36,7 +35,7 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) uint32_t bitloc = 0; data64_t scom_data = {0}; - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET); + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR); id_vector = pSgpeImgHdr->g_sgpe_location_id; // ------------------------------- diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_edit.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_edit.mk index bb69025c..8dd79344 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_edit.mk +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_edit.mk @@ -23,12 +23,32 @@ # # IBM_PROLOG_END_TAG EXE=stop_gpeImgEdit + +$(EXE)_COMMONFLAGS+= -D__PPE_PLAT + +$(call ADD_EXE_INCDIR, $(EXE), \ + $(CME_SRCDIR) \ + $(PK_SRCDIR)/kernel \ + $(HCODE_COMMON_LIBDIR) \ + $(HCODE_LIBDIR) \ + ) + IMAGE_DEPS+=stop_gpeImgEdit OBJS=p9_sgpe_img_edit.o $(call BUILD_EXE) EXE=qpmr_headerImgEdit + +$(EXE)_COMMONFLAGS+= -D__PPE_PLAT + +$(call ADD_EXE_INCDIR, $(EXE), \ + $(CME_SRCDIR) \ + $(PK_SRCDIR)/kernel \ + $(HCODE_COMMON_LIBDIR) \ + $(HCODE_LIBDIR) \ + ) + IMAGE_DEPS+=qpmr_headerImgEdit OBJS=p9_sgpe_img_edit.o $(call BUILD_EXE) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_image_header.S b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_image_header.S index 6ae0b8a0..5c54febc 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_image_header.S +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_image_header.S @@ -28,75 +28,6 @@ #version, IVPR address, __system_reset_address are populated during SGPE image build #process. -.section ".sgpe_image_header" , "aw" +#include <p9_hcode_image_defines.H> -.global g_sgpe_magic_word -.global g_sgpe_reset_address -.global g_sgpe_reserve1 -.global g_sgpe_ivpr_address -.global g_sgpe_reserve2 -.global g_sgpe_build_date -.global g_sgpe_build_ver -.global g_sgpe_resv_flag -.global g_sgpe_cmn_ring_occ_offset -.global g_sgpe_spec_ring_occ_offset -.global g_sgpe_cmn_scom_offset -.global g_sgpe_reserve3 -.global g_sgpe_reserve4 -.global g_sgpe_reserve5 -#----------------------------------------------------- -# SGPE HEADER -#----------------------------------------------------- -# Word 0 | Word 1 -#----------------------------------------------------- -# Magic Number -#----------------------------------------------------- -# __system_reset_address| Reserved -#----------------------------------------------------- -# IVPR address | Reserved -#----------------------------------------------------- -# Build Date | Version -#----------------------------------------------------- -# Reserve Flag -#----------------------------------------------------- -# Quad Cmn Ring Occ | Quad Spec Rings Occ -# Offset | Offset -#----------------------------------------------------- -# Quad Cmn SCOM Occ | Reserved -# Offset | -#----------------------------------------------------- -# Reserved -#----------------------------------------------------- - -g_sgpe_magic_word: -.quad 0x5849502053475045 #XIP SGPE - -g_sgpe_reset_address: -.long 0 - -g_sgpe_reserve1: -.long 0 - -g_sgpe_ivpr_address: -.long 0xFFF30000 - -g_sgpe_reserve2: -.long 0 - -g_sgpe_build_date: -.long 0 - -g_sgpe_build_ver: -.long 0 - -g_sgpe_resv_flag: -.quad 0 - -g_sgpe_cmn_ring_occ_offset: -.long 0 - -g_sgpe_spec_ring_occ_offset: -.long 0 - -g_sgpe_cmn_scom_offset: -.long 0 +.sgpe_header diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c index 54bb8c67..46a64c16 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c @@ -22,25 +22,18 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + #include <stdio.h> #include <stdint.h> #include <netinet/in.h> #include <time.h> +#include <p9_hcd_memmap_base.H> + enum { - SGPE_RESET_ADDR_POS = 0x0188, - SGPE_RESET_ADDRESS = 0x40, - SGPE_BUILD_DATE_POS = 0x0198, - SGPE_BUILD_VER_POS = 0x019C, - SGPE_BUILD_VER = 0x01, - QPMR_BUILD_DATE_POS = 0x18, - QPMR_BUILD_VER_POS = 0x1C, SGPE_IMAGE = 1, QPMR_IMAGE = 2, - QPMR_SGPE_HCODE_OFF_POS = 0x28, - QPMR_SGPE_HCODE_OFF_VAL = 0xA00, //512B + 1KB + 1kB - QPMR_SGPE_HCODE_LEN_POS = 0x28, }; int main(int narg, char* argv[]) @@ -54,8 +47,8 @@ int main(int narg, char* argv[]) } int imageType = SGPE_IMAGE; - long int buildDatePos = SGPE_BUILD_DATE_POS; - long int buildVerPos = SGPE_BUILD_VER_POS; + long int buildDatePos = SGPE_BUILD_DATE_IMAGE_OFFSET; + long int buildVerPos = SGPE_BUILD_VER_IMAGE_OFFSET; FILE* pMainImage = fopen( argv[1], "r+"); FILE* pDependImage = fopen(argv[2], "r+"); @@ -83,8 +76,8 @@ int main(int narg, char* argv[]) { printf(" QPMR size: %d\n", size); imageType = QPMR_IMAGE; - buildDatePos = QPMR_BUILD_DATE_POS; - buildVerPos = QPMR_BUILD_VER_POS; + buildDatePos = QPMR_BUILD_DATE_BYTE; + buildVerPos = QPMR_BUILD_VER_BYTE; if( !pDependImage ) { @@ -104,8 +97,8 @@ int main(int narg, char* argv[]) printf(" SGPE size: %d\n", size); // populating SGPE Image Header // populating RESET address - fseek (pMainImage, SGPE_RESET_ADDR_POS, SEEK_SET); - temp = SGPE_RESET_ADDRESS; + fseek (pMainImage, SGPE_RESET_ADDR_IMAGE_OFFSET, SEEK_SET); + temp = SGPE_HCODE_RESET_ADDR_VAL; temp = htonl(temp); fwrite(&(temp), sizeof(uint32_t), 1, pMainImage ); } @@ -122,19 +115,19 @@ int main(int narg, char* argv[]) // build ver fseek( pMainImage, buildVerPos, SEEK_SET ); - temp = htonl(SGPE_BUILD_VER); + temp = htonl(SGPE_BUILD_VERSION); fwrite(&temp, sizeof(uint32_t), 1, pMainImage ); if (imageType == QPMR_IMAGE) { //SGPE HCODE offset in QPMR header - fseek ( pMainImage , QPMR_SGPE_HCODE_OFF_POS, SEEK_SET ); - temp = QPMR_SGPE_HCODE_OFF_VAL; + fseek ( pMainImage , QPMR_SGPE_HCODE_OFFSET_BYTE, SEEK_SET ); + temp = SGPE_IMAGE_QPMR_OFFSET; temp = htonl(temp); fwrite(&temp, sizeof(uint32_t), 1, pMainImage ); //SGPE Hcode length in QPMR header - fseek ( pMainImage , QPMR_SGPE_HCODE_LEN_POS, SEEK_SET ); + fseek ( pMainImage , QPMR_SGPE_HCODE_LENGTH_BYTE, SEEK_SET ); temp = QPMR_SGPE_HCODE_LEN_VAL; temp = htonl(temp); fwrite(&temp, sizeof(uint32_t), 1, pMainImage ); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index ba4d7df6..6e9d1df8 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -55,8 +55,9 @@ extern "C" { #include "ipc_async_cmd.h" #include "ipc_messages.h" -#include "p9_stop_common.h" +#include "p9_hcode_image_defines.H" #include "p9_pm_hcd_flags.h" +#include "p9_stop_common.h" #if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX || FUSED_CORE_MODE_SCAN_FIX #define EXTRACT_RING_BITS(mask, ring, save) save = (ring) & (mask); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index 9e304718..0dcd7287 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -25,7 +25,6 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_enter_marks.h" -#include "p9_hcode_image_defines.H" extern SgpeStopRecord G_sgpe_stop_record; @@ -567,7 +566,7 @@ p9_sgpe_stop_entry() } // disable cme trace array - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET); + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR); if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(4)) { diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index 036a2551..77729fbf 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -25,7 +25,6 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_exit_marks.h" -#include "p9_hcode_image_defines.H" #include "p9_hcd_sgpe_boot_cme.h" #include "p9_dd1_doorbell_wr.h" @@ -429,7 +428,7 @@ p9_sgpe_stop_exit() // Reading fused core mode flag in cpmr header // To access memory, need to set MSB of homer address - cpmrHeader_t* pCpmrHdrAddr = (cpmrHeader_t*)(CPMR_BASE_HOMER_OFFSET | BIT32(0)); + cpmrHeader_t* pCpmrHdrAddr = (cpmrHeader_t*)(HOMER_CPMR_HEADER_ADDR); if (pCpmrHdrAddr->fusedModeStatus == 0xBB) { @@ -786,7 +785,7 @@ p9_sgpe_stop_exit() // xor error_stage_lt(0); // mask = 0 and pattern = 1 and may be trigger 0 - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET); + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR); if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(4)) { diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C index 5b7c0c12..fe4beadb 100755 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C @@ -28,9 +28,6 @@ #include "p9_hcode_image_defines.H" - -const uint32_t SGPE_SRAM_BASE = 0xFFF30000; -const uint32_t SGPE_IMAGE_HEADER_OFFSET = 0x180; /// /// @brief This is a plat specific (SGPE Plat) function that locates the /// Ring Container in the image and calls the functin to decompress the @@ -62,8 +59,7 @@ fapi2::ReturnCode findRS4InImageAndApply( getRingProperties(i_ringID, &l_torOffset, &l_ringType); - sgpeHeader_t* l_hcodeLayout = (sgpeHeader_t*)(SGPE_SRAM_BASE + - SGPE_IMAGE_HEADER_OFFSET); + sgpeHeader_t* l_hcodeLayout = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR); l_chipletData = g_eqData; @@ -77,7 +73,7 @@ fapi2::ReturnCode findRS4InImageAndApply( } l_sectionAddr = - (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_spec_ring_occ_offset); + (uint32_t*)(OCC_SRAM_SGPE_BASE_ADDR + l_hcodeLayout->g_sgpe_spec_ring_occ_offset); if ( l_chipletID >= l_chipletData.iv_base_chiplet_number) { @@ -102,7 +98,7 @@ fapi2::ReturnCode findRS4InImageAndApply( } l_sectionAddr = - (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_cmn_ring_occ_offset); + (uint32_t*)(OCC_SRAM_SGPE_BASE_ADDR + l_hcodeLayout->g_sgpe_cmn_ring_occ_offset); l_ringTorAddr = reinterpret_cast<uint16_t*>(l_sectionAddr) + (l_torOffset); @@ -134,7 +130,7 @@ fapi2::ReturnCode findRS4InImageAndApply( } l_sectionAddr = - (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_cmn_ring_ovrd_occ_offset); + (uint32_t*)(OCC_SRAM_SGPE_BASE_ADDR + l_hcodeLayout->g_sgpe_cmn_ring_ovrd_occ_offset); l_ringTorAddr = reinterpret_cast<uint16_t*>(l_sectionAddr) + (l_torOffset); diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index 0b52addc..2fe6d769 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -325,7 +325,8 @@ StopReturnCode_t lookUpSprInImage( uint32_t* i_pThreadSectLoc, void** io_pSprEntryLoc ) { StopReturnCode_t l_rc = STOP_SAVE_FAIL; - uint32_t temp = i_isCoreReg ? CORE_SPR_SECTN_SIZE : THREAD_SECTN_SIZE; + uint32_t temp = i_isCoreReg ? uint32_t(CORE_RESTORE_CORE_AREA_SIZE) : + uint32_t(CORE_RESTORE_THREAD_AREA_SIZE); uint32_t* i_threadSectEnd = i_pThreadSectLoc + temp; uint32_t bctr_inst = SWIZZLE_4_BYTE(BLR_INST); *io_pSprEntryLoc = NULL; @@ -967,7 +968,7 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, if( P9_STOP_SECTION_CORE_SCOM == i_section ) { - memset( pScomEntry, 0x00, SCOM_SIZE_PER_CORE ); + memset( pScomEntry, 0x00, CORE_SCOM_RESTORE_SIZE_PER_CORE ); } break; diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H b/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H index bb2534cb..4903d5ce 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H @@ -39,7 +39,7 @@ #include <endian.h> #endif -#include "p9_stop_section_defines.H" +#include "p9_hcd_memmap_base.H" #ifdef __FAPI_2_ #include <fapi2.H> @@ -52,6 +52,12 @@ namespace stopImageSection { #endif +enum +{ + MAX_SPR_RESTORE_INST = 0x08, + SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), +}; + typedef struct { uint32_t scomEntryHeader; @@ -64,8 +70,8 @@ typedef struct */ typedef struct { - uint8_t threadArea[THREAD_AREA_SIZE]; - uint8_t coreArea[CORE_SPR_SECTN_SIZE]; + uint8_t threadArea[CORE_RESTORE_THREAD_AREA_SIZE]; + uint8_t coreArea[CORE_RESTORE_CORE_AREA_SIZE]; } SprRestoreArea_t; /** @@ -76,10 +82,10 @@ typedef struct typedef struct { uint8_t occ_host_sgpe_area[ TWO_MB ]; // CPU restore area starts at an offset of 2MB from chip HOMER - uint8_t interrruptHandler[INTERRUPT_HANDLER_SIZE]; + uint8_t interrruptHandler[SELF_RESTORE_INT_SIZE]; uint8_t threadLauncher[THREAD_LAUNCHER_SIZE]; - SprRestoreArea_t coreThreadRestore[MAX_CORE_ID_SUPPORTED + 1][MAX_THREAD_ID_SUPPORTED + 1]; - uint8_t reserve[(ONE_KB * ONE_KB) - SPR_RESTORE_PER_CHIP]; + SprRestoreArea_t coreThreadRestore[MAX_CORES_PER_CHIP][MAX_THREADS_PER_CORE]; + uint8_t reserve[(ONE_KB * ONE_KB) - SELF_RESTORE_SIZE_TOTAL]; } HomerSection_t; /** @@ -121,15 +127,15 @@ enum #define CORE_ID_SCOM_START(io_image,\ i_chipletId) \ -((ScomEntry_t*)(((uint8_t*)(io_image))+ CORE_SCOM_SECTN_START +\ +((ScomEntry_t*)(((uint8_t*)(io_image)) + CORE_SCOM_RESTORE_HOMER_OFFSET +\ ((i_chipletId - CORE_CHIPLET_ID_MIN) * \ - SCOM_SIZE_PER_CORE))); + CORE_SCOM_RESTORE_SIZE_PER_CORE))); #define CACHE_SECTN_START(io_image,\ i_chipletId) \ -((StopCacheSection_t *)(((uint8_t *)(io_image))+CACHE_SCOM_SECTN_START \ - + ( i_chipletId - CACHE_CHIPLET_ID_MIN ) * \ - SCOM_SIZE_PER_CACHE_CHIPLET )); +((StopCacheSection_t *)(((uint8_t *)(io_image)) + QUAD_SCOM_RESTORE_HOMER_OFFSET +\ + ((i_chipletId - CACHE_CHIPLET_ID_MIN) * \ + QUAD_SCOM_RESTORE_SIZE_PER_QUAD))); #ifdef __cplusplus } // extern "C" diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C b/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C index 728a6aba..818fadf5 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C @@ -65,7 +65,7 @@ StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fusedMode ) HomerSection_t* pHomerDesc = ( HomerSection_t* ) i_pImage; HomerImgDesc_t* pHomer = (HomerImgDesc_t*)( pHomerDesc->interrruptHandler ); - if( SWIZZLE_8_BYTE(CPMR_MAGIC_WORD) != pHomer->cpmrMagicWord ) + if( SWIZZLE_8_BYTE(CPMR_MAGIC_NUMBER) != pHomer->cpmrMagicWord ) { MY_ERR("corrupt or invalid HOMER image location 0x%016llx", SWIZZLE_8_BYTE(pHomer->cpmrMagicWord) ); @@ -73,13 +73,13 @@ StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fusedMode ) break; } - if( (uint8_t) FUSED_MODE == pHomer->fusedModeStatus ) + if( (uint8_t) FUSED_CORE_MODE == pHomer->fusedModeStatus ) { *o_fusedMode = true; break; } - if( (uint8_t) NONFUSED_MODE == pHomer->fusedModeStatus ) + if( (uint8_t) NONFUSED_CORE_MODE == pHomer->fusedModeStatus ) { break; } |
