HB: fix HB core boot resulting cme boot

Change-Id: Ic2b36106a2423cdad267a8e54e9cd8f021487455
Original-Change-Id: I18f7c24dc84536126a90a251ae770b0498b5d3d0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31138
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

2 files changed, 24 insertions, 11 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index b4a61034..827dd7a2 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -95,6 +95,7 @@ extern "C" {
 #define EQ_QPPM_QCCR_WOR         0x100F01BF
 
 #define EX_NCU_STATUS_REG        0x1001100F
+#define EX_L3_MODE_REG0          0x1001182B
 #define EX_L3_MODE_REG1          0x1001180A
 #define EX_DRAM_REF_REG          0x1001180F
 #define EX_PM_PURGE_REG          0x10011813
@@ -155,11 +156,12 @@ enum SGPE_STOP_EVENT_LEVELS
 
 enum SGPE_STOP_CME_FLAGS
 {
+    CME_EX1_INDICATOR                 = BIT64(26),
+    CME_SIBLING_FUNCTIONAL            = BIT64(27),
     CME_CORE0_ENTRY_FIRST             = BIT64(28),
     CME_CORE1_ENTRY_FIRST             = BIT64(29),
     CME_CORE0_ENABLE                  = BIT64(30),
-    CME_CORE1_ENABLE                  = BIT64(31),
-    CME_EX1_INDICATOR                 = BIT64(26)
+    CME_CORE1_ENABLE                  = BIT64(31)
 };
 
 enum SGPE_STOP_PSCOM_MASK
@@ -184,6 +186,17 @@ enum SGPE_STOP_VECTOR_INDEX
 #define RESTORE_RING_BITS(mask, ring, save) ring = (((ring) & (~mask)) | (save));
 #endif
 
+/// 64bits data
+typedef union
+{
+    uint64_t value;
+    struct
+    {
+        uint32_t upper;
+        uint32_t lower;
+    } words;
+} data64_t;
+
 typedef struct
 {
     // requested stop state calculated from core stop levels
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index ebbbeed3..26e85115 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -665,6 +665,9 @@ p9_sgpe_stop_entry()
         PK_TRACE("Assert cache chiplet fence via NET_CTRL0[18]");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(18));
 
+        PK_TRACE("Switch glsmux to refclk to save clock grid power via CGCR[3]");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, qloop), 0);
+
         PK_TRACE("Clear SCAN_REGION prior to stop cache clocks");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SCAN_REGION_TYPE, qloop), 0);
 
@@ -694,12 +697,6 @@ p9_sgpe_stop_entry()
             pk_halt();
         }
 
-        // MF: verify compiler generate single rlwmni
-        // MF: delay may be needed for stage latch to propagate thold
-
-        PK_TRACE("Switch glsmux to refclk to save clock grid power via CGCR[3]");
-        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, qloop), 0);
-
         PK_TRACE("Assert vital fence via CPLT_CTRL1[3]");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), BIT64(3));
 
@@ -712,6 +709,9 @@ p9_sgpe_stop_entry()
                      ((uint64_t)ex << SHIFT64(9)) |
                      ((uint64_t)ex << SHIFT64(13))));
 
+        PK_TRACE("Drop CME_INTERPPM_DPLL_ENABLE after DPLL is stopped via QPMMR[26]");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_CLR, qloop), BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26));
+
         /// @todo add VDM_ENABLE attribute control
         PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_CLR, qloop), BIT64(0));
@@ -787,6 +787,9 @@ p9_sgpe_stop_entry()
         PK_TRACE("Assert electrical fence via NET_CTRL0[26]");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(26));
 
+        PK_TRACE("Drop sram_enable via NET_CTRL0[23]");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, qloop), ~BIT64(23));
+
         PK_TRACE("Assert vital thold via NET_CTRL0[16]");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(16));
 
@@ -864,9 +867,6 @@ p9_sgpe_stop_entry()
 
 #endif
 
-        PK_TRACE("Drop CME_INTERPPM_DPLL_ENABLE after DPLL is stopped via QPMMR[26]");
-        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_CLR, qloop), BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26));
-
         G_sgpe_stop_record.state[qloop].act_state_q = STOP_LEVEL_11;
 
         for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)