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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-12-23 02:02:51 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:15:24 -0500 |
| commit | 39a08f23402c40b42f42964f92fdb093c77a73cc (patch) | |
| tree | 0733a2b5aa8061a0681c9dba8971bb489929de4c | |
| parent | 7778509972ad832915e3faca708ed4449ea7259d (diff) | |
| download | talos-hcode-39a08f23402c40b42f42964f92fdb093c77a73cc.tar.gz talos-hcode-39a08f23402c40b42f42964f92fdb093c77a73cc.zip | |
PM: Updated QPMR and SGPE Header with 24x7 offset and length.
Change-Id: Idfcca3888ad1446a9e5130538e8270adc44e2631
RTC:164313
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34192
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
4 files changed, 19 insertions, 13 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index b3705de5..aee54b37 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -157,8 +157,8 @@ HCD_CONST(QPMR_QUAD_SPECIFIC_RINGS_OFFSET_BYTE, 0x40) HCD_CONST(QPMR_QUAD_SPECIFIC_RINGS_LENGTH_BYTE, 0x44) HCD_CONST(QPMR_QUAD_SCOM_RESTORE_OFFSET_BYTE, 0x48) HCD_CONST(QPMR_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x4C) -HCD_CONST(QPMR_24x7_DATA_OFFSET_BYTE, 0x50) -HCD_CONST(QPMR_24x7_DATA_LENGTH_BYTE, 0x54) +HCD_CONST(QPMR_AUX_DATA_OFFSET_BYTE, 0x50) +HCD_CONST(QPMR_AUX_DATA_LENGTH_BYTE, 0x54) HCD_CONST(QPMR_STOP_FFDC_OFFSET_BYTE, 0x58) HCD_CONST(QPMR_STOP_FFDC_LENGTH_BYTE, 0x5C) @@ -202,9 +202,9 @@ HCD_CONST(SGPE_QUAD_SPECIFIC_RING_SRAM_OFF_BYTE, 0x30) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_SRAM_OFF_BYTE, 0x34) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_MEM_OFF_BYTE, 0x38) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x3C) -HCD_CONST(SGPE_24x7_DATA_OFFSET_BYTE, 0x40) -HCD_CONST(SGPE_24x7_DATA_LENGTH_BYTE, 0x44) -HCD_CONST(PGPE_24x7_CTRL_BYTE, 0x48) +HCD_CONST(SGPE_AUX_DATA_OFFSET_BYTE, 0x40) +HCD_CONST(SGPE_AUX_DATA_LENGTH_BYTE, 0x44) +HCD_CONST(PGPE_AUX_CTRL_BYTE, 0x48) HCD_CONST(SGPE_RESET_ADDR_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_SYSTEM_RESET_ADDR_BYTE)) HCD_CONST(SGPE_BUILD_DATE_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_DATE_BYTE)) @@ -217,6 +217,9 @@ HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) HCD_CONST(SGPE_CME_INSTRUCTION_TRACE_BIT_POS, 0x08000000) HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS, 0x00008000) +///24x7 +HCD_CONST(QPMR_AUX_OFFSET, (512 * ONE_KB)) +HCD_CONST(QPMR_AUX_LENGTH, (64 * ONE_KB)) /// SGPE Hcode HCD_CONST(SGPE_HCODE_IMAGE_OFFSET, (SGPE_INT_VECTOR_SIZE + SGPE_HEADER_SIZE)) diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H index c8afefd4..2e6062f3 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H @@ -59,6 +59,7 @@ HCD_CONST(HOMER_SGPE_BOOT_LOADER_LENGTH_ADDR, (HOMER_QPMR_HEADER_ADDR + QPMR_BOOT_LOADER_LENGTH_BYTE)) HCD_CONST(HOMER_SGPE_BOOT_COPIER_ADDR, (HOMER_QPMR_HEADER_ADDR + QPMR_HEADER_SIZE)) +HCD_CONST(HOMER_AUX_BASE_ADDR, (HOMER_QPMR_BASE_ADDR + QPMR_AUX_OFFSET)) /// CPMR diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 7fddfa31..57d34d3e 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -90,8 +90,8 @@ HCD_HDR_UINT32( quadSpecRingOffset, 0); HCD_HDR_UINT32( quadSpecRingLength, 0); HCD_HDR_UINT32( quadScomOffset, 0); HCD_HDR_UINT32( quadScomLength, 0); -HCD_HDR_UINT32( quad24x7Offset, 0); -HCD_HDR_UINT32( quad24x7Length, 0); +HCD_HDR_UINT32( quadAuxOffset, 0); +HCD_HDR_UINT32( quadAuxLength, 0); HCD_HDR_UINT32( stopFfdcOffset, 0); HCD_HDR_UINT32( stopFfdcLength, 0); HCD_HDR_PAD(512); @@ -229,8 +229,10 @@ HCD_HDR_UINT32(g_sgpe_spec_ring_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_scom_offset, 0); HCD_HDR_UINT32(g_sgpe_scom_mem_offset, 0); HCD_HDR_UINT32(g_sgpe_scom_mem_length, 0); -HCD_HDR_UINT32(g_sgpe_24x7_offset, 0); -HCD_HDR_UINT32(g_sgpe_24x7_length, 0); +HCD_HDR_UINT32(g_sgpe_aux_offset, 0); +HCD_HDR_UINT32(g_sgpe_aux_length, 0); +HCD_HDR_UINT32(g_sgpe_aux_control, 0); +HCD_HDR_UINT32(g_sgpe_reserve4, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm diff --git a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h index 53caabb1..d560fd24 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h +++ b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h @@ -66,8 +66,8 @@ typedef union occ_flags uint32_t sgpe_StopExitsIgnored : 1; uint32_t sgpe_StopEntryIgnored : 1; uint32_t reserved2 : 1; - uint32_t sgpe_24x7_Activate : 1; - uint32_t sgpe_24x7_Active : 1; + uint32_t sgpe_Aux_Activate : 1; + uint32_t sgpe_Aux_Active : 1; uint32_t pib_I2CMasterEngine1Lock : 2; uint32_t pib_I2CMasterEngine2Lock : 2; uint32_t pib_I2CMasterEngine3Lock : 2; @@ -81,8 +81,8 @@ typedef union occ_flags uint32_t pib_I2CMasterEngine3Lock : 2; uint32_t pib_I2CMasterEngine2Lock : 2; uint32_t pib_I2CMasterEngine1Lock : 2; - uint32_t sgpe_24x7_Active : 1; - uint32_t sgpe_24x7_Activate : 1; + uint32_t sgpe_Aux_Active : 1; + uint32_t sgpe_Aux_Activate : 1; uint32_t reserved2 : 1; uint32_t sgpe_StopEntryIgnored : 1; uint32_t sgpe_StopExitsIgnored : 1; |
