PGPE: Use global literals for reg addrs

    Key_Cronus_Test=PM_REGRESS

Change-Id: I1e38eca3b888dde64b953e977efff887013dbd5e
CQ: SW428872
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58540
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

12 files changed, 141 insertions, 102 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c
index c779c19a..d7beb770 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c
@@ -87,7 +87,7 @@ uint8_t pollVoltageTransDone(void)
     uint32_t  ocbRegReadData = 0;
     uint8_t   ongoingFlag = 1;
     uint8_t   count = 0;
-    uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
+    uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
 
     // The point of MAX_POLL_COUNT_AVS is to verify that ongoingFlag turns to
     //   zero very fast. Otherwise, something wrong with this i/f and error out.
@@ -124,7 +124,7 @@ uint8_t driveIdleFrame(void)
 {
     uint8_t  rc = 0;
     uint32_t idleframe = 0xFFFFFFFF;
-    uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
+    uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
 
     // Clear sticky bits in o2s_status_reg
     out32(OCB_O2SCMD0A | BusMask , 0x40000000);
@@ -148,12 +148,12 @@ uint8_t driveWrite(uint32_t CmdDataType, uint32_t CmdData)
     uint32_t ocbRegWriteData = 0;
     uint32_t ocbRegReadData = 0;
 
-    uint32_t RailSelect  =  in32(OCB_OCCS2) & AVS_RAIL_NUM_MASK;
+    uint32_t RailSelect  =  in32(G_OCB_OCCS2) & AVS_RAIL_NUM_MASK;
     uint32_t StartCode   = 1;
     uint32_t CmdType     = 0; // 0:write+commit, 1:write+hold, 2: d/c, 3:read
     uint32_t CmdGroup    = 0;
     uint32_t CRC         = 0;
-    uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
+    uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
 
     // Clear sticky bits in o2s_status_reg
     out32(OCB_O2SCMD0A | BusMask, 0x40000000);
@@ -228,14 +228,14 @@ uint8_t driveRead(uint32_t CmdDataType, uint32_t* CmdData)
     uint32_t ocbRegReadData = 0;
     uint32_t ocbRegWriteData = 0;
 
-    uint32_t RailSelect  =  in32(OCB_OCCS2) & AVS_RAIL_NUM_MASK;
+    uint32_t RailSelect  =  in32(G_OCB_OCCS2) & AVS_RAIL_NUM_MASK;
     uint32_t StartCode   = 1;
     uint32_t CmdType     = 3; // 0:write+commit, 1:write+hold, 2: d/c, 3:read
     uint32_t CmdGroup    = 0;
     uint32_t Reserved    = 0xFFFF;
     uint32_t CRC         = 0;
 
-    uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
+    uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
 
     // Clear sticky bits in o2s_status_reg
     out32(OCB_O2SCMD0A | BusMask, 0x40000000);
@@ -328,7 +328,7 @@ void external_voltage_control_init(uint32_t* vext_read_mv)
     // OCI to SPIPMBus (O2S) bridge initialization
     //
 
-    uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
+    uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
 
     // O2SCTRLF
     ocbRegReadData = in32(OCB_O2SCTRLF0A | BusMask);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
index 202bc115..056e58aa 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
@@ -112,7 +112,7 @@ enum PGPE_WOF_CTRL
     (QUAD0_EX1_MASK >> (q*2))
 
 #define PGPE_OPTIONAL_TRACE_AND_PANIC(panic_code) \
-    if (in32(OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) { \
+    if (in32(G_OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) { \
         G_pgpe_optrace_data.word[0] = panic_code; \
         p9_pgpe_optrace(HALT_CONDITION ); \
         PK_PANIC(panic_code); }
@@ -123,6 +123,19 @@ enum PGPE_WOF_CTRL
     PK_PANIC(panic_code);
 
 
+extern uint32_t G_OCB_QCSR;
+extern uint32_t G_OCB_OCCS2;
+extern uint32_t G_OCB_OCCFLG;
+extern uint32_t G_OCB_OCCFLG_OR;
+extern uint32_t G_OCB_OCCFLG_CLR;
+extern uint32_t G_OCB_OCCFLG2;
+extern uint32_t G_OCB_OISR0_CLR;
+extern uint32_t G_OCB_OIMR1_OR;
+extern uint32_t G_OCB_OIMR1_CLR;
+extern uint32_t G_OCB_OIMR0_OR;
+extern uint32_t G_OCB_OIMR0_CLR;
+
+
 /// PGPE PState
 void p9_pgpe_irq_handler_occ_sgpe_cme_pvref_error(void* arg, PkIrqId irq);
 void p9_pgpe_irq_handler_system_xstop(void* arg, PkIrqId irq);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
index ca5fbd61..60261ff1 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
@@ -113,7 +113,7 @@ void p9_pgpe_fit_init()
 
 __attribute__((always_inline)) inline void handle_core_throttle()
 {
-    uint32_t config = in32(OCB_OCCS2); //bits 16-18 in OCC Scratch Register 2
+    uint32_t config = in32(G_OCB_OCCS2); //bits 16-18 in OCC Scratch Register 2
     uint32_t run = (config >> 14) & 0x3; //this looks at the inject and enable bits, if either are high we run
 
     if(run) //Currently running
@@ -146,7 +146,7 @@ __attribute__((always_inline)) inline void handle_core_throttle()
 
             if(inject == 1)
             {
-                out32(OCB_OCCS2, (config & 0xFFFFBFFF)); //write out to indicate inject has finished
+                out32(G_OCB_OCCS2, (config & 0xFFFFBFFF)); //write out to indicate inject has finished
             }
         }
 
@@ -169,7 +169,7 @@ __attribute__((always_inline)) inline void handle_quad_hb_update()
 {
     uint32_t q;
     ocb_qcsr_t qcsr;
-    qcsr.value = in32(OCB_QCSR);
+    qcsr.value = in32(G_OCB_QCSR);
 
     for (q = 0; q < MAX_QUADS; q++)
     {
@@ -209,9 +209,9 @@ __attribute__((always_inline)) inline void handle_occflg_requests()
 {
     ocb_occflg_t occFlag;
     //Read OCC_FLAGS
-    occFlag.value = in32(OCB_OCCFLG);
+    occFlag.value = in32(G_OCB_OCCFLG);
 
-    if(in32(OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_FIT_ERR_INJ))
+    if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_FIT_ERR_INJ))
     {
         PK_TRACE_ERR("FIT_IPC_ERROR_INJECT TRAP");
         PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
@@ -243,9 +243,9 @@ __attribute__((always_inline)) inline void handle_occflg_requests()
                 //set error bit
                 if(G_pgpe_pstate_record.pstatesStatus != PSTATE_ACTIVE)
                 {
-                    uint32_t occScr2 = in32(OCB_OCCS2);
+                    uint32_t occScr2 = in32(G_OCB_OCCS2);
                     occScr2 |= BIT32(PGPE_SAFE_MODE_ERROR);
-                    out32(OCB_OCCS2, occScr2);
+                    out32(G_OCB_OCCS2, occScr2);
                 }
                 //Otherwise, process safe mode request
                 else
@@ -269,9 +269,9 @@ __attribute__((always_inline)) inline void handle_occflg_requests()
 //number of FIT interrupts
 __attribute__((always_inline)) inline void handle_aux_task()
 {
-    if(in32(OCB_OCCFLG) & BIT32(AUX_THREAD_ACTIVATE))
+    if(in32(G_OCB_OCCFLG) & BIT32(AUX_THREAD_ACTIVATE))
     {
-        out32(OCB_OCCFLG_OR, BIT32(AUX_THREAD_ACTIVE));
+        out32(G_OCB_OCCFLG_OR, BIT32(AUX_THREAD_ACTIVE));
 
         if(G_aux_task_count == G_aux_task_count_threshold)
         {
@@ -285,7 +285,7 @@ __attribute__((always_inline)) inline void handle_aux_task()
     }
     else
     {
-        out32(OCB_OCCFLG_CLR, BIT32(AUX_THREAD_ACTIVE));
+        out32(G_OCB_OCCFLG_CLR, BIT32(AUX_THREAD_ACTIVE));
     }
 }
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c
index c717b09a..d36cc67c 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c
@@ -153,7 +153,7 @@ void p9_pgpe_ipc_405_set_pmcr(ipc_msg_t* cmd, void* arg)
 {
     PK_TRACE_INF("IPC: Set PMCR");
 
-    if(in32(OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
+    if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
     {
         PK_TRACE_ERR("SET PMCR IPC ERROR INJECT TRAP");
         PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.c
index e7fcbfab..ffad2e34 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.c
@@ -173,8 +173,8 @@ void pk_irq_save_and_set_mask(uint32_t iPrtyLvl)
     //  the OIMR to a known value when we exit our thread.
     if (++g_oimr_stack_ctr < NUM_EXT_IRQ_PRTY_LEVELS)
     {
-        //prev: g_oimr_stack[g_oimr_stack_ctr] = ((uint64_t)in32(OCB_OIMR0))<<32 |
-        //                                 (uint64_t)in32(OCB_OIMR1);
+        //prev: g_oimr_stack[g_oimr_stack_ctr] = ((uint64_t)in32(G_OCB_OIMR0))<<32 |
+        //                                 (uint64_t)in32(G_OCB_OIMR1);
         // Make a note of present prty level and then update tracker to new prty level.
         g_oimr_stack[g_oimr_stack_ctr] = g_current_prty_level;
         g_current_prty_level = iPrtyLvl; // Update prty level tracker.
@@ -192,16 +192,16 @@ void pk_irq_save_and_set_mask(uint32_t iPrtyLvl)
     // This includes all those IRQs which belong to this instance as well as
     // those high-prty IRQs shared with the other instances.
     //
-    out32(OCB_OIMR0_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS >> 32));
-    out32(OCB_OIMR1_CLR, (uint32_t)IRQ_VEC_ALL_OUR_IRQS);
+    out32(G_OCB_OIMR0_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS >> 32));
+    out32(G_OCB_OIMR1_CLR, (uint32_t)IRQ_VEC_ALL_OUR_IRQS);
 
     // Second, mask IRQs belonging to this task and lower prty tasks.
     // Note, that we do not modify the permanently disabled IRQs, such as the
     //  _RESERVED_ ones. Nor do we touch other instances' IRQs. Iow, the
     //  IDX_PRTY_LVL_DISABLED mask is  NOT  part of the mask we apply below.
-    out32(OCB_OIMR0_OR, (uint32_t)((ext_irq_vectors_gpe[iPrtyLvl][IDX_MASK_VEC] |
-                                    g_oimr_override) >> 32) );
-    out32(OCB_OIMR1_OR, (uint32_t)(ext_irq_vectors_gpe[iPrtyLvl][IDX_MASK_VEC] |
-                                   g_oimr_override) );
+    out32(G_OCB_OIMR0_OR, (uint32_t)((ext_irq_vectors_gpe[iPrtyLvl][IDX_MASK_VEC] |
+                                      g_oimr_override) >> 32) );
+    out32(G_OCB_OIMR1_OR, (uint32_t)(ext_irq_vectors_gpe[iPrtyLvl][IDX_MASK_VEC] |
+                                     g_oimr_override) );
 
 }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h
index f74619ab..d3a474e2 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h
@@ -44,6 +44,11 @@
 #ifndef _P9_PGPE_IRQ_H_
 #define _P9_PGPE_IRQ_H_
 
+extern uint32_t G_OCB_OIMR1_OR;
+extern uint32_t G_OCB_OIMR1_CLR;
+extern uint32_t G_OCB_OIMR0_OR;
+extern uint32_t G_OCB_OIMR0_CLR;
+
 // We define four levels of TRACE outputs:
 // _INF:  Trace level used for main informational events.
 // _DBG:  Trace level used for expanded debugging.
@@ -114,14 +119,14 @@ pk_irq_vec_restore( PkMachineContext* context)
 
     if (g_oimr_stack_ctr >= 0)
     {
-        out32( OCB_OIMR0_CLR, (uint32_t)((IRQ_VEC_ALL_OUR_IRQS |
-                                          g_oimr_override_stack[g_oimr_stack_ctr]) >> 32));
-        out32( OCB_OIMR1_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS |
-                                         g_oimr_override_stack[g_oimr_stack_ctr]));
-        out32( OCB_OIMR0_OR,
+        out32( G_OCB_OIMR0_CLR, (uint32_t)((IRQ_VEC_ALL_OUR_IRQS |
+                                            g_oimr_override_stack[g_oimr_stack_ctr]) >> 32));
+        out32( G_OCB_OIMR1_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS |
+                                           g_oimr_override_stack[g_oimr_stack_ctr]));
+        out32( G_OCB_OIMR0_OR,
                (uint32_t)((ext_irq_vectors_gpe[g_oimr_stack[g_oimr_stack_ctr]][IDX_MASK_VEC] |
                            g_oimr_override) >> 32));
-        out32( OCB_OIMR1_OR,
+        out32( G_OCB_OIMR1_OR,
                (uint32_t)(ext_irq_vectors_gpe[g_oimr_stack[g_oimr_stack_ctr]][IDX_MASK_VEC] |
                           g_oimr_override));
         // Restore the prty level tracker to the task that was interrupted, if any.
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
index 12775772..4f6a0d11 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
@@ -56,8 +56,8 @@ void p9_pgpe_irq_init()
     p9_pgpe_ocb_hb_error_init();
 
     //Setup SGPE_ERR(OISR[8]) and PVREF_ERR(OISR[20])
-    out32(OCB_OISR0_CLR, BIT32(8) | BIT32(20));//Clear any pending interrupts
-    out32(OCB_OIMR0_CLR, BIT32(8) | BIT32(20));//Unmask interrupts
+    out32(G_OCB_OISR0_CLR, BIT32(8) | BIT32(20));//Clear any pending interrupts
+    out32(G_OCB_OIMR0_CLR, BIT32(8) | BIT32(20));//Unmask interrupts
 }
 
 //
@@ -86,8 +86,8 @@ void p9_pgpe_ocb_hb_error_init()
 
     out64(OCB_OCCHBR, 0); //Clear and Disable OCC Heartbeat Register
     GPE_PUTSCOM(OCB_OCCLFIR_AND, ~BIT64(OCC_HB_ERROR_FIR));
-    out32(OCB_OISR0_CLR, BIT32(2));//Clear any pending interrupts
-    out32(OCB_OIMR0_CLR, BIT32(2));//Unmask interrupt
+    out32(G_OCB_OISR0_CLR, BIT32(2));//Clear any pending interrupts
+    out32(G_OCB_OIMR0_CLR, BIT32(2));//Unmask interrupt
 }
 
 //
@@ -145,7 +145,7 @@ void p9_pgpe_irq_handler_ocb_err()
 
     PK_TRACE_INF("OCB FIR Detected");
 
-    out32(OCB_OISR0_CLR, BIT32(2));
+    out32(G_OCB_OISR0_CLR, BIT32(2));
 
     PGPE_OPTIONAL_TRACE_AND_PANIC(PGPE_OCC_FIR_IRQ);
 
@@ -188,8 +188,8 @@ void p9_pgpe_irq_handler_sgpe_err()
     PK_TRACE_INF("SGPE Error");
 
     g_oimr_override |=   BIT64(8);
-    out32(OCB_OIMR0_OR,  BIT32(8));
-    out32(OCB_OISR0_CLR, BIT32(8));
+    out32(G_OCB_OIMR0_OR,  BIT32(8));
+    out32(G_OCB_OISR0_CLR, BIT32(8));
 
     //Optrace
     G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
@@ -226,7 +226,7 @@ void p9_pgpe_irq_handler_pvref_err()
 {
     PK_TRACE_INF("PVREF Error");
 
-    out32(OCB_OISR0_CLR, BIT32(20));
+    out32(G_OCB_OISR0_CLR, BIT32(20));
 
     //Optrace
     G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
@@ -265,8 +265,8 @@ void p9_pgpe_irq_handler_system_xstop(void* arg, PkIrqId irq)
     PkMachineContext  ctx;
 
     g_oimr_override |=   BIT64(15);
-    out32(OCB_OIMR0_OR,  BIT32(15));
-    out32(OCB_OISR0_CLR, BIT32(15));
+    out32(G_OCB_OIMR0_OR,  BIT32(15));
+    out32(G_OCB_OISR0_CLR, BIT32(15));
 
     //Optrace
     G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
@@ -296,7 +296,7 @@ void p9_pgpe_irq_handler_pcb_type1(void* arg, PkIrqId irq)
     uint32_t c;
     uint32_t opit1pra;
 
-    if(in32(OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
+    if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
     {
         PK_TRACE_ERR("PCB TYPE1 ERROR INJECT TRAP");
         PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
@@ -425,7 +425,7 @@ void p9_pgpe_irq_handler_cme_err()
     uint64_t value, baseVal;
     qppm_dpll_freq_t dpllFreq;
     ocb_qcsr_t qcsr;
-    qcsr.value = in32(OCB_QCSR);
+    qcsr.value = in32(G_OCB_QCSR);
     uint64_t cme_flags = 0;
 
     //Optrace
@@ -444,7 +444,7 @@ void p9_pgpe_irq_handler_cme_err()
     PK_TRACE_INF("CER:CME ERR opit5pr 0x%x", opit5pr);
 
     //If prolonged droop recovery is not active
-    if (!(in32(OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
+    if (!(in32(G_OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
     {
         p9_pgpe_pstate_write_core_throttle(CORE_IFU_THROTTLE, RETRY);
     }
@@ -564,7 +564,7 @@ void p9_pgpe_irq_handler_cme_err()
     }
 
     //If prolonged droop recovery is not active
-    if (!(in32(OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
+    if (!(in32(G_OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
     {
         p9_pgpe_pstate_write_core_throttle(CORE_THROTTLE_OFF, RETRY);
     }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
index 50953b25..cb246aab 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
@@ -72,6 +72,27 @@ PgpePstateRecord G_pgpe_pstate_record __attribute__((section (".dump_ptrs"))) =
 };
 
 
+//We define a global literal for these register addresses
+//This way compiler put them in .sdata area, and the address
+//can be loaded with one instruction using r13 as offset into
+//sdata area. The change helped save about 448 bytes of code space.
+//Note, some register's address were not moved to using global literals
+//because in some cases they registers are accessed few times or they are
+//used inside a loop. In both cases, either no code reduction was observed
+//or resulted in code increase.
+uint32_t G_OCB_QCSR = OCB_QCSR;
+uint32_t G_OCB_OCCS2 = OCB_OCCS2;
+uint32_t G_OCB_OCCFLG = OCB_OCCFLG;
+uint32_t G_OCB_OCCFLG_OR = OCB_OCCFLG_OR;
+uint32_t G_OCB_OCCFLG_CLR = OCB_OCCFLG_CLR;
+uint32_t G_OCB_OCCFLG2 = OCB_OCCFLG2;
+uint32_t G_OCB_OISR0_CLR = OCB_OISR0_CLR;
+uint32_t G_OCB_OIMR0_OR = OCB_OIMR0_OR;
+uint32_t G_OCB_OIMR1_OR = OCB_OIMR1_OR;
+uint32_t G_OCB_OIMR0_CLR = OCB_OIMR0_CLR;
+uint32_t G_OCB_OIMR1_CLR = OCB_OIMR1_CLR;
+
+
 EXTERNAL_IRQ_TABLE_START
 IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_DEBUGGER
 IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_TRACE_TRIGGER
@@ -193,7 +214,7 @@ main(int argc, char** argv)
                   timebase);
 
     // Read OCC_SCRATCH[PGPE_DEBUG_TRAP_ENABLE]
-    uint32_t occScr2 = in32(OCB_OCCS2);
+    uint32_t occScr2 = in32(G_OCB_OCCS2);
 
     if (occScr2 & BIT32(PGPE_DEBUG_TRAP_ENABLE))
     {
@@ -203,8 +224,8 @@ main(int argc, char** argv)
 
     PK_TRACE("Clear OCC LFIR[gpe2_halted] and OISR[gpe2_error and xstop] bits upon PGPE boot");
     GPE_PUTSCOM(OCB_OCCLFIR_AND, ~BIT64(24));
-    out32(OCB_OISR0_CLR, (BIT32(7) | BIT32(15)));
-    out32(OCB_OIMR0_CLR, (BIT32(7) | BIT32(15)));
+    out32(G_OCB_OISR0_CLR, (BIT32(7) | BIT32(15)));
+    out32(G_OCB_OIMR0_CLR, (BIT32(7) | BIT32(15)));
 
     // Initialize the thread control block for G_p9_pgpe_thread_process_requests
     pk_thread_create(&G_p9_pgpe_thread_process_requests,
@@ -265,7 +286,7 @@ main(int argc, char** argv)
     p9_pgpe_irq_init();
 
     g_oimr_override |= BIT64(49);
-    out32(OCB_OIMR1_OR, BIT32(17)); //Disable PCB_INTR_TYPE4
+    out32(G_OCB_OIMR1_OR, BIT32(17)); //Disable PCB_INTR_TYPE4
 
     p9_pgpe_optrace_init();
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_optrace.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_optrace.c
index b840d9fa..ad6f0521 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_optrace.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_optrace.c
@@ -65,7 +65,7 @@ void p9_pgpe_optrace_init() //sets up address and initializes buffer to 0's
 }
 void p9_pgpe_optrace(uint32_t mark)
 {
-    if(in32(OCB_OCCS2) & BIT32(PGPE_OP_TRACE_DISABLE)) //Check to see if tracing is enabled
+    if(in32(G_OCB_OCCS2) & BIT32(PGPE_OP_TRACE_DISABLE)) //Check to see if tracing is enabled
     {
         G_lastDisable = 1;
     }
@@ -102,7 +102,7 @@ void p9_pgpe_optrace(uint32_t mark)
             if(G_address == SRAM_ADDRESS_MAX - 0x4)
             {
                 if(G_pgpe_header_data->g_pgpe_doptrace_offset != 0 && G_pgpe_header_data->g_pgpe_doptrace_length != 0 &&
-                   in32(OCB_OCCS2) & BIT32(PGPE_OP_TRACE_MEM_MODE))
+                   in32(G_OCB_OCCS2) & BIT32(PGPE_OP_TRACE_MEM_MODE))
                 {
                     p9_pgpe_optrace_memcopy();
                 }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 16b8fec0..20de38c0 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -183,7 +183,7 @@ void p9_pgpe_pstate_setup_process_pcb_type4()
     out32(OCB_OPIT4PRA_CLR, opit4pr);
     out32(OCB_OISR1_CLR, BIT32(17));
     g_oimr_override &= ~BIT64(49);
-    out32(OCB_OIMR1_CLR, BIT32(17));
+    out32(G_OCB_OIMR1_CLR, BIT32(17));
 }
 
 //
@@ -637,7 +637,7 @@ void p9_pgpe_handle_nacks(uint32_t origTargetCores, uint32_t origExpectedAckFrom
 
     //a. If OCC Scratch2 Core Throttle Continuous Change Enable bit is set (i.e. during Manufacturing test), halt the PGPE with a unique error code.
     //Engineering Note: characterization team is responsible to set CSAR bit "Disable CME NACK on Prolonged Droop" when doing PGPE throttle scom injection.
-    if(in32(OCB_OCCS2) & BIT32(CORE_THROTTLE_CONTINUOUS_CHANGE_ENABLE))
+    if(in32(G_OCB_OCCS2) & BIT32(CORE_THROTTLE_CONTINUOUS_CHANGE_ENABLE))
     {
         PGPE_TRACE_AND_PANIC(PGPE_DROOP_AND_CORE_THROTTLE_ENABLED);
     }
@@ -645,7 +645,7 @@ void p9_pgpe_handle_nacks(uint32_t origTargetCores, uint32_t origExpectedAckFrom
     //b) If  OCC flag PGPE Prolonged Droop Workaround Active bit is not set,
     //    call droop_throttle()
 
-    if (!(in32(OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
+    if (!(in32(G_OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
     {
         p9_pgpe_droop_throttle();
     }
@@ -680,7 +680,7 @@ void p9_pgpe_handle_nacks(uint32_t origTargetCores, uint32_t origExpectedAckFrom
             // 2 Set OCC Flag register PGPE PM Reset Suppress bit that OCC
             //  will read to tell OCC not to attempt a PM Complex reset on
             //  PGPE timeouts in the meantime.
-            out32(OCB_OCCFLG_OR, BIT32(PGPE_PM_RESET_SUPPRESS));
+            out32(G_OCB_OCCFLG_OR, BIT32(PGPE_PM_RESET_SUPPRESS));
 
             // 3 Send DB0 PMSR Update with message Set Pstates Suspended only
             // to the CME QM (and their Siblings) that provided an ACK
@@ -718,7 +718,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
     uint64_t value;
     db0_parms_t p;
 
-    qcsr.value = in32(OCB_QCSR);
+    qcsr.value = in32(G_OCB_QCSR);
 
     //1. Read DPLLs. Determine lowest DPLL
     lowestDpll = 0xFFF;
@@ -860,7 +860,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
         PK_TRACE_INF("PST: OWNER_CHAR");
         G_pgpe_pstate_record.pmcrOwner = PMCR_OWNER_CHAR;
         g_oimr_override &= ~(BIT64(46));
-        out32(OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
+        out32(G_OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
     }
 
     //7. Send Pstate Start Doorbell0
@@ -905,7 +905,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
     //In case VDM Prolonged Droop event occured during PSTATE_START, then clearing
     //ensures OCC is notified about Prolonged Droop event resolution.
     //Also, at this point nothing else should be pending from OCC, so safe to clear.
-    out32(OCB_OCCFLG_CLR, BIT32(PGPE_PM_RESET_SUPPRESS));
+    out32(G_OCB_OCCFLG_CLR, BIT32(PGPE_PM_RESET_SUPPRESS));
 
     //Lower voltage if boot voltage > syncPstate voltage
     if (G_pgpe_pstate_record.eVidCurr > G_pgpe_pstate_record.eVidNext)
@@ -920,10 +920,10 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
 
     //6. Enable PStates
     G_pgpe_pstate_record.pstatesStatus = PSTATE_ACTIVE;
-    uint32_t occScr2 = in32(OCB_OCCS2);
+    uint32_t occScr2 = in32(G_OCB_OCCS2);
     occScr2 |= BIT32(PGPE_PSTATE_PROTOCOL_ACTIVE);
     PK_TRACE_DBG("PST: PGPE_PSTATE_PROTOCOL_ACTIVE set");
-    out32(OCB_OCCS2, occScr2);
+    out32(G_OCB_OCCS2, occScr2);
 
     PK_TRACE_DBG("PST: Start Done");
 }
@@ -938,7 +938,7 @@ void p9_pgpe_pstate_set_pmcr_owner(uint32_t owner)
 {
     int q = 0;
     ocb_qcsr_t qcsr;
-    qcsr.value = in32(OCB_QCSR);
+    qcsr.value = in32(G_OCB_QCSR);
 
 //Write to LMCR register in SIMICS results in error
 //So, adding a build flag for SIMICS.
@@ -952,19 +952,19 @@ void p9_pgpe_pstate_set_pmcr_owner(uint32_t owner)
     {
         G_pgpe_pstate_record.pmcrOwner = PMCR_OWNER_HOST;
         g_oimr_override &= ~(BIT64(46));
-        out32(OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
+        out32(G_OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
     }
     else if (owner == PMCR_OWNER_OCC)
     {
         G_pgpe_pstate_record.pmcrOwner = PMCR_OWNER_OCC;
         g_oimr_override |= BIT64(46);
-        out32(OCB_OIMR1_OR, BIT32(14)); //Disable PCB_INTR_TYPE1
+        out32(G_OCB_OIMR1_OR, BIT32(14)); //Disable PCB_INTR_TYPE1
     }
     else if (owner == PMCR_OWNER_CHAR)
     {
         G_pgpe_pstate_record.pmcrOwner = PMCR_OWNER_CHAR;
         g_oimr_override &= ~(BIT64(46));
-        out32(OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
+        out32(G_OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
     }
 
 
@@ -1016,7 +1016,7 @@ void p9_pgpe_pstate_stop()
     ocb_qcsr_t qcsr;
     db0_parms_t p;
 
-    qcsr.value = in32(OCB_QCSR);
+    qcsr.value = in32(G_OCB_QCSR);
     db0_stop.value = 0;
     db0_stop.fields.msg_id = MSGID_DB0_STOP_PSTATE_BROADCAST;
 
@@ -1058,13 +1058,13 @@ void p9_pgpe_pstate_stop()
 
 
     //Set status in OCC_Scratch2
-    uint32_t occScr2 = in32(OCB_OCCS2);
+    uint32_t occScr2 = in32(G_OCB_OCCS2);
     occScr2 &= ~BIT32(PGPE_PSTATE_PROTOCOL_ACTIVE);
-    out32(OCB_OCCS2, occScr2);
+    out32(G_OCB_OCCS2, occScr2);
     G_pgpe_pstate_record.pstatesStatus = PSTATE_STOPPED;
 
     G_pgpe_optrace_data.word[0] = (START_STOP_FLAG << 24) | (G_pgpe_pstate_record.psComputed.fields.glb << 16)
-                                  | (in32(OCB_QCSR) >> 16);
+                                  | (in32(G_OCB_QCSR) >> 16);
     p9_pgpe_optrace(PRC_START_STOP);
 
     PK_TRACE_DBG("PSS: Stop Done");
@@ -1264,7 +1264,7 @@ void p9_pgpe_pstate_process_quad_entry_done(uint32_t quadsRequested)
     //If WOF Enabled, then interlock with OCC
     if(G_pgpe_pstate_record.wofStatus == WOF_ENABLED && G_pgpe_pstate_record.pstatesStatus == PSTATE_ACTIVE)
     {
-        GPE_PUTSCOM(OCB_OCCFLG_OR, BIT32(REQUESTED_ACTIVE_QUAD_UPDATE));//Set OCCFLG[REQUESTED_ACTIVE_QUAD_UPDATE]
+        GPE_PUTSCOM(G_OCB_OCCFLG_OR, BIT32(REQUESTED_ACTIVE_QUAD_UPDATE));//Set OCCFLG[REQUESTED_ACTIVE_QUAD_UPDATE]
     }
 
     G_pgpe_pstate_record.pendingActiveQuadUpdtDone = 0;
@@ -1428,10 +1428,10 @@ void p9_pgpe_pstate_apply_safe_clips()
 void p9_pgpe_pstate_safe_mode()
 {
     PK_TRACE_DBG("SAF: Safe Mode Enter");
-    uint32_t occScr2 = in32(OCB_OCCS2);
-    uint32_t suspend = in32(OCB_OCCFLG) & BIT32(PM_COMPLEX_SUSPEND)
+    uint32_t occScr2 = in32(G_OCB_OCCS2);
+    uint32_t suspend = in32(G_OCB_OCCFLG) & BIT32(PM_COMPLEX_SUSPEND)
                        && !(G_pgpe_pstate_record.severeFault[SAFE_MODE_FAULT_SGPE]);
-    uint32_t safemode = in32(OCB_OCCFLG) & BIT32(PGPE_SAFE_MODE);
+    uint32_t safemode = in32(G_OCB_OCCFLG) & BIT32(PGPE_SAFE_MODE);
     db3_parms_t p;
     pgpe_db0_glb_bcast_t db0;
 
@@ -1539,7 +1539,7 @@ void p9_pgpe_pstate_safe_mode()
     //Update OCC Scratch2  (need to get new value because the suspend_stop callback changes the Scratch2 content)
     occScr2 &= ~BIT32(PGPE_PSTATE_PROTOCOL_ACTIVE);
     occScr2 |= BIT32(PGPE_SAFE_MODE_ACTIVE);
-    out32(OCB_OCCS2, occScr2);
+    out32(G_OCB_OCCS2, occScr2);
 
     if (G_pgpe_pstate_record.severeFault[SAFE_MODE_FAULT_CME])
     {
@@ -1631,9 +1631,9 @@ void p9_pgpe_pstate_cme_fault()
     //5. Clears OCC Scratch 2 [PGPE Active].
     //  This keeps the SGPE from performing Update Active Cores and Update
     //  Active Quads IPC operations to PGPE in the future.
-    uint32_t occScr2 = in32(OCB_OCCS2);
+    uint32_t occScr2 = in32(G_OCB_OCCS2);
     occScr2 &= ~BIT32(PGPE_ACTIVE);
-    out32(OCB_OCCS2, occScr2);
+    out32(G_OCB_OCCS2, occScr2);
 
     //6. Responds to any Update Active Cores and Update Active Quads IPC
     //  operations.
@@ -2044,7 +2044,7 @@ inline void p9_pgpe_droop_throttle()
 
     uint32_t q;
     ocb_qcsr_t qcsr;
-    qcsr.value = in32(OCB_QCSR);
+    qcsr.value = in32(G_OCB_QCSR);
     uint64_t value;
     uint32_t ex;
 
@@ -2100,7 +2100,7 @@ inline void p9_pgpe_droop_throttle()
     p9_pgpe_pstate_write_core_throttle(CORE_IFU_THROTTLE, RETRY);
 
     //3.  Set the OCC flag PGPE Prolonged Droop Workaround Active bit.
-    out32(OCB_OCCFLG_OR, BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE));
+    out32(G_OCB_OCCFLG_OR, BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE));
 
     //4.  Clear the Prolonged Droop Global variables (Bit vector and retry counts).
     G_pgpe_pstate_record.cntNACKs = 0;
@@ -2151,7 +2151,7 @@ inline void p9_pgpe_droop_unthrottle()
 
     //4.  Clear the OCC flag PGPE Prolonged Droop Workaround Active. OCCFLG[PM_RESET_SUPPRESS] will be cleared later
     //after any pending IPCs from OCC have been processed and acked.
-    out32(OCB_OCCFLG_CLR, BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE));
+    out32(G_OCB_OCCFLG_CLR, BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE));
 
     //5.  Write PK Trace and Optrace record that the Prolonged Throttle workaround was removed,
     //including the Total Retry Count and the most recent bit vector of Quads that provided the NACK(s) .
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
index 031617ec..24f352b6 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
@@ -63,7 +63,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
 
     //Upon PGPE Boot, if OCC_FLAGS[PGPE_PSTATE_PROTOCOL_ACTIVATE] is set, then we start Pstart here, and not wait
     //for an IPC to come from OCC
-    occFlag.value = in32(OCB_OCCFLG);
+    occFlag.value = in32(G_OCB_OCCFLG);
 
     if (occFlag.value & BIT32(PGPE_PSTATE_PROTOCOL_ACTIVATE))
     {
@@ -77,7 +77,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
         pk_irq_sub_critical_enter(&ctx);
         p9_pgpe_pstate_start(PSTATE_START_OCC_FLAG);
         G_pgpe_optrace_data.word[0] = (START_STOP_FLAG << 24) | (G_pgpe_pstate_record.psComputed.fields.glb << 16) | (in32(
-                                          OCB_QCSR) >> 16);
+                                          G_OCB_QCSR) >> 16);
         p9_pgpe_optrace(PRC_START_STOP);
         pk_irq_sub_critical_exit(&ctx);
     }
@@ -86,10 +86,10 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
     // Set OCC Scratch2[PGPE_ACTIVE] and start updating beacon,
     // so that external world knows that PGPE is UP
     G_pgpe_pstate_record.updatePGPEBeacon = 1;
-    occScr2 = in32(OCB_OCCS2);
+    occScr2 = in32(G_OCB_OCCS2);
     occScr2 |= BIT32(PGPE_ACTIVE);
-    out32(OCB_OCCS2, occScr2);
-    PK_TRACE_INF("Setting PGPE_ACTIVE in OCC SCRATCH2 addr %X = %X", OCB_OCCS2, occScr2);
+    out32(G_OCB_OCCS2, occScr2);
+    PK_TRACE_INF("Setting PGPE_ACTIVE in OCC SCRATCH2 addr %X = %X", G_OCB_OCCS2, occScr2);
 
     //Thread Loop
     while(1)
@@ -109,14 +109,14 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
         //Loop while Pstate is ACTIVE
         while(G_pgpe_pstate_record.pstatesStatus == PSTATE_ACTIVE)
         {
-            //If a VDM prolonged droop happened, then we set OCB_OCCFLG[PGPE_PM_RESET_SUPPRESS]
+            //If a VDM prolonged droop happened, then we set G_OCB_OCCFLG[PGPE_PM_RESET_SUPPRESS]
             //It should be cleared once VDM prolonged droop condition has subsided and all pending IPCs
             //from OCC have been processed and acked. Note, that pending processing and pending ack are
             //only set inside IPC handler, and it's possible that while PGPE is stuck in the VDM prolonged
             //droop loop(the p9_pgpe_pstate_do_step function call) an IPC interrupt happened, so
             //PGPE must be given a change to take IPC interrupt and see if any other IPC from OCC
             //needs processing.
-            if ((in32(OCB_OCCFLG) & BIT32(PGPE_PM_RESET_SUPPRESS)))
+            if ((in32(G_OCB_OCCFLG) & BIT32(PGPE_PM_RESET_SUPPRESS)))
             {
                 if ((G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_CLIP_UPDT].pending_ack == 0) &&
                     (G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_WOF_VFRT].pending_ack == 0)  &&
@@ -125,7 +125,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
                     (G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_WOF_VFRT].pending_processing == 0)  &&
                     (G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_WOF_CTRL].pending_processing == 0))
                 {
-                    out32(OCB_OCCFLG_CLR, BIT32(PGPE_PM_RESET_SUPPRESS));
+                    out32(G_OCB_OCCFLG_CLR, BIT32(PGPE_PM_RESET_SUPPRESS));
                 }
             }
 
@@ -249,7 +249,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
                                 G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_ack = 0;
                                 ipc_send_rsp(G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].cmd, IPC_RC_SUCCESS);
                                 p9_pgpe_optrace(ACK_QUAD_ACTV);
-                                GPE_PUTSCOM(OCB_OCCFLG_CLR, BIT32(REQUESTED_ACTIVE_QUAD_UPDATE));//Clear OCCFLG[REQUESTED_ACTIVE_QUAD_UPDATE]
+                                GPE_PUTSCOM(G_OCB_OCCFLG_CLR, BIT32(REQUESTED_ACTIVE_QUAD_UPDATE));//Clear OCCFLG[REQUESTED_ACTIVE_QUAD_UPDATE]
 
                             }
                         }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
index c3ae7321..bebc5140 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
@@ -82,7 +82,7 @@ void p9_pgpe_thread_process_requests(void* arg)
         (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_VRATIO_MODIFIER) ||
         (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_ENABLE_FRATIO))
     {
-        out32(OCB_OCCFLG_OR, BIT32(29));
+        out32(G_OCB_OCCFLG_OR, BIT32(29));
     }
 
     PK_TRACE_DBG("PTH:Inited");
@@ -380,7 +380,7 @@ inline void p9_pgpe_process_sgpe_updt_active_quads()
             if(G_pgpe_pstate_record.wofStatus == WOF_ENABLED && G_pgpe_pstate_record.pstatesStatus == PSTATE_ACTIVE)
             {
                 PK_TRACE_INF("PTH: OCCLFG[30] set");
-                out32(OCB_OCCFLG_OR, BIT32(REQUESTED_ACTIVE_QUAD_UPDATE));//Set OCCFLG[REQUESTED_ACTIVE_QUAD_UPDATE]
+                out32(G_OCB_OCCFLG_OR, BIT32(REQUESTED_ACTIVE_QUAD_UPDATE));//Set OCCFLG[REQUESTED_ACTIVE_QUAD_UPDATE]
                 ack_now = 0;
             }
             else
@@ -431,7 +431,7 @@ inline void p9_pgpe_process_start_stop()
         args->msg_cb.rc = PGPE_RC_SUCCESS;
         G_pgpe_optrace_data.word[0] = (START_STOP_IPC << 24) |
                                       (G_pgpe_pstate_record.psComputed.fields.glb << 16) |
-                                      (in32(OCB_QCSR) >> 16);
+                                      (in32(G_OCB_QCSR) >> 16);
         p9_pgpe_optrace(PRC_START_STOP);
 
     }
@@ -493,7 +493,7 @@ inline void p9_pgpe_process_start_stop()
                 G_pgpe_optrace_data.word[0] = (args->pmcr_owner << 25 ) |
                                               (1 << 24) |
                                               (G_pgpe_pstate_record.psCurr.fields.glb << 16) |
-                                              (in32(OCB_QCSR) >> 16);
+                                              (in32(G_OCB_QCSR) >> 16);
                 p9_pgpe_optrace(PRC_START_STOP);
             }
             else
@@ -518,7 +518,7 @@ inline void p9_pgpe_process_start_stop()
                 p9_pgpe_pstate_stop();
                 args->msg_cb.rc = PGPE_RC_SUCCESS;
                 G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.psCurr.fields.glb << 16) |
-                                              (in32(OCB_QCSR) >> 16);
+                                              (in32(G_OCB_QCSR) >> 16);
                 p9_pgpe_optrace(PRC_START_STOP);
             }
         }
@@ -686,7 +686,7 @@ inline void p9_pgpe_process_wof_ctrl()
         args->msg_cb.rc = PGPE_RC_SUCCESS;
         G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
                                       (args->action << 16) |
-                                      (in32(OCB_QCSR) >> 16);
+                                      (in32(G_OCB_QCSR) >> 16);
         p9_pgpe_optrace(PRC_WOF_CTRL);
     }
     else if (G_pgpe_pstate_record.pstatesStatus & ( PSTATE_PM_SUSPENDED | PSTATE_PM_SUSPEND_PENDING |
@@ -730,7 +730,7 @@ inline void p9_pgpe_process_wof_ctrl()
 
                 G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
                                               (args->action << 16) |
-                                              (in32(OCB_QCSR) >> 16);
+                                              (in32(G_OCB_QCSR) >> 16);
                 p9_pgpe_optrace(PRC_WOF_CTRL);
             }
             else
@@ -753,7 +753,7 @@ inline void p9_pgpe_process_wof_ctrl()
 
                 G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
                                               (args->action << 16) |
-                                              (in32(OCB_QCSR) >> 16);
+                                              (in32(G_OCB_QCSR) >> 16);
                 p9_pgpe_optrace(PRC_WOF_CTRL);
             }
             else
@@ -990,7 +990,7 @@ inline void p9_pgpe_process_registration()
     ocb_ccsr_t ccsr;
     ccsr.value = in32(OCB_CCSR);
     ocb_qcsr_t qcsr;
-    qcsr.value = in32(OCB_QCSR);
+    qcsr.value = in32(G_OCB_QCSR);
     uint32_t  q, c, oldActiveDB, oldActiveQuads, unicastCoresVector = 0, quadsRegisterProcess;
     uint32_t quadAckExpect = 0;
     uint64_t value;
@@ -1032,7 +1032,7 @@ inline void p9_pgpe_process_registration()
                          G_pgpe_pstate_record.activeDB);
 
             G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) | (G_pgpe_pstate_record.psCurr.fields.glb << 16)
-                                          | (in32(OCB_QCSR) >> 16);
+                                          | (in32(G_OCB_QCSR) >> 16);
             p9_pgpe_optrace(PRC_PCB_T4);
         }
     }
@@ -1241,7 +1241,7 @@ inline void p9_pgpe_process_ack_sgpe_suspend_stop()
 
     //Change PMCR ownership
     PK_TRACE_INF("SUSP: Setting SCOM Ownership of PMCRs");
-    qcsr.value = in32(OCB_QCSR);
+    qcsr.value = in32(G_OCB_QCSR);
 
     //Set LMCR for each CME
     for (q = 0; q < MAX_QUADS; q++)
@@ -1264,10 +1264,10 @@ inline void p9_pgpe_process_ack_sgpe_suspend_stop()
 
     //OP Trace and Set OCCS2[PM_COMPLEX_SUSPENDED)
     p9_pgpe_optrace(ACK_PM_SUSP);
-    uint32_t occScr2 = in32(OCB_OCCS2);
+    uint32_t occScr2 = in32(G_OCB_OCCS2);
     occScr2 |= BIT32(PM_COMPLEX_SUSPENDED);
     G_pgpe_pstate_record.pstatesStatus = PSTATE_PM_SUSPENDED;
-    out32(OCB_OCCS2, occScr2);
+    out32(G_OCB_OCCS2, occScr2);
 
     PK_TRACE_INF("SUSP: Suspend Stop Processed");
 }