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| author | Yue Du <daviddu@us.ibm.com> | 2017-02-20 11:38:24 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:10:01 -0500 |
| commit | 330bde2507ccae78973ea670f696fa2c99b28617 (patch) | |
| tree | 109a91f8d6644bd19c377006ac0ddaa4c1b14773 | |
| parent | 77226fe18ccb3533beaff5051236051660e8cf15 (diff) | |
| download | talos-hcode-330bde2507ccae78973ea670f696fa2c99b28617.tar.gz talos-hcode-330bde2507ccae78973ea670f696fa2c99b28617.zip | |
IPL/Stop: Assert ABIST_SRAM_MODE_DC to support ABIST Recovery
Change-Id: I4465535c32e3cde8e8e2f0f3a13bb1d66d1f7614
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36728
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
| -rwxr-xr-x | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c | 5 | ||||
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index fa7a3b0b..109e929d 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -370,6 +370,11 @@ p9_cme_stop_entry() PK_TRACE("Assert skew sense to skewadjust fence via NET_CTRL0[22]"); CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(22)); + PK_TRACE("Drop ABIST_SRAM_MODE_DC to support ABIST Recovery via BIST[1]"); + CME_GETSCOM(C_BIST, core, CME_SCOM_AND, scom_data.value); + scom_data.words.upper &= ~BIT32(1); + CME_PUTSCOM(C_BIST, core, scom_data.value); + PK_TRACE("Assert vital fence via CPLT_CTRL1[3]"); CME_PUTSCOM(C_CPLT_CTRL1_OR, core, BIT64(3)); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c index 3ef16035..a44f81c0 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c @@ -68,6 +68,11 @@ p9_hcd_core_startclocks(uint32_t core) MARK_TRAP(SX_STARTCLOCKS_ALIGN) + PK_TRACE("Assert ABIST_SRAM_MODE_DC to support ABIST Recovery via BIST[1]"); + CME_GETSCOM(C_BIST, core, CME_SCOM_AND, scom_data.value); + scom_data.words.upper |= BIT32(1); + CME_PUTSCOM(C_BIST, core, scom_data.value); + PK_TRACE("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]"); CME_PUTSCOM(C_CPLT_CTRL0_CLEAR, core, BITS64(0, 2)); |
