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| author | Yue Du <daviddu@us.ibm.com> | 2018-05-15 17:03:42 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-05-30 10:29:43 -0500 |
| commit | 1dc26ec0072e9404fc5f2d39cb8b7b0ce6bc37dd (patch) | |
| tree | a40a8922720f8ca8f99bd76072ba2ec7f91f5c2e | |
| parent | 262e018945d36246fc169517b76e53c892ee1b58 (diff) | |
| download | talos-hcode-1dc26ec0072e9404fc5f2d39cb8b7b0ce6bc37dd.tar.gz talos-hcode-1dc26ec0072e9404fc5f2d39cb8b7b0ce6bc37dd.zip | |
STOP: Add URMOR RAM to CME for NDD23 SMF
Key_Cronus_Test=PM_REGRESS
Change-Id: I7b4bc42805a82cafe52f6a80a646c2554e973905
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58953
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
3 files changed, 25 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h index 6d76f329..63ad2414 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h @@ -57,6 +57,16 @@ // being enabled on all other dd levels unless this override #define DISABLE_CME_DUAL_CAST 0 +// NDD23 Secure Memory Support: RAM URMOR +#if NIMBUS_DD_LEVEL >= 23 || CUMULUS_DD_LEVEL >= 13 + + #define SMF_SUPPORT_ENABLE 1 + +#else + + #define SMF_SUPPORT_ENABLE 0 + +#endif #if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1 // NDD2: no catchup due to dual cast bug diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index dbd9efdf..b6ad553b 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -108,6 +108,7 @@ #define IMA_EVENT_MASK 0x20010AA8 #define CORE_THREAD_STATE 0x20010AB3 #define HRMOR 0x20010AB9 +#define URMOR 0x20010ABA #define C_SYNC_CONFIG 0x20030000 #define C_OPCG_ALIGN 0x20030001 diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 47fda5c0..f3aef781 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -1140,6 +1140,20 @@ p9_cme_stop_exit() // Nimbus DD2+ #else +#if SMF_SUPPORT_ENABLE + +#if EPM_P9_TUNING + + CME_PUTSCOM(URMOR, core, 0xA200000); + +#else + + PK_TRACE_INF("Core Wakes Up, Write URMOR with HOMER address"); + CME_PUTSCOM(URMOR, core, scom_data.value); + +#endif + +#endif #if EPM_P9_TUNING |
