STOP: Add Core quiesce workaround to CME Fit Timer

-- p7:  Added a check for LSU and Nest quiesce as well
-- p8:  Added clear of the TSR FIS to IOTA fit handler
-- p9:  Added stop workaround on checkstop or special attention
-- p10: rebase on disable flag support
-- p11:
1) enable for Cumulus 1.0 and Nimbus 2.0 & 2.1 only
2) disable the livelock buster if special wakeup done is asserted
3) clear the fit_counter when special wakeup done
   or stop entry is done on either core
4) delete CME_FLAGS_DISABLE_PERIODIC_CORE_QUIESCE and
   instead look at bit 2 of CPPMR with dualcast OR
   unless nimbus dd2.0 then you have to
   read both cores and OR because of the bug
-- p12:
1) no longer have PGPE sample OCC Flag bit 13 (back out the change)
2) have SGPE init set CPMMR bit 2 in response to the attribute
   instead of CME flag bit 23.
3) add cme_flags[12] as workaround active bit (nor of both cpmmr[2])
-- p13:
   kills the CME flag, OCC flag and SGPE header flag
   diff commit will establish attr-> cpmmr[2] simple flow
   cme only read cpmmr[2]
-- p14:
   in case of stop0/1, assert pm_exit and poll for it to wake core up
-- p15: rebase
-- p16: add drop pm_exit after workaround
-- p17: add pm_exit delay, remove pm_active=1 poll
        remove some PK_TRACEs, change to unified compiler flag

Change-Id: Ic9d77954488977967a93049d1da0f785aae9639f
Original-Change-Id: I855f7f8e4b5ce7275511d581b8e68d10217ab601
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44965
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index f3d90032..d8f2f0d9 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -408,6 +408,12 @@ p9_cme_stop_entry()
             // Mark core as to be stopped
             G_cme_stop_record.core_running &= ~core;
 
+#ifdef PCQW_ENABLE
+
+            G_cme_record.fit_record.core_quiesce_fit_trigger = 0;
+
+#endif
+
             // Request PCB Mux
 
 #if HW405292_NDD1_PCBMUX_SAVIOR
@@ -555,6 +561,8 @@ p9_cme_stop_entry()
             PK_TRACE("HW407385: Waking up the core(pm_exit=1) via SICR[4/5]");
             out32(CME_LCL_SICR_OR, core << SHIFT32(5));
 
+            CME_PM_EXIT_DELAY
+
             PK_TRACE("HW407385: Polling for core wakeup(pm_active=0) via EINR[20/21]");
 
             while((in32(CME_LCL_EINR)) & (core << SHIFT32(21)));