PM: Added support for PGPE Boot/PGPE integration

- support for P-State parameter block
- implements a compact image layout of PGPE similar to CME/SGPE.
- adds PGPE boot progress code as a field in PPMR header.
- implements PGPE boot loader and PGPE boot copier.
- incorporates ability to generate PPMR header in the build flow.
- change logic for calculating CME's first block copy length.
- Turned on generated tables in PGPE Hcode
- Fixed up pointers to generated tables
- add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE ops
- fix p9_pstate_parameter_build bug with AVS timing attributes
- Make OCC Pstate Parameter block a fixed offset (128KB) in PPMR
- Make Pstate Table from PGPE a fixed offset (144KB) in PPMR to ease debug
- Fix Endianes issues in OCC PPB and input slope calcs
- Added PGPE Hcode Length to PGPE header so that GPPB SRAM location is known.
- Build flag for OCc Immediate IPC response
- Build flag to no use temp boot settings
- Expanding tracing for debug
- Added default values for PBAX attributes as placeholders for MRW in firmware
- Added WOF VFRT structure definions to headers;  movement into HOMER NOT
  yet supported
- Addressed review comments and rebased
- Rebased with ATTR_PGPE_HCODE_FUNCTION_ENABLE in separate commit for Cronus

Change-Id: I4752debbc7fb3275d4e79804333654511de427ff
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26115
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

28 files changed, 1058 insertions, 286 deletions

diff --git a/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h b/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
index 7e76a7dd..b6c5a5b5 100644
--- a/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
+++ b/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
@@ -104,8 +104,8 @@ typedef struct ipcmsg_start_stop
 typedef struct ipcmsg_clip_update
 {
     ipcmsg_base_t   msg_cb;
-    uint8_t         ps_val_clip_min[MAX_QUADS];
-    uint8_t         ps_val_clip_max[MAX_QUADS];
+    uint8_t         ps_val_clip_min[MAXIMUM_QUADS];
+    uint8_t         ps_val_clip_max[MAXIMUM_QUADS];
     uint8_t         pad[2];
 } ipcmsg_clip_update_t;
 
@@ -114,7 +114,7 @@ typedef struct ipcmsg_set_pmcr
 {
     ipcmsg_base_t   msg_cb;
     uint8_t         pad[6];
-    uint64_t        pmcr[MAX_QUADS];
+    uint64_t        pmcr[MAXIMUM_QUADS];
 } ipcmsg_set_pmcr_t;
 
 
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index ef0d35ac..41b8fd88 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -35,33 +35,40 @@
 #ifndef __HW_IMG_DEFINE
 #define __HW_IMG_DEFINE
 
-
 #include <p9_hcd_header_defs.H>
+#include <p9_pstates_cmeqm.h>
+#include <p9_pstates_common.h>
+#include <p9_pstates_occ.h>
+#include <p9_pstates_pgpe.h>
+#include <p9_pstates_table.h>
+
 //--------------------------------------------------------------------------
 // local structs and constants
 // -------------------------------------------------------------------------
 #ifndef __ASSEMBLER__
-
+#ifdef __cplusplus
 #ifndef __PPE_PLAT
 namespace p9_hcodeImageBuild
 {
 #endif //__PPE_PLAT
+#endif //__cplusplus
 #endif //__ASSEMBLER__
-
 // Constants used in both C++ and Assembler/Linker code
 CONST_UINT32_T(CPMR_HEADER_SIZE, 256);
 CONST_UINT32_T(QPMR_HEADER_SIZE, 512);
+CONST_UINT32_T(PPMR_HEADER_SIZE, 512);
+CONST_UINT32_T(PGPE_IVPR_ADDR,   0xfff20000);
 
 //#pragma message (STR(CPMR_HEADER_SIZE))
 
 // Define the Magic Numbers for the various images
 HCD_MAGIC_NUMBER(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30));  // CPMR_1.0
-HCD_MAGIC_NUMBER(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30));  // QPMR_1.0
 HCD_MAGIC_NUMBER(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30));  // CME__1.0
+HCD_MAGIC_NUMBER(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30));  // QPMR_1.0
 HCD_MAGIC_NUMBER(SGPE_MAGIC_NUMBER, ULL(0x534750455f312e30 )); // SGPE_1.0
+HCD_MAGIC_NUMBER(PPMR_MAGIC_NUMBER, ULL(0x50504d525f312e30));  // PPMR_1.0
 HCD_MAGIC_NUMBER(PGPE_MAGIC_NUMBER , ULL(0x504750455F312E30)); // PGPE_1.0
 
-
 /**
  * @brief models QPMR header in HOMER
  */
@@ -124,7 +131,7 @@ typedef struct
 {
 #endif
 HCD_HDR_ATTN  ( attnOpcodes, 2);
-HCD_HDR_UINT64( magic_number, CPMR_MAGIC_NUMBER);  // CPMR_1.0
+HCD_HDR_UINT64( magic_number, CPMR_MAGIC_NUMBER);
 HCD_HDR_UINT32( cpmrbuildDate, 0);
 HCD_HDR_UINT32( cpmrVersion, 0);
 HCD_HDR_UINT8_VEC (cpmrReserveFlags, 7, 0);
@@ -139,16 +146,63 @@ HCD_HDR_UINT32( coreSpecRingOffset, 0);
 HCD_HDR_UINT32( coreSpecRingLength, 0);
 HCD_HDR_UINT32( coreScomOffset, 0);
 HCD_HDR_UINT32( coreScomLength, 0);
-HCD_HDR_PAD(256);
+HCD_HDR_PAD(CPMR_HEADER_SIZE);
 #ifdef __ASSEMBLER__
 .endm
 #else
 } __attribute__((packed, aligned(256))) cpmrHeader_t;
 #endif
 
+
 // @todo Get around the above hardcoding.
 
 /**
+ * PPMR Header
+ *
+ *  This header is only consumed by Hcode Image Build and
+ *  lab tools, not by PPE code.  It is generated with assembler
+ *  primitives during PGPE build and placed in HOMER by
+ *  Hcode Image Build.
+ */
+
+#ifdef __ASSEMBLER__
+.macro  .ppmr_header
+.section ".ppmr_header" , "aw"
+.balign    8
+#else
+typedef struct
+{
+#endif
+//Offset are wrt to start of PPMR unless specified otherwise
+//length in bytes unless specified otherwise.
+HCD_HDR_UINT64(g_ppmr_magic_number, PPMR_MAGIC_NUMBER);  // PPMR_1.0
+HCD_HDR_UINT32(g_ppmr_bc_offset,    0 );  // PGPE Level1 Boot loader
+HCD_HDR_UINT32(g_ppmr_reserve1,     0 );
+HCD_HDR_UINT32(g_ppmr_bl_offset,    0 );  // PGPE Level2 Boot loader
+HCD_HDR_UINT32(g_ppmr_bl_length,    0 );  // PGPE Level2 Boot loader
+HCD_HDR_UINT32(g_ppmr_build_date,   0 );  // Build date for PGPE Image
+HCD_HDR_UINT32(g_ppmr_build_ver,    0 );  // Build Version
+HCD_HDR_UINT64(g_ppmr_reserve_flag, 0 );  // Reserve Flag
+HCD_HDR_UINT32(g_ppmr_hcode_offset, 0 );  // Offset to start of PGPE Hcode
+HCD_HDR_UINT32(g_ppmr_hcode_length, 0 );  // PGPE Hcode length in Bytes
+HCD_HDR_UINT32(g_ppmr_gppb_offset,  0 );  // Offset to Global P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_gppb_length,  0 );  // Length of Global P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_lppb_offset,  0 );  // Offset to Local P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_lppb_length,  0 );  // Length of Local P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_oppb_offset,  0 );  // Offset to OCC P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_oppb_length,  0 );  // Length of OCC P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_pstables_offset, 0); // Offset to PState Table
+HCD_HDR_UINT32(g_ppmr_pstables_length, 0); // Length of P State table
+HCD_HDR_UINT32(g_ppmr_pgpe_sram_img_size, 0); // PGPE Actual SRAM Image Size
+HCD_HDR_UINT32(g_ppmr_pgpe_boot_prog_code, 0 );// for debug of PGPE booting
+HCD_HDR_PAD(0x200);
+#ifdef __ASSEMBLER__
+.endm
+#else
+} __attribute__((packed, aligned(0x200))) PpmrHeader_t;
+#endif
+
+/**
  * SGPE Header
  *
  * The SGPE header is loaded in the OCC SRAM.  Structure member names are
@@ -169,7 +223,7 @@ HCD_HDR_PAD(256);
 typedef struct
 {
 #endif
-HCD_HDR_UINT64(g_sgpe_magic_number, P9_XIP_MAGIC_SGPE);   //XIP SGPE
+HCD_HDR_UINT64(g_sgpe_magic_number, SGPE_MAGIC_NUMBER);   //SGPE 1.0
 HCD_HDR_UINT32(g_sgpe_reset_address, 0);
 HCD_HDR_UINT32(g_sgpe_reserve1, 0);
 HCD_HDR_UINT32(g_sgpe_ivpr_address, 0);
@@ -214,7 +268,7 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
 typedef struct
 {
 #endif
-HCD_HDR_UINT64(g_cme_magic_number, CME_MAGIC_NUMBER);  // CME__1.0
+HCD_HDR_UINT64(g_cme_magic_number, CME_MAGIC_NUMBER);
 HCD_HDR_UINT32(g_cme_hcode_offset, 0);
 HCD_HDR_UINT32(g_cme_hcode_length, 0);
 HCD_HDR_UINT32(g_cme_common_ring_offset, 0);
@@ -255,25 +309,40 @@ typedef struct CMEImageFlags
  * PGPE Header
  *
  * The PGPE header is loaded in the OCC SRAM so it is "tight" (little extra space)
- * Thus, this "structure" is NOT padded to a specific size and is limited to
- * 64B.  Also, structure member names are preceded with "g_" as these becoming
- * global variables in the CME Hcode.
+ * Also, structure member names are preceded with "g_" as these becoming
+ * global variables in the PGPE Hcode.
  */
 #ifdef __ASSEMBLER__
 .macro  .pgpe_header
-.section ".pgpe_header" , "aw"
+.section ".pgpe_image_header" , "aw"
 .balign    8
 #else
 typedef struct
 {
 #endif
-HCD_HDR_UINT64(g_pgpe_magic_number, PGPE_MAGIC_NUMBER);  // PGPE_1.0
-HCD_HDR_UINT32(g_pgpe_build_date, 0);
-HCD_HDR_UINT32(g_pgpe_build_ver, 0);
-HCD_HDR_UINT32(g_pgpe_hcode_offset, 0);
-HCD_HDR_UINT32(g_pgpe_hcode_length, 0);
-HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
-//FIXME Need to get info on other fields
+HCD_HDR_UINT64(g_pgpe_magic_number, PGPE_MAGIC_NUMBER);     // PGPE_1.0
+HCD_HDR_UINT32(g_pgpe_sys_reset_addr,           0 );        // Fully qualified OCC address where pk_init resides
+HCD_HDR_UINT32(g_pgpe_shared_sram_addr,         0 );        // SRAM address where shared SRAM begins
+HCD_HDR_UINT32(g_pgpe_ivpr_addr,   PGPE_IVPR_ADDR );        // Beginning of PGPE region in OCC SRAM
+HCD_HDR_UINT32(g_pgpe_shared_sram_len,          0 );        // Length of shared SRAM area
+HCD_HDR_UINT32(g_pgpe_build_date,               0 );        // Build date for PGPE Image
+HCD_HDR_UINT32(g_pgpe_build_ver,                0 );        // Build Version
+HCD_HDR_UINT16(g_pgpe_flags,                    0 );        // PGPE Flags
+HCD_HDR_UINT16(g_pgpe_reserve1,                 0 );        // Reserve field
+HCD_HDR_UINT32(g_pgpe_reserve2,                 0 );        // Reserve field
+HCD_HDR_UINT32(g_pgpe_gppb_sram_addr,           0 );        // Offset to Global P State Parameter Block
+HCD_HDR_UINT32(g_pgpe_hcode_length,             0 );        // Length of PGPE Hcode
+HCD_HDR_UINT32(g_pgpe_gppb_mem_offset,
+               0 );        // Offset to start of Global PS Param Block wrt start of HOMER.
+HCD_HDR_UINT32(g_pgpe_gppb_length,              0 );        // Length of Global P State Parameter Block
+HCD_HDR_UINT32(g_pgpe_gen_pstables_mem_offset,  0 );        // Offset to PState Table wrt start of HOMER
+HCD_HDR_UINT32(g_pgpe_gen_pstables_length,      0 );        // Length of P State table
+HCD_HDR_UINT32(g_pgpe_occ_pstables_sram_addr,   0 );        // Offset to start of OCC P-State table
+HCD_HDR_UINT32(g_pgpe_occ_pstables_len,         0 );        // Length of OCC P-State table
+HCD_HDR_UINT32(g_pgpe_beacon_addr,              0 );        // SRAM addr where PGPE beacon is located
+HCD_HDR_UINT32(g_quad_status_addr,              0 );
+HCD_HDR_UINT32(g_wof_table_addr,                0 );
+HCD_HDR_UINT32(g_wof_table_length,              0 );
 #ifdef __ASSEMBLER__
 .endm
 #else
@@ -409,17 +478,39 @@ enum
     SGPE_PROC_FAB_ADDR_BAR_MODE_POS =   0x00008000,
 
     // PPMR
-
     //** Boot Loaders
-    PGPE_LVL_1_BOOT_LOAD_SIZE   = ONE_KB,
-    PGPE_LVL_2_BOOT_LOAD_SIZE   = ONE_KB,
-    PGPE_INT_VECTOR             = 384,
-    PGPE_HCODE_SIZE             = 30 * ONE_KB,
-    PGPE_PARAM_BLOCK_SIZE       = 8 * ONE_KB,  //Global and OCC PPB
-    PSTATE_OUTPUT_TABLE         = 8 * ONE_KB,
-
-    PGPE_MAX_AREA_SIZE          = 48 * ONE_KB, // @todo RTC 158543 Reallocate space
-
+    PPMR_OFFSET                 =  HOMER_PPMR_REGION_NUM * ONE_MB,
+    PPMR_HEADER_LEN             =  512,
+    PGPE_LVL_1_BOOT_LOAD_SIZE   =  ONE_KB,
+    PGPE_LVL_2_BOOT_LOAD_SIZE   =  ONE_KB,
+    PGPE_MAX_AREA_SIZE          =  48 * ONE_KB, // @todo RTC 158543 Reallocate space
+
+    PGPE_HOMER_SRAM_ALLOC       =  128 * ONE_KB,
+    PGPE_HOMER_SRAM_RESERVE     =  PGPE_HOMER_SRAM_ALLOC -
+                                   (PPMR_HEADER_LEN  +
+                                    PGPE_LVL_1_BOOT_LOAD_SIZE +
+                                    PGPE_LVL_2_BOOT_LOAD_SIZE +
+                                    PGPE_MAX_AREA_SIZE),
+
+    PGPE_INT_VECTOR             =  384,
+    PGPE_HCODE_SIZE             =  32 * ONE_KB,
+    PGPE_PARAM_BLOCK_SIZE       =  8 * ONE_KB,
+
+    // @todo: get these from the p9_homer_map.h file
+    HOMER_OOC_PARAM_BLOCK_ADDR      =  0x00320000,   // PPMR + 128KB
+    HOMER_PSTATE_OUTPUT_TABLE_ADDR  =  0x00324000,   // PPMR + 144KB
+    HOMER_WOF_TABLE_ADDR            =  0x003C0000,   // PPMR + 768KB (the last 256KB)
+
+    OCC_PARAM_BLOCK_ALLOC       =  16 * ONE_KB,
+    OCC_PARAM_BLOCK_SIZE        =  8 * ONE_KB,
+
+    PSTATE_OUTPUT_TABLE_ALLOC   =  16 * ONE_KB,
+    PSTATE_OUTPUT_TABLE_SIZE    =  8 * ONE_KB,
+
+    WOF_TABLES_BLOCK_ALLOC       =  256 * ONE_KB,
+
+    OCI_SRAM_ADDR_BASE          =  0xFFF20000,   // @todo: what is this for?
+    OCI_PBA_ADDR_BASE           =  0x80300000,
     IGNORE_CHIPLET_INSTANCE     =  0xFF,
 
     //RING LAYOUT
@@ -468,6 +559,7 @@ enum ImgBldRetCode_t
     CME_SRAM_IMG_SIZE_ERR       =   31,
     SGPE_SRAM_IMG_SIZE_ERR      =   32,
     PGPE_SRAM_IMG_SIZE_ERR      =   33,
+    BUILD_FAIL_PGPE_PPMR        =   34,
 };
 
 /**
@@ -658,24 +750,17 @@ typedef struct
 /**
  * @brief   models image section associated with PGPE in HOMER.
  */
-typedef union PgpeHcodeLayout
-{
-    uint8_t hcode[PGPE_HCODE_SIZE];
-    struct
-    {
-        uint8_t pgpeIntVector[PGPE_INT_VECTOR];
-        PgpeHeader_t imgHeader;
-        uint8_t exe[PGPE_HCODE_SIZE - PGPE_INT_VECTOR - sizeof(PgpeHeader_t)];
-    } elements;
-} PgpeHcodeLayout_t;
-
 typedef struct
 {
-    uint8_t l1BootLoader[PGPE_LVL_1_BOOT_LOAD_SIZE];
-    uint8_t l2BootLoader[PGPE_LVL_2_BOOT_LOAD_SIZE];
-    PgpeHcodeLayout_t pgpeBin;
-    uint8_t paramBlock[PGPE_PARAM_BLOCK_SIZE];
-    uint8_t pstateOutputTable[PSTATE_OUTPUT_TABLE];
+    uint8_t  ppmrHeader[PPMR_HEADER_LEN];
+    uint8_t  l1BootLoader[PGPE_LVL_1_BOOT_LOAD_SIZE];
+    uint8_t  l2BootLoader[PGPE_LVL_2_BOOT_LOAD_SIZE];
+    uint8_t  pgpeSramImage[PGPE_MAX_AREA_SIZE];     // Includes the Global Pstate Parameter Block
+    uint8_t  ppmr_reserved0[PGPE_HOMER_SRAM_RESERVE];
+    uint8_t  occParmBlock[sizeof(OCCPstateParmBlock)];  // PPMR + 128KB
+    uint8_t  occParmBlockReserve[OCC_PARAM_BLOCK_ALLOC - sizeof(OCCPstateParmBlock)];
+    uint8_t  pstateTable[sizeof(GeneratedPstateInfo)];  // PPMR + 144KB
+    uint8_t  pstateTableReserve[PSTATE_OUTPUT_TABLE_ALLOC - sizeof(GeneratedPstateInfo)];
 } PPMRLayout_t;
 
 /**
@@ -702,9 +787,11 @@ typedef struct
     uint8_t      pgpeReserve[ONE_MB - sizeof( PPMRLayout_t )];
 } Homerlayout_t;
 
+#ifdef __cplusplus
 #ifndef __PPE_PLAT
 }// namespace p9_hcodeImageBuild ends
 #endif //__PPE_PLAT
+#endif //__cplusplus
 
 #endif //__ASSEMBLER__
 #endif //__HW_IMG_DEFINE
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
index 5914cd62..53caabb1 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
@@ -134,6 +134,37 @@ typedef union occ_scratch2
     } fields;
 } occ_scratch2_t;
 
+typedef union pgpe_flags
+{
+    uint16_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint16_t  resclk_enable                 : 1;
+        uint16_t  ivrm_enable                   : 1;
+        uint16_t  vdm_enable                    : 1;
+        uint16_t  wof_enable                    : 1;
+        uint16_t  dpll_dynamic_fmax_enable      : 1;
+        uint16_t  dpll_dynamic_fmin_enable      : 1;
+        uint16_t  dpll_droop_protect_enable     : 1;
+        uint16_t  reserved7                     : 1;
+        uint16_t  occ_ipc_immed_response        : 1;
+        uint16_t  reserved_9_15                 : 7;
+#else
+        uint16_t  reserved_9_15                 : 7;
+        uint16_t  occ_ipc_immed_response        : 1;
+        uint16_t  reserved7                     : 1;
+        uint16_t  dpll_droop_protect_enable     : 1;
+        uint16_t  dpll_dynamic_fmin_enable      : 1;
+        uint16_t  dpll_dynamic_fmax_enable      : 1;
+        uint16_t  wof_enable                    : 1;
+        uint16_t  vdm_enable                    : 1;
+        uint16_t  ivrm_enable                   : 1;
+        uint16_t  resclk_enable                 : 1;
+#endif
+    } fields;
+} pgpe_flags_t;
+
 typedef union cme_flags
 {
     uint32_t value;
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h
index 5327880c..fb0b7d99 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h
@@ -34,6 +34,7 @@
 #ifndef __P9_PSTATES_CME_H__
 #define __P9_PSTATES_CME_H__
 
+#include <p9_pstates_common.h>
 
 /// \defgroup QM Flags
 ///
@@ -64,13 +65,22 @@
 
 /// @}
 
-
+#ifndef __ASSEMBLER__
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #include <stdint.h>
 
+/// LocalParmsBlock Magic Number
+///
+/// This magic number identifies a particular version of the
+/// PstateParmsBlock and its substructures.  The version number should be
+/// kept up to date as changes are made to the layout or contents of the
+/// structure.
+
+#define LOCAL_PARMSBLOCK_MAGIC 0x434d455050423030ull /* CMEPPB00 */
+
 /// Quad Manager Flags
 ///
 
@@ -292,5 +302,5 @@ typedef struct
 #ifdef __cplusplus
 } // end extern C
 #endif
-
+#endif    /* __ASSEMBLER__ */
 #endif    /* __P9_PSTATES_CME_H__ */
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
index 9e1482f8..e87f2af8 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
@@ -35,13 +35,13 @@
 #ifndef __P9_PSTATES_COMMON_H__
 #define __P9_PSTATES_COMMON_H__
 
-/// The minimum Pstate (knowing the increasing Pstates numbers represent
+/// The maximum Pstate (knowing the increasing Pstates numbers represent
 /// decreasing frequency)
-#define PSTATE_MIN 255
+#define PSTATE_MAX 255
 
-/// The maximum Pstate (knowing the increasing Pstates numbers represent
+/// The minimum Pstate (knowing the increasing Pstates numbers represent
 /// decreasing frequency)
-#define PSTATE_MAX 0
+#define PSTATE_MIN 0
 
 /// The minimum \e legal DPLL frequency code
 ///
@@ -83,7 +83,7 @@
 #define IVID_STEP_UV 4000
 
 /// Maximum number of Quads (4 cores plus associated caches)
-#define MAX_QUADS 6
+#define MAXIMUM_QUADS 6
 
 // Constants associated with VRM stepping
 // @todo Determine what is needed here (eg Attribute mapping) and if any constants
@@ -130,7 +130,8 @@
 #define IDDQ_MEASUREMENTS 6
 #define MEASUREMENT_ELEMENTS  6    // Number of Quads for P9
 #define IDDQ_READINGS_PER_IQ 2
-#define IDDQ_ARRAY_VOLTAGES {0.60, 0.70, 0.80, 0.90, 1.00, 1.10}
+#define IDDQ_ARRAY_VOLTAGES     { 0.60 ,  0.70 ,  0.80 ,  0.90 ,  1.00 ,  1.10}
+#define IDDQ_ARRAY_VOLTAGES_STR {"0.60", "0.70", "0.80", "0.90", "1.00", "1.10"}
 
 /// WOF Items
 #define NUM_ACTIVE_CORES 24
@@ -170,6 +171,7 @@
 #define LPST_GPST_WARNING        0x00477902
 #define LPST_INCR_CLIP_ERROR     0x00477903
 
+#ifndef __ASSEMBLER__
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -198,15 +200,13 @@ typedef uint16_t VidAVS;
 ///
 typedef struct
 {
-
     uint32_t vdd_mv;
     uint32_t vcs_mv;
     uint32_t idd_100ma;
     uint32_t ics_100ma;
     uint32_t frequency_mhz;
     uint8_t  pstate;        // Pstate of this VpdOperating
-    uint8_t  pad[3];
-
+    uint8_t  pad[3];        // Alignment padding
 } VpdOperatingPoint;
 
 /// VPD Biases.
@@ -258,16 +258,141 @@ typedef struct
 // WOF Voltage, Frequency Ratio Tables
 //
 
+// VFRT Header
+
+typedef struct
+{
+
+    /// Magic Number
+    ///   Set to ASCII  "VT"
+    uint16_t magic_number;
+
+    /// Indicator
+    ///   Space for generation tools to be anything unique necessary to ID this
+    ///    VFRT
+    uint16_t indicator;
+
+    union
+    {
+        uint8_t value;
+        struct
+        {
+            uint8_t type    : 4;
+            uint8_t version : 4;
+        } fields;
+    } typever;
+
+    uint8_t reserved;
+
+    union
+    {
+        uint16_t value;
+        struct
+        {
+#ifdef _BIG_ENDIAN
+            uint16_t reserved: 4;
+            uint16_t vdn_id  : 4;
+            uint16_t vdd_id  : 4;
+            uint16_t qa_id   : 4;
+#else
+            uint16_t qa_id   : 4;
+            uint16_t vdd_id  : 4;
+            uint16_t vdn_id  : 4;
+            uint16_t reserved: 4;
+#endif // _BIG_ENDIAN
+
+        } fields;
+    } ids;
+
+} VFRTHeader_t;
+
+// WOF Tables Header
+
+typedef struct
+{
+
+    /// Magic Number
+    ///   Set to ASCII  "VFRT___x" where x is the version of the VFRT structure
+    uint64_t magic_number;
+
+    /// VFRT Size
+    ///    Length, in bytes, of a VFRT
+    uint8_t vfrt_size;
+
+    /// VFRT Data Size
+    ///    Length, in bytes, of the data field.
+    uint8_t vfrt_data_size;
+
+    uint8_t reserved;
+
+    /// Quad Active Size
+    ///    Total number of Active Quads
+    uint8_t quads_active_size;
+
+    /// Ceff Vdn Start
+    ///    CeffVdn value represented by index 0 (in percent)
+    uint8_t vdn_start;
+
+    /// Ceff Vdn Step
+    ///    CeffVdn step value for each CeffVdn index (in percent)
+    uint8_t vdn_step;
+
+    /// Ceff Vdn Size
+    ///    Number of CeffVdn indexes
+    uint8_t vdn_size;
+
+    /// Ceff Vdd Start
+    ///    CeffVdd value represented by index 0 (in percent)
+    uint8_t vdd_start;
+
+    /// Ceff Vdd Step
+    ///    CeffVdd step value for each CeffVdd index (in percent)
+    uint8_t vdd_step;
+
+    /// Ceff Vdd Size
+    ///    Number of CeffVdd indexes
+    uint8_t vdd_size;
+
+    /// Vratio Start
+    ///    Vratio value represented by index 0 (in percent)
+    uint8_t vratio_start;
+
+    /// Vratio Step
+    ///   Vratio step value for each CeffVdd index (in percent)
+    uint8_t vratio_step;
+
+    /// Vratio Size
+    ///    Number of Vratio indexes
+    uint8_t vratio_size;
+
+    /// Fratio Start
+    ///    Fratio value represented by index 0 (in percent)
+    uint8_t fratio_start;
+
+    /// Fratio Step
+    ///   Fratio step value for each CeffVdd index (in percent)
+    uint8_t fratio_step;
+
+    /// Fratio Size
+    ///    Number of Fratio indexes
+    uint8_t fratio_size;
+
+} WofTablesHeader_t;
+
+
 // VDN
 
 // Data is provided in 12ths (eg 12 core pairs on a 24 core chip)
 #define VFRT_VRATIO_SIZE 12
 
-// 100%/10% steps + 1 (for 0)
-#define VFRT_FRATIO_SIZE 11
+// 100%/10% steps
+#define VFRT_FRATIO_SIZE 10
+
+// Holds a frequency that is 1000MHz + 16.667*VFRT_Circuit_t
+typedef uint8_t VFRT_Circuit_t;
+typedef Pstate  VFRT_Hcode_t;
+
 
-typedef uint16_t VFRT_Circuit_t;   // Holds a frequency in MHz
-typedef Pstate   VFRT_Hcode_t;
 
 extern VFRT_Circuit_t VFRTCircuitTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE];
 
@@ -277,5 +402,5 @@ extern VFRT_Hcode_t   VFRTInputTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE];
 #ifdef __cplusplus
 } // end extern C
 #endif
-
+#endif    /* __ASSEMBLER__ */
 #endif    /* __P9_PSTATES_COMMON_H__ */
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
index 0855ab85..f61dcb00 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
@@ -36,11 +36,22 @@
 #define __P9_PSTATES_OCC_H__
 
 #include <p9_pstates_common.h>
+#include <p9_pstates_pgpe.h>
 
+#ifndef __ASSEMBLER__
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/// PstateParmsBlock Magic Number
+///
+/// This magic number identifies a particular version of the
+/// PstateParmsBlock and its substructures.  The version number should be
+/// kept up to date as changes are made to the layout or contents of the
+/// structure.
+
+#define OCC_PARMSBLOCK_MAGIC 0x4f43435050423030ull /* OCCPPB00 */
+
 /// IDDQ Reading Type
 /// Each entry is 2 bytes. The values are in 6.25mA units; this allow for a
 /// maximum value of 409.6A to be represented.
@@ -51,7 +62,7 @@ typedef uint16_t iddq_entry_t;
 /// Each entry is 1 byte. The values are in 0.5degC units; this allow for a
 /// maximum value of 127degC to be represented.
 ///
-typedef uint16_t avgtemp_entry_t;
+typedef uint8_t avgtemp_entry_t;
 
 /// Iddq Table
 ///
@@ -76,10 +87,10 @@ typedef struct
     uint8_t     good_caches_per_sort;
 
     /// Good Normal Cores
-    uint8_t     good_normal_cores[MAX_QUADS];
+    uint8_t     good_normal_cores[MAXIMUM_QUADS];
 
     /// Good Caches
-    uint8_t     good_caches[MAX_QUADS];
+    uint8_t     good_caches[MAXIMUM_QUADS];
 
     /// RDP to TDP Scaling Factor in 0.01% units
     uint16_t    rdp_to_tdp_scale_factor;
@@ -103,10 +114,10 @@ typedef struct
     iddq_entry_t ivdd_all_good_cores_off_good_caches_on[IDDQ_MEASUREMENTS];
 
     /// IVDD Quad 0 Good Cores ON, Caches ON; 6.25mA units
-    iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAX_QUADS][IDDQ_MEASUREMENTS];
+    iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS];
 
-    /// IVDDN ; 6.25mA units
-    iddq_entry_t ivdn;
+    /// IVDDN  6.25mA units
+    iddq_entry_t ivdn[IDDQ_MEASUREMENTS];
 
 
     /// IVDD ALL Good Cores ON, Caches ON; 6.25mA units
@@ -119,11 +130,14 @@ typedef struct
     avgtemp_entry_t avgtemp_all_good_cores_off[IDDQ_MEASUREMENTS];
 
     /// avgtemp Quad 0 Good Cores ON, Caches ON; 6.25mA units
-    avgtemp_entry_t avgtemp_quad_good_cores_on[MAX_QUADS][IDDQ_MEASUREMENTS];
+    avgtemp_entry_t avgtemp_quad_good_cores_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS];
 
     /// avgtempN ; 6.25mA units
     avgtemp_entry_t avgtemp_vdn;
 
+    /// spare (per MVPD documentation
+    uint8_t spare_1[43];
+
 } IddqTable;
 
 
@@ -132,6 +146,9 @@ typedef struct
 /// comsumption by the OCC firmware.  This data will reside in the Quad
 /// Power Management Region (QPMR).
 ///
+/// This structure is aligned to 128B to allow for easy downloading using the
+/// OCC block copy engine
+///
 typedef struct
 {
 
@@ -168,11 +185,10 @@ typedef struct
     // Minimum Pstate;  Maximum is always 0.
     uint32_t pstate_min;    // Comes from PowerSave #V point after biases
 
-} OCCPstateParmBlock;
-
+} __attribute__((aligned(128))) OCCPstateParmBlock;
 
 #ifdef __cplusplus
 } // end extern C
 #endif
-
+#endif    /* __ASSEMBLER__ */
 #endif    /* __P9_PSTATES_OCC_H__ */
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
index 789cdd17..a06f586b 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
@@ -47,6 +47,7 @@
 
 #define PSTATE_PARMSBLOCK_MAGIC 0x5053544154453030ull /* PSTATE00 */
 
+#ifndef __ASSEMBLER__
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -117,8 +118,6 @@ typedef struct
     /// UltraTurbo Segment VIDs by Core Count
     VIDModificationTable ut_vid_mod;
 
-    uint8_t pad[4];
-
 } WOFElements;
 
 
@@ -218,28 +217,28 @@ typedef struct
     /// Resonant Clock Grid Management Setup
     ResonantClockingSetup resclk;
 
-    //Time b/w ext VRM detects write voltage cmd and when voltage begins to move
+    /// Time b/w ext VRM detects write voltage cmd and when voltage begins to move
     uint32_t ext_vrm_transition_start_ns;
 
-    //Transition rate for an increasing VDD voltage excursion
+    /// Transition rate for an increasing VDD voltage excursion
     uint32_t ext_vrm_transition_rate_inc_uv_per_us;
 
-    //Transition rate for an decreasing VDD voltage excursion
+    /// Transition rate for an decreasing VDD voltage excursion
     uint32_t ext_vrm_transition_rate_dec_uv_per_us;
 
-    //Delay to account for VDD rail setting
+    /// Delay to account for VDD rail setting
     uint32_t ext_vrm_stabilization_time_us;
 
-    //External VRM transition step size
+    /// External VRM transition step size
     uint32_t ext_vrm_step_size_mv;
 
-    //Nest frequency in Mhz. This is used by FIT interrupt
+    /// Nest frequency in Mhz. This is used by FIT interrupt
     uint32_t nest_frequency_mhz;
 
-    //Precalculated Pstate-Voltage Slopes
+    /// Precalculated Pstate-Voltage Slopes
     uint16_t PsVSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
 
-    //Precalculated Voltage-Pstates Slopes
+    /// Precalculated Voltage-Pstates Slopes
     uint16_t VPsSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
 
 
@@ -251,5 +250,5 @@ typedef struct
 #ifdef __cplusplus
 } // end extern C
 #endif
-
+#endif    /* __ASSEMBLER__ */
 #endif    /* __P9_PSTATES_PGPE_H__ */
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
index c7456835..5e8ac7a1 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
@@ -49,6 +49,7 @@
 #define MAX_PSTATE_TABLE_ENTRIES  128
 #define GEN_PSTATES_TBL_MAGIC    0x50535441424c3030 //PSTABL00 (last two ASCII characters indicate version number)
 
+#ifndef __ASSEMBLER__
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -137,5 +138,5 @@ typedef struct
 #ifdef __cplusplus
 } // end extern C
 #endif
-
+#endif    /* __ASSEMBLER__ */
 #endif    /* __P9_PSTATES_TABLE_H__ */
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/Makefile b/import/chips/p9/procedures/ppe_closed/pgpe/Makefile
index 1a291ab7..b48fdfb8 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/Makefile
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/Makefile
@@ -22,61 +22,35 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-ifndef BASE_OBJDIR
-BASE_OBJDIR = $(abspath ./obj/)
-endif
+include img_defs.mk
 
-ifndef BASE_SRCDIR
-BASE_SRCDIR = $(abspath ./)
-endif
+#Pull in object file names for the top directory
+include topfiles.mk
 
-#CME_OBJDIR = $(abspath ../cme/obj/)
-#CME_SRCDIR = $(abspath ../cme/)
-PGPE_OBJDIR = $(BASE_OBJDIR)
-PGPE_SRCDIR = $(BASE_SRCDIR)
+OBJS := $(addprefix $(OBJDIR)/, $(TOP_OBJECTS))
+LINK_OBJS = $(OBJS)
+LINK_SCRIPT = pstate_gpe/linkppmr.cmd
 
-ifndef PPETRACEPP_DIR
-export PPETRACEPP_DIR = $(abspath ../../ppe/tools/ppetracepp)
-endif
+lib_pstate_gpe    := pstate_gpe
+lib_boot_loader := boot
+libraries       := $(lib_boot_loader) $(lib_pstate_gpe)
 
-THASH   = $(PPETRACEPP_DIR)/tracehash.pl
+.PHONY: all $(libraries) ppmr_header
+all: $(libraries) ppmr_header
+	make qpmr_header
 
-#CME_IMAGE_NAME = cme
-GPE_IMAGE_NAME = pstate_gpe
+$(libraries) :
+	$(MAKE) --directory=$@ $(TARGET)
+	@echo 'Directory $(TARGET)'
+	$(if $(TARGET), $(MAKE) $(TARGET))
 
-#NEEDED_IMAGES = \
- #    $(CME_OBJDIR)/$(CME_IMAGE_NAME)/$(CME_IMAGE_NAME).out \
-     $(PGPE_OBJDIR)/$(GPE_IMAGE_NAME)/$(GPE_IMAGE_NAME).out
-NEEDED_IMAGES = \
-     $(PGPE_OBJDIR)/$(GPE_IMAGE_NAME)/$(GPE_IMAGE_NAME).out
+ppmr_header: p9_pgpe_img_edit.c $(LINK_OBJS) pstate_gpe/linkqpmr.cmd
+	g++ p9_pgpe_img_edit.c -o $(OBJDIR)/pgpeImgEdit $(INCLUDES)
+	$(LD) -T$(LINK_SCRIPT) -o $(OBJDIR)/ppmr_header.bin -Map $(OBJDIR)/ppmr.map -s $(OBJDIR)/p9_pgpe_qpmr.o
+	$(OBJDIR)/pgpeImgEdit $(OBJDIR)/pstate_gpe/pstate_gpe.bin $(OBJDIR)/pstate_gpe/pstate_gpe.bin
+	@echo "Done editing pgpe image....."
+	$(OBJDIR)/pgpeImgEdit $(OBJDIR)/ppmr_header.bin $(OBJDIR)/pstate_gpe/pstate_gpe.bin
+	@echo "Done editing ppmr images....."
 
-
-#default is to build images
-needed_images: $(NEEDED_IMAGES)
-
-#run: $(NEEDED_IMAGES)
-#	$(SIMICS_WS)/simics \
-#	           -e '$$cme_binary_to_load=$(CME_OBJDIR)/$(CME_IMAGE_NAME)/$(CME_IMAGE_NAME).out' \
-#	           -e '$$gpe_binary_to_load=$(PGPE_OBJDIR)/$(GPE_IMAGE_NAME)/$(GPE_IMAGE_NAME).out' \
-#	           modelsetup.simics
-
-
-
-#clean the obj directory
 clean:
-#	rm -fr $(CME_OBJDIR)/$(CME_IMAGE_NAME)
-	rm -fr $(PGPE_OBJDIR)/$(GPE_IMAGE_NAME)
-
-#make binary application images
-#$(CME_OBJDIR)/$(CME_IMAGE_NAME)/$(CME_IMAGE_NAME).out:
-#	(cd $(CME_SRCDIR) && make && make fmode && make tracehash)
-
-$(PGPE_OBJDIR)/$(GPE_IMAGE_NAME)/$(GPE_IMAGE_NAME).out:
-	(cd $(PGPE_SRCDIR)/$(GPE_IMAGE_NAME) && make && make fmode && make tracehash)
-
-# collect all of the trace hash files for all OCC images into a single trexStringFile
-.PHONY : tracehash
-tracehash:
-	mkdir -p $(BASE_OBJDIR)
-	$(THASH) -c -d $(BASE_OBJDIR) -s $(BASE_OBJDIR)/combStringFile
-                 
+	rm -fr $(OBJDIR)
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_copier.S b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_copier.S
index e18fb9c3..37ca8696 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_copier.S
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_copier.S
@@ -24,17 +24,16 @@
 /* IBM_PROLOG_END_TAG                                                     */
 
         .nolist
-#include <ppe42_asm.h>
 #include <pgpe_boot_defines.H>
         .list
 
-	.section .loader_text, "ax", @progbits
+        .section .loader_text, "ax", @progbits
 
 __vectors:
 
     .org __vectors + 0x0000
 __machine_check:
-        b .
+        trap
 
     .org __vectors + 0x0040
     .global __system_reset
@@ -43,67 +42,88 @@ __system_reset:
 
     .org __vectors + 0x0060
 __data_storage:
-	b .
+        trap
 
     .org __vectors + 0x0080
 __instruction_storage:
-	b .
+        trap
 
     .org __vectors + 0x00A0
 __external_interrupt_vector:
-	b .
+        trap
 
     .org __vectors + 0x00C0
 __alignment_exception:
-	b .
+        trap
 
     .org __vectors + 0x00E0
 __program_exception:
-	b .
+        trap
 
     .org __vectors + 0x0100
 __dec_interrupt:
-	b .
+        trap
 
     .org __vectors + 0x0120
 __fit_interrupt:
-	b .
+        trap
 
     .org __vectors + 0x0140
 __watchdog_interrupt:
-	b .
+        trap
 
 __bootCopier:
-	//load r3 with BASE_
-    _liw    %r3, HOMER_BOOT_LOADER_LENGTH_ADDR
+    ## Address where the Boot loader will be loaded in SRAM (Destination address)
+    _liw   %GPR_BL_SRAM_ADDR, SRAM_PGPE_BOOT_LOADER_ADDR
 
-	_liw    %r7, HOMER_BOOT_LOADER_OFFSET_ADDR
+    ## Base address of PPMR header, also the PGPE base address
+    _liw   %GPR_PPMR_ADDR, PPMR_HEADER_ADDR
 
-	//load r4 with address where bootLoader will be loaded in SRAM e.g 0xFFFE8000 (Destination address)
-    _liw    %r4, SRAM_PGPE_BOOT_LOADER_ADDR # dest
+    ## Location in PPMR header where the offset of Boot loader is present
+    _liw   %GPR_BL_HOMER, HOMER_BOOT_LOADER_OFFSET_ADDR
 
-	//load r9 with PPMR header address
-	_liw    %r9, PPMR_HEADER_ADDR
+    ## Fetch offset of Boot loader
+    lwz    GPR_BL_HOMER_ADDR, OFFSET(GPR_BL_HOMER)
 
-	//size of image in bytes
-	lwz    r5, 0(r3)
-    li    r6, 3
-    srw   r5, r5, r6    # r5 contains number of bytes, divide by 8 will give number of double words
-    mtctr   r5          # set the counter for loop
+    ## Compute the source address of Boot loader (address in HOMER)
+    add   GPR_BL_HOMER_ADDR, GPR_BL_HOMER_ADDR, GPR_PPMR_ADDR
 
-	// calculating bootLoader image loaded address
-	lwz     r8, 0(r7)   # offset of bootLoader section  in Homer
-    adde    r8, r8, r9  # add base address to offset to get absolute bootLoader address in Homer
+    ## Location in PPMR header where the length of boot loader is present
+    _liw   %GPR_BL_HOMER, HOMER_BOOT_LOADER_LENGTH_ADDR
 
+    ## Boot Loader size(in Bytes)
+    lwz    GPR_BL_SIZE, OFFSET(GPR_BL_HOMER)
+    srwi    GPR_BL_SIZE, GPR_BL_SIZE, PGPE_DIV_8
+
+    ## If bootLoader size is 0 then failure
+    cmpwbeq    %GPR_BL_SIZE, 00, BCFAIL
+
+    ## Set the counter for copy loop
+    mtctr  GPR_BL_SIZE
+
+    ## Copy the bootLoader from HOMER to OCC SRAM
 copy_loop:
-    lvd    d28, 0(r8)  # Load Double word
-    stvd   d28, 0(r4)  # Destination address
-	addi   r8, r8, 8   # Increasing source address
-	addi   r4, r4, 8   # Increasing Dest address
-	bdnz   copy_loop   # Keep repeating the address.
-
-	## Using blr command:
-    _liw  %r6,   SRAM_PGPE_BOOT_LOADER_RESET_ADDR
-    mtlr  r6
+    lvd    DATA_WR, OFFSET(GPR_BL_HOMER_ADDR)   # Load Double word
+    stvd   DATA_WR, OFFSET(GPR_BL_SRAM_ADDR)    # Destination address
+    addi   GPR_BL_HOMER_ADDR, GPR_BL_HOMER_ADDR, NXT_BLK_OFF    # Increasing source address
+    addi   GPR_BL_SRAM_ADDR, GPR_BL_SRAM_ADDR, NXT_BLK_OFF    # Increasing Dest address
+    bdnz   copy_loop    # Keep repeating the address.
+
+    ##FIXME 167543  Shall be uncommented when availability of memory based system improves
+    ## Write the success status "CP" to PPMR header
+    ##_liw   %GPR_STAT_ADDR, BCPASS_STAT
+    ##stw   GPR_STAT_ADDR, OFF_STAT_WR(GPR_PPMR_ADDR)
+
+BRANCH:
+    ## branch to the system_reset location for bootLoader to be executed
+    _liw   %GPR_TEMP,   SRAM_PGPE_BOOT_LOADER_RESET_ADDR
+    mtlr   GPR_TEMP
     blr
+
+    ## Write the failure status "CF" to PPMR header
+BCFAIL:
+    ##FIXME 167543  Shall be uncommented when availability of memory based system improves
+    ##_liw  %GPR_STAT_ADDR, BCFAIL_STAT
+    ##stw   GPR_STAT_ADDR, OFF_STAT_WR(GPR_PPMR_ADDR)
+    trap
     .epilogue __bootCopier
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_defines.H b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_defines.H
index fa68aaa9..3e4f4afd 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_defines.H
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_defines.H
@@ -29,39 +29,119 @@
 #ifndef __HCD_GPE_BOOT_DEFINES_H__
 #define __HCD_GPE_BOOT_DEFINES_H__
 
+#include <ppe42_asm.h>
+
+
+// Base address of HOMER
 #define HOMER_BASE_ADDR 0x80000000
+
+// SRAM Base address
 #define SRAM_BASE_ADDR  0xFFF00000
 
-#define PGPE_NUM 2
-#define HOMER_PGPE_REGION 3   // Zero origin; 1MB per region
+// SRAM Base address of PGPE region
+#define SRAM_PGPE_BASE_ADDR 0xFFF20000
 
+// Address of PGPE HCODE in HOMER, to be loaded in IVPR
+#define PGPE_IVPR_OCI_ADDR 0xC0020008
 
-// PGPE Boot
-#define PPMR_HEADER_ADDR (HOMER_BASE_ADDR + HOMER_PGPE_REGION*1024*1024)
+// 48KB allocated for PGPE in SRAM
+#define SRAM_PGPE_MEM_ALLOC (48 * 1024)
+
+// The numeric identity of PGPE - GPE2
+#define PGPE_NUM 0x2
+
+// The position of the PGPE region in HOMER
+#define HOMER_PGPE_REGION 0x3   // Zero origin; 1MB per region
+
+// Offset in PPMR header at which the BL offset is stored
 #define HOMER_BOOT_LOADER_OFFSET_HDR_LOC 0x10
+
+// Offset in PPMR header at which the BL length is stored
 #define HOMER_BOOT_LOADER_LENGTH_HDR_LOC 0x14
-#define HOMER_BOOT_LOADER_OFFSET_ADDR (PPMR_HEADER_ADDR +  HOMER_BOOT_LOADER_OFFSET_HDR_LOC)
-#define HOMER_BOOT_LOADER_LENGTH_ADDR (PPMR_HEADER_ADDR +  HOMER_BOOT_LOADER_LENGTH_HDR_LOC)
 
+// Offset in PPMR header at which the execution status will be written
+#define STATE_WRITE_OFFSET 0x5A
+
+// Reset offset
+#define RESET_OFFSET 0x40
+
+// Size of PPMR header (bytes)
+#define PPMR_HEADER_SIZE 0x200
 
+// Offset in PPMR header, where the HCODE offset resides
+#define SRAM_PGPE_HCODE_OFFSET_BYTE 0x28
 
-#define SRAM_PGPE_MEM_ALLOC (64 * 1024)
-#define SRAM_PGPE_BASE_ADDR (SRAM_BASE_ADDR + (PGPE_NUM * SRAM_PGPE_MEM_ALLOC))
-#define SRAM_GPE_HCODE_RESET_ADDR (SRAM_PGPE_BASE_ADDR + 0x40)
+// Offset in PPMR header, where the HCODE length resides
+#define SRAM_PGPE_HCODE_LENGTH_BYTE 0x50
 
-///BOOT Copier will copy in last 1k of SRAM PGPE memory section
+// Status codes for failure/success of Boot loader and copier
+#define BCPASS_STAT 0x4350 // Ascii of "CP" -> Boot Copier passed
+#define BCFAIL_STAT 0x4346 // Ascii of "CF" -> Boot Copier failed
+#define BLPASS_STAT 0x4C50 // Ascii of "LP" -> Boot Loader passed
+#define BLFAIL_STAT 0x4C46 // Ascii of "LF" -> Boot Loader failed
+
+
+// Absolute base address of PPMR Header in HOMER
+#define PPMR_HEADER_ADDR (HOMER_BASE_ADDR + HOMER_PGPE_REGION*1024*1024)
+
+// Absolute address of BL offset in PPMR header in HOMER
+#define HOMER_BOOT_LOADER_OFFSET_ADDR (PPMR_HEADER_ADDR +  HOMER_BOOT_LOADER_OFFSET_HDR_LOC)
+
+// Absolute address of BL length in PPMR header in HOMER
+#define HOMER_BOOT_LOADER_LENGTH_ADDR (PPMR_HEADER_ADDR +  HOMER_BOOT_LOADER_LENGTH_HDR_LOC)
+
+// Address in PPMR header in HOMER where the copie/loader status will be written
+#define STATE_WRITE_ADDR (PPMR_HEADER_ADDR + STATE_WRITE_OFFSET)
+
+// Base Address of Boot Loader in SRAM PGPE region
 #define SRAM_PGPE_BOOT_LOADER_ADDR (SRAM_PGPE_BASE_ADDR + SRAM_PGPE_MEM_ALLOC - 1024)
-#define SRAM_PGPE_BOOT_LOADER_RESET_ADDR (SRAM_PGPE_BOOT_LOADER_ADDR + 0x40)
 
-///BOOT Loader will copy in second to last 1k of SRAM_PGPE_MEMORY_SECTION
+// Base address of PPMR header in SRAM PGPE Region
 #define SRAM_PGPE_PPMR_ADDR (SRAM_PGPE_BOOT_LOADER_ADDR - 1024)
-#define PPMR_HEADER_SIZE 512
-#define SRAM_PGPE_HCODE_OFFSET_BYTE 40
-#define SRAM_PGPE_HCODE_LENGTH_BYTE 44
-#define SRAM_PGPE_HCODE_OFFSET_ADDR PPMR_HEADER_ADDR + SRAM_PGPE_HCODE_OFFSET_BYTE
-#define SRAM_PGPE_HCODE_LENGTH_ADDR PPMR_HEADER_ADDR + SRAM_PGPE_HCODE_LENGTH_BYTE
 
+// Address of reset vector in SRAM to which branch happens after BL is loaded
+#define SRAM_PGPE_BOOT_LOADER_RESET_ADDR (SRAM_PGPE_BOOT_LOADER_ADDR + RESET_OFFSET)
+
+// Address of reset vector in SRAM to which branch happens after HCODE is loaded
+#define SRAM_PGPE_HCODE_RESET_ADDR (SRAM_PGPE_BASE_ADDR + RESET_OFFSET)
+
+// Base address of PGPE HCODE offset in SRAM
+#define SRAM_PGPE_HCODE_OFFSET_ADDR SRAM_PGPE_PPMR_ADDR + SRAM_PGPE_HCODE_OFFSET_BYTE
+
+// Base address of PGPE image length in SRAM
+#define SRAM_PGPE_IMAGE_LENGTH_ADDR SRAM_PGPE_PPMR_ADDR + SRAM_PGPE_HCODE_LENGTH_BYTE
+
+
+// Constants used in copier and loader
+#define OFFSET 0
+#define OFF_STAT_WR 0x54
+#define PGPE_DIV_8 0x03
+#define NXT_BLK_OFF 0x8
+
+
+// Register mnemonics used in Boot Copier
+#define GPR_BL_SRAM_ADDR r3
+#define GPR_PPMR_ADDR r4
+#define GPR_BL_HOMER r5
+#define GPR_BL_HOMER_ADDR r6
+#define GPR_BL_SIZE r7
+
+// register mnemonics used in Boot Copier and Loader
+#define GPR_TEMP r8
+#define DATA_WR d28
+#define GPR_STAT_ADDR r9
+#define GPR_TRAP r31
+#define ENABLE_PGPE_TRAP 0x100
 
-// PGPE Boot
+// Register mnemonics used in Boot Loader
+#define GPR_PPMR_HOMER_ADDR r3
+#define GPR_PPMR_SRAM_ADDR  r4
+#define GPR_SIZE            r5
+#define GPR_SRAM_PGPE_ADDR  r7
+#define GPR_SRAM_HCODE_OFF_ADDR r6
+#define GPR_HOMER_PAYLOAD_OFF  r9
+#define GPR_ADDR_PAYLOAD_HOMER r4
+#define GPR_SRAM_IMG_LEN_ADDR r6
+#define BL_START_SRAM_ADDRESS_REG r28
 
 #endif  // __HCD_GPE_BOOT_DEFINES_H__
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_loader.S b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_loader.S
index 765a0a40..10b4d5fe 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_loader.S
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/pgpe_boot_loader.S
@@ -23,16 +23,15 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
        .nolist
-#include <ppe42_asm.h>
 #include <pgpe_boot_defines.H>
-	.list
+        .list
 
-	.global __vectors
+        .global __vectors
 __vectors:
 
     .org __vectors + 0x0000
 __machine_check:
-        b .
+        trap
 
     .org __vectors + 0x0040
     .global __system_reset
@@ -41,98 +40,136 @@ __system_reset:
 
     .org __vectors + 0x0060
 __data_storage:
-	b .
+        trap
 
     .org __vectors + 0x0080
 __instruction_storage:
-	b .
+        trap
 
     .org __vectors + 0x00A0
 __external_interrupt_vector:
-	b .
+        trap
 
     .org __vectors + 0x00C0
 __alignment_exception:
-	b .
+        trap
 
     .org __vectors + 0x00E0
 __program_exception:
-	b .
+        trap
 
     .org __vectors + 0x0100
 __dec_interrupt:
-	b .
+        trap
 
     .org __vectors + 0x0120
 __fit_interrupt:
-	b .
+        trap
 
     .org __vectors + 0x0140
 __watchdog_interrupt:
-	b .
+        trap
 
 __bootLoader:
 
-	######################
-	## PPMR Header Copy
-	######################
-	## cal source Address
-	_liw %r10, SRAM_PGPE_HCODE_LENGTH_ADDR
-	_liw  %r3, PPMR_HEADER_ADDR
+        ######################
+        ## PPMR Header Copy
+        ######################
 
-	## Cal Destination Address(in r4)
-	_liw %r4, SRAM_PGPE_PPMR_ADDR
+        ## update IVPR to Boot Loader Base Addr in OCC SRAM
 
-        ## Find double words(in r5).
-  	_liw %r5, PPMR_HEADER_SIZE
-       	li r6, 3
-	srw r5,r5,r6
+        _liw    %BL_START_SRAM_ADDRESS_REG, SRAM_PGPE_BOOT_LOADER_ADDR
+        _liw    %GPR_TEMP, PGPE_IVPR_OCI_ADDR
+         stw     BL_START_SRAM_ADDRESS_REG, OFFSET (GPR_TEMP)
 
-	## start copying
-	mtctr r5
+        ## Enable Trap
+         lis     GPR_TEMP, ENABLE_PGPE_TRAP
+         mtdbcr  GPR_TEMP
 
+        ## Address of PPMR in HOMER(source address)
+        _liw  %GPR_PPMR_HOMER_ADDR, PPMR_HEADER_ADDR
+
+        ## Address of PPMR in SRAM(destination Address)
+        _liw %GPR_PPMR_SRAM_ADDR, SRAM_PGPE_PPMR_ADDR
+
+        ## Load the size of PPMR header (in double words)
+        _liw %GPR_SIZE, PPMR_HEADER_SIZE
+        srwi GPR_SIZE, GPR_SIZE, PGPE_DIV_8
+
+        ## Set the counter for copying
+        mtctr GPR_SIZE
+
+        ## Copy the PPMR header from HOMER to OCC SRAM
 PPMR_header_copy_loop:
-	lvd d28,0(r3)
-	stvd d28,0(r4)
-	addi r3,r3,8
-	addi r4,r4,8
-	bdnz PPMR_header_copy_loop
-
-	#########################
-	## Copy PGPE Header/Exe
-	#########################
-	## Calculate Source address(in r8)
-        _liw %r6, SRAM_PGPE_HCODE_OFFSET_ADDR
-	_liw %r9, PPMR_HEADER_ADDR
-	lwz  r7, 0(r6)
-	adde r8,r9,r7
-
-	## Calculate Destination address
-	_liw %r4, SRAM_PGPE_BASE_ADDR
-
-	##Find the double word counts
-	lwz r5, 0(r10)
-	nop
-	li r6, 3
-	srw r5,r5,r6
-
-	## start copying
-	mtctr r5
+        lvd  DATA_WR, OFFSET(GPR_PPMR_HOMER_ADDR)
+        stvd DATA_WR, OFFSET(GPR_PPMR_SRAM_ADDR)
+        addi GPR_PPMR_HOMER_ADDR, GPR_PPMR_HOMER_ADDR, NXT_BLK_OFF
+        addi GPR_PPMR_SRAM_ADDR, GPR_PPMR_SRAM_ADDR, NXT_BLK_OFF
+        bdnz PPMR_header_copy_loop
 
+        #########################
+        ## Copy PGPE Header/Exe
+        #########################
 
-payload_copy_loop:
-	lvd d28,0(r8)
-	stvd d28,0(r4)
-	addi r8,r8,8
-	addi r4,r4,8
-	bdnz payload_copy_loop
+        ## Address in SRAM where the payload will have to be copied (Destination address)
+        _liw %GPR_SRAM_PGPE_ADDR, SRAM_PGPE_BASE_ADDR
+
+        ## Address in SRAM where the offset of payload will be found
+        _liw %GPR_SRAM_HCODE_OFF_ADDR, SRAM_PGPE_HCODE_OFFSET_ADDR
 
-	########################
-	## branch to hcode
-	########################
+        ## Base address of PPMR header in HOMER
+        _liw %GPR_PPMR_HOMER_ADDR, PPMR_HEADER_ADDR
 
-	_liw %r6, SRAM_GPE_HCODE_RESET_ADDR
-        mtlr r6
-	blr
+        ## Offset of HCODE from PPMR header
+        lwz  GPR_HOMER_PAYLOAD_OFF, OFFSET(GPR_SRAM_HCODE_OFF_ADDR)
 
-	.epilogue __bootLoader
+        ## Compute the loaction of the payload in HOMER (source address)
+        add GPR_ADDR_PAYLOAD_HOMER, GPR_PPMR_HOMER_ADDR, GPR_HOMER_PAYLOAD_OFF
+
+        ## Address in SRAM where the length of payload will be found
+        _liw %GPR_SRAM_IMG_LEN_ADDR, SRAM_PGPE_IMAGE_LENGTH_ADDR
+
+        ## Size of payload (in double words)
+        lwz GPR_SIZE, OFFSET(GPR_SRAM_IMG_LEN_ADDR)
+        srwi GPR_SIZE, GPR_SIZE, PGPE_DIV_8
+
+        ## If PGPE payload size is 0 then fail
+        cmpwbeq    %GPR_SIZE, 00, BLFAIL
+
+        ## Set the counter for copying
+        mtctr GPR_SIZE
+
+        ## Start copying
+payload_copy_loop:
+        lvd DATA_WR, OFFSET(GPR_ADDR_PAYLOAD_HOMER)
+        stvd DATA_WR, OFFSET(GPR_SRAM_PGPE_ADDR)
+        addi GPR_ADDR_PAYLOAD_HOMER, GPR_ADDR_PAYLOAD_HOMER, NXT_BLK_OFF
+        addi GPR_SRAM_PGPE_ADDR, GPR_SRAM_PGPE_ADDR, NXT_BLK_OFF
+        bdnz payload_copy_loop
+
+        ##FIXME 167543  Shall be uncommented when availability of memory based system improves
+        ## Write the success status "LP" to PPMR header
+        ##_liw   %GPR_STAT_ADDR, BLPASS_STAT
+        ##stw  GPR_STAT_ADDR, OFF_STAT_WR(GPR_PPMR_HOMER_ADDR)
+
+        ########################
+        ## branch to hcode
+        ########################
+branch:
+        ## Reset address to which branch must take place
+        _liw %GPR_TEMP, SRAM_PGPE_HCODE_RESET_ADDR
+        mtlr GPR_TEMP
+
+        ## Setup the IVPR for the Hcode
+        _liw    %GPR_PPMR_HOMER_ADDR, SRAM_PGPE_BASE_ADDR
+        _liw    %GPR_ADDR_PAYLOAD_HOMER, PGPE_IVPR_OCI_ADDR
+        stw     GPR_PPMR_HOMER_ADDR, OFFSET(GPR_ADDR_PAYLOAD_HOMER)
+        blr
+
+        //Write the failure status "LF" to PPMR header
+BLFAIL:
+        ##FIXME 167543  Shall be uncommented when availability of memory based system improves
+        ##_liw  %GPR_STAT_ADDR, BLFAIL_STAT
+        ##stw   GPR_STAT_ADDR, OFF_STAT_WR(GPR_PPMR_HOMER_ADDR)
+        trap
+        .epilogue __bootLoader
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/link.cmd b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/link.cmd
index 5876d922..6059a2b9 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/link.cmd
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/link.cmd
@@ -48,6 +48,9 @@ MEMORY
 // to ensure that table is pulled in by the linker even though PPE code
 // never references it.
 EXTERN(pk_debug_ptrs);
+EXTERN(g_pgpe_magic_number);
+EXTERN(_PK_INITIAL_STACK);
+EXTERN(_END_IMAGE);
 
 SECTIONS
 {
@@ -58,6 +61,14 @@ SECTIONS
     _VECTOR_START = .;
 
     .vectors  _VECTOR_START  : { *(.vectors) } > sram
+      
+    ///////////////////////////////////////////////////////////////////////////
+    //
+    // PGPE Image Header
+    //
+    ///////////////////////////////////////////////////////////////////////////
+    _PGPE_IMG_HEADER = _VECTOR_START + PGPE_HEADER_OFFSET;
+    .pgpe_image_header _PGPE_IMG_HEADER : { *(.pgpe_image_header) } > sram
 
     ///////////////////////////////////////////////////////////////////////////
     //
@@ -126,7 +137,6 @@ SECTIONS
 
         . = ALIGN(8);
         _PK_INITIAL_STACK_LIMIT = .;
-
         FILL(0xA55A);
         . = . + INITIAL_STACK_SIZE;
         . = ALIGN(8);
@@ -137,4 +147,5 @@ SECTIONS
     _PGPE_END = .;
     _PGPE_SIZE = . - SRAM_START;
 
+
 }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/linkppmr.cmd b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/linkppmr.cmd
new file mode 100644
index 00000000..22e47508
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/linkppmr.cmd
@@ -0,0 +1,37 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/linkppmr.cmd $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+OUTPUT_FORMAT(binary)
+MEMORY
+{
+    ppmrHeader(rw) : ORIGIN = 0, LENGTH = 512
+}
+
+    SECTIONS
+{
+    . = 0;
+    .ppmr :
+    { *(.ppmr) } > ppmrHeader
+}
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_edit.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_edit.mk
new file mode 100644
index 00000000..fd558fa8
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_edit.mk
@@ -0,0 +1,36 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_edit.mk $
+#
+# OpenPOWER HCODE Project
+#
+# COPYRIGHT 2016,2017
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+EXE=pstate_gpeImgEdit
+IMAGE_DEPS+=pstate_gpeImgEdit
+OBJS=p9_pgpe_img_edit.o
+$(call ADD_EXE_INCDIR,$(EXE),$(ROOTPATH)/chips/p9/procedures/hwp/lib)
+$(call BUILD_EXE)
+
+
+EXE=ppmr_headerImgEdit
+IMAGE_DEPS+=ppmr_headerImgEdit
+OBJS=p9_pgpe_img_edit.o
+$(call ADD_EXE_INCDIR,$(EXE),$(ROOTPATH)/chips/p9/procedures/hwp/lib)
+$(call BUILD_EXE)
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
index f366fcca..a49f009f 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
@@ -46,6 +46,8 @@ void p9_pgpe_gen_occ_pstate_tbl(GeneratedPstateInfo* gpi);
 //
 void p9_pgpe_gen_pstate_info()
 {
+    PK_TRACE_DBG("> p9_pgpe_gen_pstate_info to memory 0x%X",
+                 (uint32_t)G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset);
     int p;
     //Get GlobalPstateParmBlock offset from pgpe_header
     uint32_t* pstate_tbl_memory_offset  = G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset;
@@ -83,6 +85,7 @@ void p9_pgpe_gen_pstate_info()
 
     //Generate Pstate table for OCC in SRAM
     p9_pgpe_gen_occ_pstate_tbl(&G_gpi);
+    PK_TRACE_DBG("< p9_pgpe_gen_pstate_info");
 }
 
 //
@@ -92,6 +95,7 @@ void p9_pgpe_gen_pstate_info()
 //
 void p9_pgpe_gen_raw_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* gpi)
 {
+    PK_TRACE_DBG(">> p9_pgpe_gen_raw_pstates");
     int32_t p;
     uint32_t freq_khz_offset = 0, highest_pstate;
     highest_pstate = G_operating_points[VPD_PT_SET_SYSP][POWERSAVE].pstate;
@@ -111,6 +115,8 @@ void p9_pgpe_gen_raw_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* g
         gpi->raw_pstates[p].vdm_thresholds = 0;
         freq_khz_offset += gppb->frequency_step_khz;
     }
+
+    PK_TRACE_DBG("<< p9_pgpe_gen_raw_pstates");
 }
 
 //
@@ -120,6 +126,7 @@ void p9_pgpe_gen_raw_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* g
 //
 void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* gpi)
 {
+    PK_TRACE_DBG(">> p9_pgpe_gen_biased_pstates");
     int32_t p;
     uint32_t freq_khz_offset = 0, highest_pstate;
     highest_pstate = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
@@ -142,6 +149,8 @@ void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo
         gpi->biased_pstates[p].vdm_thresholds = 0;
         freq_khz_offset += gppb->frequency_step_khz;
     }
+
+    PK_TRACE_DBG("<< p9_pgpe_gen_biased_pstates");
 }
 
 
@@ -152,6 +161,8 @@ void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo
 //
 void p9_pgpe_gen_occ_pstate_tbl(GeneratedPstateInfo* gpi)
 {
+    PK_TRACE_DBG(">> p9_pgpe_gen_occ_pstate_tbl to SRAM 0x%X",
+                 (uint32_t)G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr);
     int p;
     OCCPstateTable_t* opst = (OCCPstateTable_t*)G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr;
     opst->entries = (G_pgpe_header_data->g_pgpe_occ_pstables_len) / sizeof(OCCPstateTable_entry_t);
@@ -162,4 +173,6 @@ void p9_pgpe_gen_occ_pstate_tbl(GeneratedPstateInfo* gpi)
         opst->table[p].frequency_mhz = gpi->biased_pstates[p].frequency_mhz ;
         opst->table[p].internal_vdd_vid  = gpi->biased_pstates[p].internal_vid;
     }
+
+    PK_TRACE_DBG("<< p9_pgpe_gen_occ_pstate_tbl");
 }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
index 75261625..9c3cbdcb 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
@@ -25,9 +25,14 @@
 #include "p9_pgpe_header.h"
 #include "pstate_pgpe_occ_api.h"
 
+// @todo The PGPE start and the length needs to come from the occ_sram_layout.h
+#define OCC_PGPE_SRAM_ADDR_START 0xfff20000
+#define OCC_PGPE_SRAM_SIZE       0xC000      // 48KB
+
 //OCC Shared SRAM starts at bottom 2K of PGPE OCC SRAM space
-#define OCC_PGPE_SRAM_ADDR_START (0xfff20000)
-#define OCC_SHARED_SRAM_ADDR_START (OCC_PGPE_SRAM_ADDR_START + 0x10000 - 0x800)
+#define OCC_SHARED_SRAM_ADDR_LENGTH 2*1024
+#define OCC_SHARED_SRAM_ADDR_START \
+    (OCC_PGPE_SRAM_ADDR_START + OCC_PGPE_SRAM_SIZE - OCC_SHARED_SRAM_ADDR_LENGTH)
 
 PgpeHeader_t* G_pgpe_header_data;
 extern PgpeHeader_t* _PGPE_IMG_HEADER __attribute__ ((section (".pgpe_image_header")));
@@ -44,25 +49,49 @@ void p9_pgpe_header_init()
 void p9_pgpe_header_fill()
 {
     PK_TRACE_DBG("> p9_pgpe_header_fill");
+
+    uint32_t i;
+
     HcodeOCCSharedData_t* occ_shared_data = (HcodeOCCSharedData_t*)
                                             OCC_SHARED_SRAM_ADDR_START; //Bottom 2K of PGPE OCC Sram Space
-    G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr = (uint32_t*)&occ_shared_data->pstate_table;//OCC Pstate table address
-    G_pgpe_header_data->g_pgpe_occ_pstables_len  = sizeof(OCCPstateTable_t);//OCC Pstate table length
+
+    PK_TRACE_DBG("   occ_shared_data = 0x%0xX\n", (uint32_t)occ_shared_data );
+
+    G_pgpe_header_data->g_pgpe_shared_sram_addr = (uint32_t*)OCC_SHARED_SRAM_ADDR_START;
+    G_pgpe_header_data->g_pgpe_shared_sram_len = OCC_SHARED_SRAM_ADDR_LENGTH;
+
+    PK_TRACE_DBG("   Zeroing occ_shared_data region: start 0x%X length 0x%X",
+                 (uint32_t)OCC_SHARED_SRAM_ADDR_START,
+                 OCC_SHARED_SRAM_ADDR_LENGTH);
+
+    uint64_t* occ_shared_data_indx = (uint64_t*)OCC_SHARED_SRAM_ADDR_START;
+
+    for (i = 0; i < OCC_SHARED_SRAM_ADDR_LENGTH / sizeof(uint64_t); ++i)
+    {
+        *occ_shared_data_indx = 0;
+        occ_shared_data_indx++;
+    }
+
+    G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr = (uint32_t*)
+            &occ_shared_data->pstate_table; //OCC Pstate table address
+    G_pgpe_header_data->g_pgpe_occ_pstables_len  = sizeof(OCCPstateTable_t); //OCC Pstate table length
+
     G_pgpe_header_data->g_pgpe_beacon_addr = (uint32_t*)&occ_shared_data->pgpe_beacon;
     G_pgpe_header_data->g_quad_status_addr = (uint32_t*)&occ_shared_data->quad_pstate_0;
 
-    // @todo: change to value from header
-    G_pgpe_header_data->g_pgpe_gppb_sram_addr  = (uint32_t*)0xfff27000;//GPPB Sram Offset
-    /*
-     *
-     *     //GPPB Sram Offset
-     *     G_pgpe_header_data->g_pgpe_gppb_sram_addr = (uint32_t*)(OCC_PGPE_SRAM_ADDR_START +
-     *             G_pgpe_header_data->g_pgpe_hcode_length)
-     */
-
+    //GPPB Sram Offset
+    G_pgpe_header_data->g_pgpe_gppb_sram_addr = (uint32_t*)(OCC_PGPE_SRAM_ADDR_START +
+            G_pgpe_header_data->g_pgpe_hcode_length);
 
     G_pgpe_header_data->g_pgpe_wof_state_addr = (uint32_t*)&occ_shared_data->pgpe_wof_state;
     G_pgpe_header_data->g_req_active_quad_addr = (uint32_t*)&occ_shared_data->req_active_quads;
 
+#if !BOOT_TEMP_SET_FULL_OCC_IPC_FUNC
+    PK_TRACE_INF("OCC IPC Immediate Response mode set");
+    G_pgpe_header_data->g_pgpe_qm_flags = (uint16_t)(0x0080); //OCC IPC Immediate Response
+#else
+    G_pgpe_header_data->g_pgpe_qm_flags = (uint16_t)(0x0000); //OCC IPC Full Functionality
+#endif //BOOT_TEMP_SET_FULL_OCC_IPC_FUNC
+
     PK_TRACE_DBG("< p9_pgpe_header_fill");
 }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
index 7a5253c1..1dea8e2c 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
@@ -44,7 +44,7 @@ typedef struct
     uint16_t  g_pgpe_reserve1;                // Reserve field
     uint32_t  g_pgpe_reserve2;                // Reserve field
     uint32_t* g_pgpe_gppb_sram_addr;          // Offset to Global P State Parameter Block
-    uint32_t  g_pgpe_reserve3;                // Reserve field
+    uint32_t  g_pgpe_hcode_length;            // Length of PGPE Hcode
     uint32_t* g_pgpe_gppb_mem_offset;         // Offset to start of Global PS Param Block wrt start of HOMER.
     uint32_t  g_pgpe_gppb_length;             // Length of Global P State Parameter Block
     uint32_t* g_pgpe_gen_pstables_mem_offset; // Offset to PState Table wrt start of HOMER
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_image_header.S b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_image_header.S
new file mode 100644
index 00000000..b7e9d2d9
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_image_header.S
@@ -0,0 +1,33 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_image_header.S $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2016,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#Definition of a PGPE Image header to be used by PGPE Hcode when loaded in
+#SRAM. Linker script maps this 64 bit image header to an SRAM address starting from
+#0xfff20000. Some fields will be populated during Hcode image build activity. Build date,
+#version, IVPR address, __system_reset_address are populated during SGPE image build
+#process.
+
+#include <p9_hcode_image_defines.H>
+
+.pgpe_header
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c
new file mode 100644
index 00000000..d76c7b7c
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c
@@ -0,0 +1,166 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include <stdio.h>
+#include <stdint.h>
+#include <stddef.h>     /* offsetof */
+#include <netinet/in.h>
+#include <time.h>
+#include <p9_hcode_image_defines.H>
+
+enum
+{
+    PGPE_RESET_ADDR_POS  =   0x0188,
+    PGPE_RESET_ADDRESS   =   0x40,
+    PGPE_BUILD_DATE_POS  =   0x0198,
+    PGPE_BUILD_VER_POS   =   0x019C,
+    PGPE_BUILD_VER       =   0x01,
+    PPMR_BUILD_DATE_POS  =   0x18,
+    PPMR_BUILD_VER_POS   =   0x1C,
+    PGPE_IMAGE           =   1,
+    PPMR_IMAGE           =   2,
+    PPMR_PGPE_HCODE_OFF_POS  = 0x28,
+    PPMR_PGPE_HCODE_OFF_VAL  = 0xA00, //512B + 1KB + 1kB
+};
+
+int main(int narg, char* argv[])
+{
+
+    if(narg < 2)
+    {
+        printf("Usage: %s <full path to image>\n",
+               argv[0]);
+        return -1;
+    }
+
+    int imageType = PGPE_IMAGE;
+
+    uint32_t buildDatePos;
+    uint32_t buildVerPos;
+
+    FILE* pMainImage = fopen( argv[1], "r+");
+    FILE* pDependImage = fopen(argv[2], "r+");
+
+    time_t buildTime = time(NULL);
+    struct tm* headerTime = localtime(&buildTime);
+
+    do
+    {
+        if( !pMainImage )
+        {
+            printf("\n image file to edit was not found\n");
+            break;
+        }
+
+        fseek (pMainImage, 0, SEEK_END);
+        uint32_t size = ftell (pMainImage);
+        rewind(pMainImage);
+
+        uint32_t l_ppmr_pgpe_hcode_len_val = 0;
+
+        // For ekb build it's desired to detect the image type w/o special
+        // make rules. Better way?
+
+        if(size < 1024)
+        {
+            printf("                    PPMR size:     %d\n", size);
+            imageType = PPMR_IMAGE;
+            buildDatePos = offsetof(PpmrHeader_t, g_ppmr_build_date);
+            buildVerPos  = offsetof(PpmrHeader_t, g_ppmr_build_ver);
+
+            if( !pDependImage )
+            {
+                printf("\n image file to find the size was not found\n");
+                break;
+            }
+
+            fseek (pDependImage, 0, SEEK_END);
+            l_ppmr_pgpe_hcode_len_val = ftell (pDependImage);
+            rewind(pDependImage);
+            fclose(pDependImage);
+        }
+
+        uint32_t temp = 0;
+
+        if(imageType == PGPE_IMAGE)
+        {
+            printf("                    PGPE size: %d\n", size);
+            //  populating PGPE Image Header
+            //  populating RESET address
+            uint32_t l_reset_addr_pos = offsetof(PgpeHeader_t, g_pgpe_sys_reset_addr);
+            fseek (pMainImage, l_reset_addr_pos, SEEK_SET);
+            temp = PGPE_RESET_ADDRESS;
+            temp = htonl(temp);
+            fwrite(&(temp), sizeof(uint32_t), 1, pMainImage );
+
+            buildDatePos = offsetof(PgpeHeader_t, g_pgpe_build_date);
+            buildVerPos  = offsetof(PgpeHeader_t, g_pgpe_build_ver);
+        }
+
+        // build date
+        fseek( pMainImage, buildDatePos, SEEK_SET );
+        // date format same as in XIP Header YYYYMMDD
+        temp = ((headerTime->tm_mday ) |
+                ((headerTime->tm_mon + 1) << 8) |
+                (headerTime->tm_year + 1900) << 16);
+
+        printf("                    Build date:    %X pos %X\n", temp, buildDatePos);
+        temp = htonl(temp);
+        fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+
+
+        // build ver
+        printf("                    Build version: %X pos %X\n", temp, buildVerPos);
+        fseek( pMainImage,  buildVerPos, SEEK_SET );
+        temp = htonl(PGPE_BUILD_VER);
+        fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+
+        if (imageType == PPMR_IMAGE)
+        {
+            //SGPE HCODE offset in PPMR header
+            uint32_t l_hcode_offset_pos = offsetof(PpmrHeader_t, g_ppmr_hcode_offset);
+            fseek ( pMainImage , l_hcode_offset_pos, SEEK_SET );
+            temp =  sizeof(PpmrHeader_t) +
+                    PGPE_LVL_1_BOOT_LOAD_SIZE +
+                    PGPE_LVL_2_BOOT_LOAD_SIZE;
+            printf("                    PPMR Hcode offset: 0x%X\n", temp);
+            temp = htonl(temp);
+            fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+
+            //SGPE Hcode length in PPMR header
+            uint32_t l_hcode_length_pos = offsetof(PpmrHeader_t, g_ppmr_hcode_length);
+            fseek ( pMainImage , l_hcode_length_pos, SEEK_SET );
+            temp = l_ppmr_pgpe_hcode_len_val;
+            printf("                    PPMR Hcode size:   0x%X (%d)\n", temp, temp);
+            temp = htonl(temp);
+            fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+        }
+
+        fclose(pMainImage);
+
+    }
+    while(0);
+
+    return 0;
+}
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ppmr.S b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ppmr.S
new file mode 100644
index 00000000..66749534
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ppmr.S
@@ -0,0 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ppmr.S $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#include <p9_hcode_image_defines.H>
+.ppmr_header
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
index 55f934d4..fd5d46c9 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
@@ -37,9 +37,9 @@
 // --------------------
 #define EPM_P9_TUNING 1
 #define SIMICS_TUNING 0
-#define GEN_PSTATE_TBL 0
+#define GEN_PSTATE_TBL 1
 #define USE_BOOT_TEMP 0
-#define BOOT_TEMP_SET_FULL_OCC_IPC_FUNC 1
+#define BOOT_TEMP_SET_FULL_OCC_IPC_FUNC 0
 #define DEV_DEBUG     1
 #define PK_TRACE_TIMER_OUTPUT 0
 #define SGPE_IPC_ENABLED 0
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
index 0b0671ce..4af98d07 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
@@ -80,7 +80,7 @@ $(IMAGE)_TRACE_HASH_PREFIX := $(shell echo $(IMAGE) | md5sum | cut -c1-4 \
 	| xargs -i printf "%d" 0x{})
 
 # Options for PK_TRACE
-$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=1
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=3
 $(IMAGE)_COMMONFLAGS+= -DPK_TRACE_TIMER_OUTPUT=0
 
 
@@ -113,3 +113,31 @@ $(call ADD_PPEIMAGE_INCDIR,$(IMAGE),\
 $(IMAGE)_LDFLAGS=-e __system_reset -N -gc-sections -Bstatic
 
 $(call BUILD_PPEIMAGE)
+
+# PPMR header edit:
+IMAGE=ppmr_header
+
+# Target tool chain
+$(IMAGE)_TARGET=PPE
+
+#linkscript to use
+$(IMAGE)_LINK_SCRIPT=linkppmr.cmd
+
+OBJS = p9_pgpe_ppmr.o
+
+$(call ADD_BINHEADER_INCDIR,$(IMAGE),\
+	$(PK_SRCDIR)/kernel \
+	$(PK_SRCDIR)/ppe42 \
+	$(PK_SRCDIR)/trace \
+	$(PK_SRCDIR)/$(_PPE_TYPE) \
+	$(PM_LIBDIR)/include \
+	$(PM_LIBDIR)/include/registers \
+	$(PM_LIBDIR)/common \
+	$(PM_LIBDIR)/occlib \
+	$(HCODE_LIBDIR) \
+	$(HCODE_COMMON_LIBDIR) \
+	$(HCODE_UTILS_INCDIR) \
+        $(ROOTPATH)/chips/p9/procedures/hwp/lib/ \
+	)
+
+$(call BUILD_BINHEADER,$(IMAGEPATH)/pstate_gpe/pstate_gpe.bin)
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/topfiles.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/topfiles.mk
index a21c605e..21a48576 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/topfiles.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/topfiles.mk
@@ -37,6 +37,7 @@ TOP-C-SOURCES = p9_pgpe_pstate.c \
 				p9_pgpe_ipc_handlers.c \
 				p9_pgpe_irq_handlers.c 
 
-TOP-S-SOURCES =
+TOP-S-SOURCES = p9_pgpe_image_header.S \
+                p9_pgpe_ppmr.S
 
 TOP_OBJECTS = $(TOP-C-SOURCES:.c=.o) $(TOP-S-SOURCES:.S=.o)
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
index 6eac41ca..c710920e 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
@@ -208,16 +208,14 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
                 l_blockCopyLength = pCpmrHdrAddr->cmeImgLength;         // CME Image length
             }
 
-            if (  pCpmrHdrAddr->cmeCommonRingLength != 0 )
+            if (  pCpmrHdrAddr->cmePstateLength != 0 )
             {
-                l_blockCopyLength = (pCpmrHdrAddr->cmeCommonRingOffset - (pCpmrHdrAddr->cmeImgOffset * 32)) +
-                                    pCpmrHdrAddr->cmeCommonRingLength;     // adding common ring length
+                l_blockCopyLength += pCpmrHdrAddr->cmePstateLength; // Local P-State parameter block
             }
 
-            if (  pCpmrHdrAddr->cmePstateLength != 0 )
+            if (  pCpmrHdrAddr->cmeCommonRingLength != 0 )
             {
-                l_blockCopyLength = (pCpmrHdrAddr->cmePstateOffset - (pCpmrHdrAddr->cmeImgOffset * 32)) +
-                                    pCpmrHdrAddr->cmePstateLength;         // adding Pstate region length
+                l_blockCopyLength += pCpmrHdrAddr->cmeCommonRingLength; // Common Ring Length
             }
 
             PK_TRACE("Block Copy Length: 0x%08x", l_blockCopyLength);
diff --git a/import/chips/p9/xip/p9_xip_image.h b/import/chips/p9/xip/p9_xip_image.h
index ee4a266e..4a230f45 100644
--- a/import/chips/p9/xip/p9_xip_image.h
+++ b/import/chips/p9/xip/p9_xip_image.h
@@ -1083,7 +1083,7 @@ p9_xip_find(void* i_image,
 ///
 /// \retval non-0 See \ref p9_xip_image_errors
 int
-p9_xip_delete_section(void* io_image, 
+p9_xip_delete_section(void* io_image,
                       void* o_imageBuf,
                       const uint32_t i_imageBufSize,
                       const int i_sectionId);
@@ -1893,14 +1893,16 @@ typedef enum
 
 typedef enum
 {
-    P9_XIP_SECTION_PGPE_LVL1_BL  = P9_XIP_SECTIONS_PLUS(0),
-    P9_XIP_SECTION_PGPE_LVL2_BL  = P9_XIP_SECTIONS_PLUS(1),
-    P9_XIP_SECTION_PGPE_HCODE    = P9_XIP_SECTIONS_PLUS(2),
-    P9_XIP_SECTIONS_PGPE         = P9_XIP_SECTIONS_PLUS(3) // # sections
+    P9_XIP_SECTION_PGPE_PPMR     = P9_XIP_SECTIONS_PLUS(0),
+    P9_XIP_SECTION_PGPE_LVL1_BL  = P9_XIP_SECTIONS_PLUS(1),
+    P9_XIP_SECTION_PGPE_LVL2_BL  = P9_XIP_SECTIONS_PLUS(2),
+    P9_XIP_SECTION_PGPE_HCODE    = P9_XIP_SECTIONS_PLUS(3),
+    P9_XIP_SECTIONS_PGPE         = P9_XIP_SECTIONS_PLUS(4) // # sections
 } p9_xip_section_pgpe_t;
 
 #define P9_XIP_SECTION_NAMES_PGPE(var)         \
     P9_XIP_SECTION_NAMES(var,                  \
+                         ".ppmr_header",       \
                          ".lvl1_bl",           \
                          ".lvl2_bl",           \
                          ".hcode")
diff --git a/import/tools/imageProcs/pstate_gpe_image.cmd b/import/tools/imageProcs/pstate_gpe_image.cmd
index bd5d0c33..2754905a 100644
--- a/import/tools/imageProcs/pstate_gpe_image.cmd
+++ b/import/tools/imageProcs/pstate_gpe_image.cmd
@@ -59,6 +59,14 @@ SECTIONS
     _strings_offset = . - _pgpe_image_origin;
     .strings . : { *(.strings) }
     _strings_size = . - _strings_origin;
+    ////////////////////////////////
+    // PPMR Header
+    ////////////////////////////////
+    . = ALIGN(8);
+    _ppmr_hdr_origin = .;
+    _ppmr_hdr_offset = . - _pgpe_image_origin;
+    .ppmr_header . : { *(.ppmr_header) }
+    _ppmr_hdr_size = . - _ppmr_hdr_origin;
 
     ////////////////////////////////
     // Level 1 Bootloader
diff --git a/import/tools/imageProcs/pstate_gpe_image.mk b/import/tools/imageProcs/pstate_gpe_image.mk
index 8406600b..063a003b 100644
--- a/import/tools/imageProcs/pstate_gpe_image.mk
+++ b/import/tools/imageProcs/pstate_gpe_image.mk
@@ -28,11 +28,14 @@ IMAGE=pstate_gpe_image
 PGPE_DEPS=$$($(IMAGE)_PATH)/.$(IMAGE).setbuild_host
 
 # dependencies for bin files needed in the pgpe xip image
+PPMR_HDR_BIN_FILE=$(IMAGEPATH)/ppmr_header/ppmr_header.bin
 LVL1_BL_BIN_FILE=$(IMAGEPATH)/pgpe_lvl1_copier/pgpe_lvl1_copier.bin
 LVL2_BL_BIN_FILE=$(IMAGEPATH)/pgpe_lvl2_loader/pgpe_lvl2_loader.bin
 PGPE_BIN_FILE=$(IMAGEPATH)/pstate_gpe/pstate_gpe.bin
 
-$(call XIP_TOOL,append,.lvl1_bl,$(PGPE_DEPS) $(LVL1_BL_BIN_FILE), $(LVL1_BL_BIN_FILE))
+$(call XIP_TOOL,append,.ppmr_header,$(PGPE_DEPS) $(PPMR_HDR_BIN_FILE), $(PPMR_HDR_BIN_FILE))
+$(call XIP_TOOL,append,.lvl1_bl,$(PGPE_DEPS) $$($(IMAGE)_PATH)/.$(IMAGE).append.ppmr_header \
+    $(LVL1_BL_BIN_FILE), $(LVL1_BL_BIN_FILE))
 $(call XIP_TOOL,append,.lvl2_bl,$(PGPE_DEPS) $$($(IMAGE)_PATH)/.$(IMAGE).append.lvl1_bl \
    	$(LVL2_BL_BIN_FILE), $(LVL2_BL_BIN_FILE))
 $(call XIP_TOOL,append,.hcode,$(PGPE_DEPS) $$($(IMAGE)_PATH)/.$(IMAGE).append.lvl2_bl \