Secure memory allocation and setup

p9_mss_eff_grouping.C:
  - determines whether secure mem is requested, reserves smf space
  - always reserve smf at end of range because of end-of-range bit
  - set addr15 when reporting smf base address
  - mask off group_id(0) via chip address extension if smf is enabled
  - updated to set value of attr_smf_enabled
  - enhanced error reporting with smf config/supported values
  - made values reported to attr_mss_mcs_group_32 more clear

p9_mss_setup_bars.C:
  - set MCFGPA/MCFGPMA registers with SMF data
  - fixed scom registers for MCFGPA/MCFGPMA hole setup
  - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711
  - added assert to check for HOLE1 and SMF enable overlaps

p9_query_mssinfo.C:
  - updated to print out SMF reservations
  - print out HTM/OCC/SMF reservations regardless of mirroring enable

p9_fbc_utils.C:
  - prevent group_id(0)=1 from affecting mappable memory ranges

p9_sbe_fabricinit.C:
  - mask off group_id(0) via chip address extension if smf is enabled

p9_setup_sbe_config.C, p9_sbe_attr_setup.C:
  - use scratch_reg6 bit(16) to pass smf_config value

initfiles:
  - removed setup to use other addr bits as secure bit; core only uses addr15
  - added setup for ncu addr15 value in hcode
  - always set addr15 config bit in bridge unit if smf is supported
  - set addr15 bit across all mcs if smf is enabled
  - added in settings to enable smf in nmmu unit
  - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported

attributes:
  - ATTR_SMF_ENABLE is a system level attribute
  - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported)

CQ:HW451708
CQ:HW451711
Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

2 files changed, 14 insertions, 1 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index bbde4de6..047e376f 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -237,6 +237,7 @@ HCD_CONST(SGPE_ENABLE_MEM_EARLY_DATA_SCOM_POS,    0x00008000)
 HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS,        0x00004000)
 HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS,     0x00002000)
 HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS,       0x00001000)
+HCD_CONST(SGPE_PROC_SMF_CONFIG_BIT_POS,           0x00000800)
 
 ///24x7
 HCD_CONST(QPMR_AUX_OFFSET,                     (512 * ONE_KB))
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
index f6c09e1e..0580293d 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
@@ -32,6 +32,7 @@ void
 p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
 {
     uint32_t      attr_proc_fabric_pump_mode_chip_is_node = 0; // default chip_is_group
+    uint32_t      attr_proc_smf_config_enabled            = 0;
     uint32_t      ex_loop                                 = 0;
     uint32_t      ex_count                                = 0;
     uint32_t      ex_mask                                 = 0;
@@ -46,6 +47,11 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
         attr_proc_fabric_pump_mode_chip_is_node = 1;
     }
 
+    if (pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_PROC_SMF_CONFIG_BIT_POS)
+    {
+        attr_proc_smf_config_enabled = 1;
+    }
+
     // Note: Epsilon settings are done via image build and scom restore(scomcust), not here
 
     if (!is_stop8) // Quad overall + L3/NCU(except L2) settings goes here
@@ -225,6 +231,7 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
                 // EXP.NC.NCMISC.NCSCOMS.TLBIE_STALL_CMPLT_CNT
                 // EXP.NC.NCMISC.NCSCOMS.TLBIE_STALL_DELAY_CNT
                 // EXP.NC.NCMISC.NCSCOMS.TLBIE_PACING_MST_DLY_EN
+                // EXP.NC.NCMISC.NCSCOMS.SMF_CONFIG
 
                 GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG3, quad, ex_index),
                             scom_data.value);
@@ -237,10 +244,15 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
 #endif
 
 #if NIMBUS_DD_LEVEL != 10
-
                 scom_data.words.upper |= BIT32(16);
+#endif
 
+                if (attr_proc_smf_config_enabled)
+                {
+#if NIMBUS_DD_LEVEL != 10 && NIMBUS_DD_LEVEL != 20 && NIMBUS_DD_LEVEL != 21 && CUMULUS_DD_LEVEL != 10 && CUMULUS_DD_LEVEL != 11
+                    scom_data.words.upper |= BIT32(20);
 #endif
+                }
 
                 GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG3, quad, ex_index),
                             scom_data.value);