STOP: update deskew procedure

HW-Image-Coreq: yes
Change-Id: Ie50b4fe582d16ec0e145a5222122ed4d99a07812
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43299
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

3 files changed, 133 insertions, 80 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index 7fd95c86..dfd1ca5b 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -226,9 +226,11 @@ HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS,             0x40000000)
 HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS,             0x20000000)
 HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS,            0x10000000)
 HCD_CONST(SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS,  0x08000000)
-HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS,   0x04000000)
 HCD_CONST(SGPE_VDM_ENABLE_BIT_POS,              0x04000000)
+HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS,   0x02000000)
 HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS,      0x00004000)
+HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS,   0x00002000)
+HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS,     0x00001000)
 
 ///24x7
 HCD_CONST(QPMR_AUX_OFFSET,                     (512 * ONE_KB))
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C
index 8e5d9485..8a51798c 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C
@@ -45,96 +45,147 @@
 
 extern "C" void p9_hcd_cache_dcc_skewadjust_setup(uint32_t quad)
 {
+    FAPI_DBG(">>p9_hcd_cache_dcc_skewadjust_setup");
+
     fapi2::Target<fapi2::TARGET_TYPE_EQ>        l_eqTarget
     (
         fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET)
     );
 
-    FAPI_DBG(">>p9_hcd_cache_dcc_skewadjust_setup");
-
-    PK_TRACE("Release skew adjust reset via NET_CTRL0[2]");
-    GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(2));
+    sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR);
 
-    FAPI_DBG("Release L2-0, L2-1 DC Adjust reset");
-    GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BITS64(23, 2));
+    if (!(pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_CACHE_DCADJ_DISABLE_BIT_POS))
+    {
+        FAPI_DBG("Release L2-0, L2-1 DC Adjust reset");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BITS64(23, 2));
 
-    ocb_ccsr_t ccsr;
+        ocb_ccsr_t ccsr;
 
-    do
-    {
-        ccsr.value = in32(OCB_CCSR);
-    }
-    while (ccsr.fields.change_in_progress);
+        do
+        {
+            ccsr.value = in32(OCB_CCSR);
+        }
+        while (ccsr.fields.change_in_progress);
 
-    for(int core = 0; core < CORES_PER_QUAD; core++)
-    {
-        if (ccsr.value & BIT32(((quad << 2) + core)))
+        for(int core = 0; core < CORES_PER_QUAD; core++)
         {
-            FAPI_DBG("Release CORE DC Adjust reset");
-            GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0_WAND, ((quad << 2) + core)), ~BIT64(2));
+            if (ccsr.value & BIT32(((quad << 2) + core)))
+            {
+                FAPI_DBG("Release CORE DC Adjust reset");
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0_WAND, ((quad << 2) + core)), ~BIT64(2));
+            }
         }
+
+        FAPI_DBG("Scan eq_ana_bndy_bucket_0 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_0, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_1 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_2 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_2, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_3 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_3, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_4 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_4, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_5 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_5, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_6 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_6, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_7 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_7, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_8 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_8, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_9 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_9, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_10 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_10, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_11 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_11, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_12 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_12, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_13 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_13, fapi2::RING_MODE_SET_PULSE_NSL));
+
+        FAPI_DBG("Release DCC bypass");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BIT64(1));
+
+        FAPI_DBG("Scan eq_ana_bndy_bucket_14 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_14, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_15 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_15, fapi2::RING_MODE_SET_PULSE_NSL));
     }
 
-    FAPI_DBG("Scan eq_ana_bndy_bucket_0 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_0, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_1 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_2 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_2, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_3 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_3, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_4 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_4, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_5 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_5, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_6 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_6, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_7 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_7, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_8 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_8, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_9 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_9, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_10 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_10, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_11 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_11, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_12 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_12, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_13 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_13, fapi2::RING_MODE_SET_PULSE_NSL));
-
-    FAPI_DBG("Release DCC bypass");
-    GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BIT64(1));
-
-    FAPI_DBG("Scan eq_ana_bndy_bucket_14 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_14, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_15 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_15, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_16 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_16, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_17 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_17, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_18 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_18, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_19 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_19, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_20 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_20, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_21 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_21, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_22 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_22, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_23 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_23, fapi2::RING_MODE_SET_PULSE_NSL));
-
-    FAPI_DBG("Release Progdly bypass");
-    GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BIT64(2));
-
-    FAPI_DBG("Scan eq_ana_bndy_bucket_24 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_24, fapi2::RING_MODE_SET_PULSE_NSL));
-    FAPI_DBG("Scan eq_ana_bndy_bucket_25 ring");
-    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_25, fapi2::RING_MODE_SET_PULSE_NSL));
+    if (!(pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS))
+    {
+        PK_TRACE("Release skew adjust reset via NET_CTRL0[2]");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(2));
+
+        FAPI_DBG("Scan eq_ana_bndy_bucket_16 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_16, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_17 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_17, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_18 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_18, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_19 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_19, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_20 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_20, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_21 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_21, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_22 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_22, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_23 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_23, fapi2::RING_MODE_SET_PULSE_NSL));
+
+#if NIMBUS_DD_LEVEL == 10
+
+        FAPI_DBG("Release Progdly bypass");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BIT64(2));
+
+#endif
+
+        FAPI_DBG("Scan eq_ana_bndy_bucket_24 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_24, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_25 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_25, fapi2::RING_MODE_SET_PULSE_NSL));
+
+#if NIMBUS_DD_LEVEL != 10
+
+        FAPI_DBG("Scan eq_ana_bndy_bucket_26 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_26, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_27 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_27, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_28 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_28, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_29 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_29, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_30 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_30, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_31 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_31, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_32 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_32, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_33 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_33, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_34 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_34, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_35 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_35, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_36 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_36, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_37 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_37, fapi2::RING_MODE_SET_PULSE_NSL));
+
+        FAPI_DBG("Release Progdly bypass");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BIT64(2));
+
+        FAPI_DBG("Scan eq_ana_bndy_bucket_38 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_38, fapi2::RING_MODE_SET_PULSE_NSL));
+        FAPI_DBG("Scan eq_ana_bndy_bucket_39 ring");
+        FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_39, fapi2::RING_MODE_SET_PULSE_NSL));
+
+#endif
+
+    }
 
 fapi_try_exit:
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_ringid_sgpe.H b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_ringid_sgpe.H
index a7fc6894..2ff2e543 100755
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_ringid_sgpe.H
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_ringid_sgpe.H
@@ -106,8 +106,8 @@ typedef enum
     eq_ana_bndy_bucket_34 = 55,
     eq_ana_bndy_bucket_35 = 56,
     eq_ana_bndy_bucket_36 = 57,
-    eq_ana_bndy_bucket_37 = 68,
-    eq_ana_bndy_bucket_38 = 69,
+    eq_ana_bndy_bucket_37 = 58,
+    eq_ana_bndy_bucket_38 = 59,
     eq_ana_bndy_bucket_39 = 60,
     eq_ana_bndy_bucket_40 = 61,
     eq_ana_bndy_bucket_41 = 62,