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| author | Yue Du <daviddu@us.ibm.com> | 2016-12-02 16:57:19 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:54:05 -0500 |
| commit | 6efde4e9efe502cbda758cc642aa25b6591c12b8 (patch) | |
| tree | d2efd07c203fc9e394fff6fbbb8507fb3eb8227b | |
| parent | d92c32ce5cc6e6b3eb7bf03935794bcc0d0dedd4 (diff) | |
| download | talos-hcode-6efde4e9efe502cbda758cc642aa25b6591c12b8.tar.gz talos-hcode-6efde4e9efe502cbda758cc642aa25b6591c12b8.zip | |
HW396520: DD1 workaround skip flushmode inhibit drop in cache hwp
Change-Id: I6575ec51a94024708611678bee7af0cf7819b206
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33362
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Dev-Ready: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c index a7c485f7..be504135 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c @@ -119,9 +119,10 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg) // ------------------------------- /// @todo Check the Global Checkstop FIR of dedicated EX chiplet - +#if NIMBUS_DD_LEVEL != 1 PK_TRACE("Clear flushmode_inhibit via CPLT_CTRL0[2]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_CLEAR, quad), BIT64(2)); +#endif PK_TRACE("Set parital bad l2/l3 and stopped l2 pscom mask"); scom_data = 0; |
