From 6efde4e9efe502cbda758cc642aa25b6591c12b8 Mon Sep 17 00:00:00 2001 From: Yue Du Date: Fri, 2 Dec 2016 16:57:19 -0600 Subject: HW396520: DD1 workaround skip flushmode inhibit drop in cache hwp Change-Id: I6575ec51a94024708611678bee7af0cf7819b206 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33362 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: AMIT KUMAR Reviewed-by: ADAM S. HALE Dev-Ready: ADAM S. HALE Reviewed-by: Jennifer A. Stofer --- .../procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c index a7c485f7..be504135 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c @@ -119,9 +119,10 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg) // ------------------------------- /// @todo Check the Global Checkstop FIR of dedicated EX chiplet - +#if NIMBUS_DD_LEVEL != 1 PK_TRACE("Clear flushmode_inhibit via CPLT_CTRL0[2]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_CLEAR, quad), BIT64(2)); +#endif PK_TRACE("Set parital bad l2/l3 and stopped l2 pscom mask"); scom_data = 0; -- cgit v1.2.3