Merge pull request #18 from alvintpwang/P8NVLink

P8NVLink support

2 files changed, 124 insertions, 4 deletions

diff --git a/xml/target_instances_v3.xml b/xml/target_instances_v3.xml
index d1e4731..b7d1081 100644
--- a/xml/target_instances_v3.xml
+++ b/xml/target_instances_v3.xml
@@ -905,7 +905,7 @@
 		<child_id>p8p_ex-14</child_id>
 		<child_id>p8p_pore-0</child_id>
 		<child_id>p8p_capp-0</child_id>
-                <child_id>p8p_capp-1</child_id>
+		<child_id>p8p_capp-1</child_id>
 		<child_id>p8p_nx-0</child_id>
 		<child_id>p8p_occ-0</child_id>
 		<child_id>p8p_pci_configs</child_id>
@@ -1081,6 +1081,17 @@
 		</attribute>
 	</targetInstance>
 
+	<targetInstance>
+		<type>occ</type>
+		<id>p8p_occ-0</id>
+		<hidden_child_id>occ_active_sensor</hidden_child_id>
+		<attribute>
+			<id>CHIP_UNIT</id>
+			<default>0</default>
+		</attribute>
+	</targetInstance>
+
+
 	<!-- PCIe instances -->
 	<targetInstance>
 		<type>unit-pciconfigs-naples</type>
diff --git a/xml/target_types_mrw.xml b/xml/target_types_mrw.xml
index 0860a22..ad8eced 100644
--- a/xml/target_types_mrw.xml
+++ b/xml/target_types_mrw.xml
@@ -745,9 +745,106 @@
 		</attribute>
 	</targetType>
 	<targetType>
+		<id>socket-proc_socket_dellovo-50mm</id>
+		<parent>connector</parent>
+		<parent_type>card-motherboard</parent_type>
+		<parent_type>card-daughtercard</parent_type>
+		<attribute>
+			<id>TYPE</id>
+			<default>NA</default>
+		</attribute>
+		<attribute>
+			<id>FABRIC_NODE_ID</id>
+			<default>0</default>
+		</attribute>
+		<attribute>
+			<id>FABRIC_CHIP_ID</id>
+			<default>0</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id>
+			<default>0x000018F4,0x000018F4,0x000018F4
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id>
+			<default>0x0000086C,0x0000086C,0x0000086C
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_PCS_CONTROL0</id>
+			<default>0x00003AE8,0x00003AE8,0x00003AE8
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_PCS_CONTROL1</id>
+			<default>0x00005CB9,0x00005CB9,0x00005CB9
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id>
+			<default>0x00000146,0x00000146,0x00000146
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id>
+			<default>0x000006D7,0x000006D7,0x000006D7
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_RX_PEAK</id>
+			<default>0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8,0x00000FF8
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_RX_SDL</id>
+			<default>0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A,0x0000294A
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id>
+			<default>0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451,0x00009451
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_TX_BWLOSS1</id>
+			<default>0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id>
+			<default>0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294,0x00004294
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id>
+			<default>0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151,0x00002151
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_TX_FFE_GEN1</id>
+			<default>0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0,0x000082C0
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_TX_FFE_GEN2</id>
+			<default>0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400,0x00008400
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_ZCAL_CONTROL</id>
+			<default>0x00000080,0x00000080,0x00000080
+			</default>
+		</attribute>
+		<attribute>
+			<id>PROC_PCIE_IOP_CONFIG</id>
+			<default>1</default>
+		</attribute>
+	</targetType>
+	<targetType>
 		<id>module-module-dellovo</id>
 		<parent>card</parent>
-		<parent_type>socket-proc_socket-50mm</parent_type>
+		<parent_type>socket-proc_socket_dellovo-50mm</parent_type>
 		<attribute>
 			<id>TYPE</id>
 			<default>NA</default>
@@ -1149,6 +1246,18 @@
 			</default>
 		</attribute>
 		<attribute>
+			<id>NPU_MMIO_BAR_ENABLE</id>
+			<default>0x01</default>
+		</attribute>
+		<attribute>
+			<id>NPU_MMIO_BAR_BASE_ADDR</id>
+			<default>8,0x0003FFF000000000,0x2000000,0x1000000,0x200000</default>
+		</attribute>
+		<attribute>
+			<id>NPU_MMIO_BAR_SIZE</id>
+			<default>0x200000</default>
+		</attribute>
+		<attribute>
 			<id>RNG_BASE_ADDR</id>
 			<default>1,0x0003FFFF40000000,0x4000,0x1000,0</default>
 		</attribute>
@@ -2463,7 +2572,7 @@
 		</attribute>
 		<attribute>
 			<id>WRITE_PAGE_SIZE</id>
-			<default>0x80</default>
+			<default>32</default>
 		</attribute>
 	</targetType>
 	<targetType>
@@ -2517,7 +2626,7 @@
 		</attribute>
 		<attribute>
 			<id>WRITE_PAGE_SIZE</id>
-			<default>0x50</default>
+			<default>0x08</default>
 		</attribute>
 	</targetType>