diff options
| author | nkskjames <nkskjames@gmail.com> | 2015-10-20 12:51:54 -0500 |
|---|---|---|
| committer | nkskjames <nkskjames@gmail.com> | 2015-10-20 12:51:54 -0500 |
| commit | 25a98575966b4e5ec2b8b85151ecabb73a676796 (patch) | |
| tree | 56f608276a3bb269672053f32b6995cd522dde1c | |
| parent | a7f9f3d0cdd8369de0dd710db820df6c1231f52a (diff) | |
| parent | 04f15f37e9ab6c09412a0abcffb87e9aefcc5368 (diff) | |
| download | serverwiz-25a98575966b4e5ec2b8b85151ecabb73a676796.tar.gz serverwiz-25a98575966b4e5ec2b8b85151ecabb73a676796.zip | |
Merge pull request #13 from rjknight/master
Update Targets.pm and target_types_mrw.xml
| -rw-r--r-- | scripts/Targets.pm | 12 | ||||
| -rwxr-xr-x | scripts/processMrw.pl | 153 | ||||
| -rw-r--r-- | xml/attribute_types.xml | 1263 | ||||
| -rw-r--r-- | xml/attribute_types_hb.xml | 608 | ||||
| -rw-r--r-- | xml/target_types_mrw.xml | 29 |
5 files changed, 1506 insertions, 559 deletions
diff --git a/scripts/Targets.pm b/scripts/Targets.pm index 8cf9bc4..dffb5fa 100644 --- a/scripts/Targets.pm +++ b/scripts/Targets.pm @@ -55,7 +55,7 @@ sub new '4' => '7', '5' => '6' } - # TODO RTC: TBD + # TODO RTC:132549 # DMI_FSI_MAP is a lookup table for DMI channel to FSI and ref clock. # It is processor specific and needs to be pulled from a # processor attribute instead of being hardcoded @@ -190,18 +190,14 @@ sub printAttribute $filter{MODEL} = 1; $filter{TYPE} = 1; $filter{CDM_POLICIES} = 1; - $filter{ALL_MCS_IN_INTERLEAVING_GROUP} = 1; - $filter{MSS_INTERLEAVE_ENABLE} = 1; $filter{CDM_POLICIES_BITMASK} = 1; $filter{ENTITY_ID_LOOKUP} = 1; $filter{ENTITY_INSTANCE} = 1; $filter{MBA_NUM} = 1; - $filter{IPMI_INSTANCE} = 1; - $filter{FRU_NAME} = 1; + $filter{IPMI_NAME} = 1; $filter{INSTANCE_ID} = 1; - #$filter{ADC_CHANNEL_SENSOR_NUMBERS} = 1; $filter{IO_CONFIG_SELECT} = 1; - #$filter{FRU_ID} = 1; + $filter{FRU_NAME} = 1; if ($filter{$attribute} == 1) { @@ -590,8 +586,6 @@ sub processMcs $parent_affinity . "/mcs-$mcs/membuf-$membufnum"); $self->setAttribute($membuf, "PHYS_PATH", $node_phys . "/membuf-$membufnum"); - # $self->setAttribute($membuf, "VPD_REC_NUM", - # $self->getAttribute($membuf, "POSITION")); ## copy DMI bus attributes to membuf $self->setAttribute($unit, "EI_BUS_TX_LANE_INVERT", diff --git a/scripts/processMrw.pl b/scripts/processMrw.pl index 7d7b50a..9276768 100755 --- a/scripts/processMrw.pl +++ b/scripts/processMrw.pl @@ -77,13 +77,18 @@ my $xmldir = dirname($serverwiz_file); $targetObj->loadXML($serverwiz_file); +my $str=sprintf( + " %30s | %10s | %6s | %4s | %9s | %4s | %4s | %4s | %10s | %s\n", + "Sensor Name","FRU Name","Ent ID","Type","Evt Type","ID","Inst","FRU", + "HUID","Target"); -my $str=sprintf(" %30s | %10s | %6s | %4s | %4s | %4s | %4s | %s\n", - "Sensor Name","FRU Name","Ent ID","Type","ID","Inst","FRU","Target"); $targetObj->writeReport($str); -$str=sprintf(" %30s | %10s | %6s | %4s | %4s | %4s | %4s | %s\n", - "------------------------------","----------", - "------","----","----","----","----","----------"); +my $str=sprintf( + " %30s | %10s | %6s | %4s | %9s | %4s | %4s | %4s | %10s | %s\n", + "------------------------------","----------", + "------","----","---------","----","----","----","----------", + "----------"); + $targetObj->writeReport($str); #-------------------------------------------------- ## loop through all targets and do stuff @@ -202,6 +207,11 @@ sub processIpmiSensors { { $fru_id=$targetObj->getAttribute($target,"FRU_ID"); } + my $huid=""; + if (!$targetObj->isBadAttribute($target,"HUID")) + { + $huid=$targetObj->getAttribute($target,"HUID"); + } my @sensors; foreach my $child (@{$targetObj->getTargetChildren($target)}) @@ -216,6 +226,9 @@ sub processIpmiSensors { getAttribute($child,"IPMI_SENSOR_NAME_SUFFIX"); my $sensor_id=$targetObj-> getAttribute($child,"IPMI_SENSOR_ID"); + my $sensor_evt=$targetObj-> + getAttribute($child,"IPMI_SENSOR_READING_TYPE"); + $name_suffix=~s/\n//g; $name_suffix=~s/\s+//g; @@ -229,15 +242,17 @@ sub processIpmiSensors { my $s=sprintf("0x%02X%02X,0x%02X", oct($sensor_type),oct($entity_id),oct($sensor_id)); push(@sensors,$s); - my $sensor_id_str = "Err"; + my $sensor_id_str = ""; if ($sensor_id ne "") { $sensor_id_str = sprintf("0x%02X",oct($sensor_id)); } my $str=sprintf( - " %30s | %10s | 0x%02X | 0x%02X | %4s | %4d | %4d | %s\n", - $sensor_name,$name,oct($entity_id),oct($sensor_type), - $sensor_id_str,$instance,$fru_id,$target); + " %30s | %10s | 0x%02X | 0x%02X | 0x%02x |" . + " %4s | %4d | %4d | %10s | %s\n", + $sensor_name,$name,oct($entity_id),oct($sensor_type), + oct($sensor_evt), $sensor_id_str,$instance,$fru_id, + $huid,$target); $targetObj->writeReport($str); } } @@ -273,6 +288,8 @@ sub processApss { getAttribute($child,"IPMI_SENSOR_NAME_SUFFIX"); my $sensor_id=$targetObj-> getAttribute($child,"IPMI_SENSOR_ID"); + my $sensor_evt=$targetObj-> + getAttribute($child,"IPMI_SENSOR_READING_TYPE"); my $channel = $targetObj-> getAttribute($child,"ADC_CHANNEL_ASSIGNMENT"); my $channel_id = $targetObj-> @@ -288,7 +305,7 @@ sub processApss { $name=~s/\s+//g; $name=~s/\t+//g; - my $sensor_id_str = "Err"; + my $sensor_id_str = ""; if ($sensor_id ne "") { $sensor_id_str = sprintf("0x%02X",oct($sensor_id)); @@ -301,14 +318,13 @@ sub processApss { $channel_offsets[$channel] = $channel_offset; $channel_gains[$channel] = $channel_gain; } - else - { - $sensor_id_str="N/A"; - } my $str=sprintf( - " %30s | %10s | 0x%02X | 0x%02X | %4s | %4d | %4d | %s\n", + " %30s | %10s | 0x%02X | 0x%02X | 0x%02x |" . + " %4s | %4d | %4d | %10s | %s\n", $name,"",oct($entity_id),oct($sensor_type), - $sensor_id_str,$channel,"",$systemTarget); + oct($sensor_evt),$sensor_id_str,$channel,"","", + $systemTarget); + $targetObj->writeReport($str); } } @@ -422,7 +438,6 @@ sub processProcessor my $target = shift; ######################### - ## Copy PCIE attributes from socket ## In serverwiz, processor instances are not unique ## because plugged into socket ## so processor instance unique attributes are socket level. @@ -431,6 +446,12 @@ sub processProcessor $targetObj->getTargetParent($targetObj->getTargetParent($target)); $targetObj->copyAttribute($socket_target,$target,"LOCATION_CODE"); + ## Module attibutes are inherited into the proc target + my $module_target = + $targetObj->getTargetParent($target); + $targetObj->copyAttribute($module_target,$target,"LOCATION_CODE"); + + ## Copy PCIE attributes from socket foreach my $attr (sort (keys %{ $targetObj->getTarget($socket_target)->{TARGET}->{attribute} })) { @@ -439,6 +460,14 @@ sub processProcessor $targetObj->copyAttribute($socket_target,$target,$attr); } } + + ## Copy all attributes from module + foreach my $attr (sort (keys + %{ $targetObj->getTarget($module_target)->{TARGET}->{attribute} })) + { + $targetObj->copyAttribute($module_target,$target,$attr); + } + $targetObj->log($target, "Processing PROC"); foreach my $child (@{ $targetObj->getTargetChildren($target) }) { @@ -508,7 +537,7 @@ sub processProcessor else { $targetObj->setAttribute($target, "PROC_MASTER_TYPE", - "MASTER_CANDIDATE"); + "NOT_MASTER"); } ## Update bus speeds processI2cSpeeds($targetObj,$target); @@ -588,6 +617,11 @@ sub setupBars "INTP_BASE_ADDR","PHB_BASE_ADDRS","PCI_BASE_ADDRS_32", "PCI_BASE_ADDRS_64","RNG_BASE_ADDR","IBSCOM_PROC_BASE_ADDR"); + # Attribute only valid in naples-based systems + if (!$targetObj->isBadAttribute($target,"NPU_MMIO_BAR_BASE_ADDR") ) { + push(@bars,"NPU_MMIO_BAR_BASE_ADDR"); + } + foreach my $bar (@bars) { my ($num,$base,$node_offset,$proc_offset,$offset) = split(/,/, @@ -606,8 +640,10 @@ sub setupBars { for (my $i=0;$i<$num;$i++) { + #Note: Hex convert method avoids overflow on 32bit machine my $b=sprintf("0x%016s",substr(( - $i_base+$i_node_offset*$node+$i_proc_offset*$proc+$i_offset*$i)->as_hex(),2)); #Note: Hex convert method avoids overflow on 32bit machines. + $i_base+$i_node_offset*$node+ + $i_proc_offset*$proc+$i_offset*$i)->as_hex(),2)); my $sep=","; if ($i==$num-1) { @@ -640,8 +676,10 @@ sub processMcs my $i_offset = Math::BigInt->new($offset); my $mcs = $targetObj->getAttribute($target, "MCS_NUM"); + #Note: Hex convert method avoids overflow on 32bit machines my $mcsStr=sprintf("0x%016s",substr(( - $i_base+$i_node_offset*$node+$i_proc_offset*$proc+$i_offset*$mcs)->as_hex(),2)); #Note: Hex convert method avoids overflow on 32bit machines. + $i_base+$i_node_offset*$node+ + $i_proc_offset*$proc+$i_offset*$mcs)->as_hex(),2)); $targetObj->setAttribute($target, "IBSCOM_MCS_BASE_ADDR", $mcsStr); } @@ -657,23 +695,23 @@ sub processXbus my $target = shift; my $found_xbus = 0; - + my $xbus_child_conn = $targetObj->getFirstConnectionDestination($target); if ($xbus_child_conn ne "") { - ## set attributes for both directions + ## set attributes for both directions $targetObj->setAttribute($xbus_child_conn, "PEER_TARGET", - $targetObj->getAttribute($target, "PHYS_PATH")); + $targetObj->getAttribute($target, "PHYS_PATH")); $targetObj->setAttribute($target, "PEER_TARGET", - $targetObj->getAttribute($xbus_child_conn, "PHYS_PATH")); + $targetObj->getAttribute($xbus_child_conn, "PHYS_PATH")); $targetObj->setAttribute($xbus_child_conn, "PEER_TARGET", - $targetObj->getAttribute($target, "PHYS_PATH")); + $targetObj->getAttribute($target, "PHYS_PATH")); $targetObj->setAttribute($target, "PEER_TARGET", - $targetObj->getAttribute($xbus_child_conn, "PHYS_PATH")); + $targetObj->getAttribute($xbus_child_conn, "PHYS_PATH")); $found_xbus = 1; - } + } } @@ -697,8 +735,6 @@ sub processAbus { $targetObj->setAttribute($target, "EI_BUS_TX_MSBSWAP","0"); } - # $targetObj->setAttribute($target, "PEER_TARGET",""); - my $abus_child_conn = $targetObj->getFirstConnectionDestination($target); if ($abus_child_conn ne "") { @@ -828,23 +864,23 @@ sub processPcie $iop_swap{0}{1}{'11'}=$t[7]; $iop_swap{1}{0}{'00'}=$t[8]; - $iop_swap{1}{0}{'01'}=$t[9]; - $iop_swap{1}{0}{'10'}=$t[10]; + $iop_swap{1}{0}{'10'}=$t[9]; + $iop_swap{1}{0}{'01'}=$t[10]; $iop_swap{1}{0}{'11'}=$t[11]; $iop_swap{1}{1}{'00'}=$t[12]; $iop_swap{1}{1}{'10'}=$t[13]; $iop_swap{1}{1}{'01'}=$t[14]; $iop_swap{1}{1}{'11'}=$t[15]; - $iop_swap{2}{0}{'00'}=$t[8]; - $iop_swap{2}{0}{'01'}=$t[9]; - $iop_swap{2}{0}{'10'}=$t[10]; - $iop_swap{2}{0}{'11'}=$t[11]; - $iop_swap{2}{1}{'00'}=$t[12]; - $iop_swap{2}{1}{'10'}=$t[13]; - $iop_swap{2}{1}{'01'}=$t[14]; - $iop_swap{2}{1}{'11'}=$t[15]; + $iop_swap{2}{0}{'00'}=$t[16]; + $iop_swap{2}{0}{'01'}=$t[17]; + $iop_swap{2}{0}{'10'}=$t[18]; + $iop_swap{2}{0}{'11'}=$t[19]; + $iop_swap{2}{1}{'00'}=$t[20]; + $iop_swap{2}{1}{'10'}=$t[21]; + $iop_swap{2}{1}{'01'}=$t[22]; + $iop_swap{2}{1}{'11'}=$t[23]; my @lane_eq; my $NUM_PHBS=4; @@ -940,30 +976,33 @@ sub processPcie die "PCIE config for $iop,$iop_lane_swap[$iop],$lane_rev not found\n"; } } - my $lane_swap_attr0 = sprintf("%s,%s,%s",$iop_lane_swap[0], - $iop_lane_swap[1],$iop_lane_swap[2]); - my $lane_swap_attr1 = sprintf("%s,0,%s,0,%s,0",$iop_lane_swap[0], - $iop_lane_swap[1],$iop_lane_swap[2]); + + my $lane_rev_attr0 = sprintf("%s,%s,%s", + oct($iop_swap_lu[0]), + oct($iop_swap_lu[1]), + oct($iop_swap_lu[2])); + my $lane_rev_attr1 = sprintf("%s,0,%s,0,%s,0", + oct($iop_swap_lu[0]), + oct($iop_swap_lu[1]), + oct($iop_swap_lu[2])); $targetObj->setAttribute($parentTarget, "PROC_PCIE_IOP_SWAP", - $lane_swap_attr0); + $lane_rev_attr0); $targetObj->setAttribute($parentTarget, "PROC_PCIE_IOP_SWAP_NON_BIFURCATED", - $lane_swap_attr1); + $lane_rev_attr1); $targetObj->setAttribute($parentTarget, "PROC_PCIE_IOP_SWAP_BIFURCATED", "0,0,0,0"); - - my $lane_rev_attr = sprintf("%s,0,%s,0,%s,0", - oct($iop_swap_lu[0]),oct($iop_swap_lu[1]),oct($iop_swap_lu[2])); - $targetObj->setAttribute($parentTarget, "PROC_PCIE_IOP_REVERSAL", - $lane_rev_attr); + "0,0,0,0"); $targetObj->setAttribute($parentTarget, - "PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED",$lane_rev_attr); + "PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED","0,0,0,0"); $targetObj->setAttribute($parentTarget, "PROC_PCIE_IOP_REVERSAL_BIFURCATED", "0,0,0,0"); - my $is_slot_attr = sprintf("%s,%s,%s,%s", - $is_slot[0][0], $is_slot[0][1], $is_slot[1][0], $is_slot[1][1], $is_slot[2][0], $is_slot[2][1]); + my $is_slot_attr = sprintf("%s,%s,%s,%s,%s,%s", + $is_slot[0][0], $is_slot[0][1], + $is_slot[1][0], $is_slot[1][1], + $is_slot[2][0], $is_slot[2][1]); $targetObj->setAttribute($parentTarget, "PROC_PCIE_IS_SLOT", $is_slot_attr); ## don't support DSMP @@ -1012,7 +1051,6 @@ sub processMembufVpdAssociation my $membuf_target = $membuf_assoc->{DEST_PARENT}; setEepromAttributes($targetObj, "EEPROM_VPD_PRIMARY_INFO",$membuf_target,$vpd); - my $index = $targetObj->getBusAttribute($membuf_assoc->{SOURCE}, $membuf_assoc->{BUS_NUM}, "ISDIMM_MBVPD_INDEX"); $targetObj->setAttribute( @@ -1032,7 +1070,6 @@ sub processMembufVpdAssociation "EEPROM_VPD_PRIMARY_INFO",$node_target,$vpd); $targetObj->setAttribute($node_target, "VPD_REC_NUM",$targetObj->{vpd_num}); - print ">>> $node_target,$targetObj->{vpd_num}\n"; } } $targetObj->{vpd_num}++; @@ -1113,7 +1150,6 @@ sub processMembuf setEepromAttributes($targetObj, "EEPROM_VPD_PRIMARY_INFO",$dimm_target, $dimm); - my $field=getI2cMapField($targetObj,$dimm_target,$dimm); my $map = $dimm_portmap{$dimm_target}; if ($map eq "") { @@ -1123,7 +1159,7 @@ sub processMembuf $addr_map[$map] = $field; } } - $targetObj->setAttribute($targetObj->{targeting}->{SYS}[0]->{KEY}, + $targetObj->setAttribute($target, "MRW_MEM_SENSOR_CACHE_ADDR_MAP","0x".join("",@addr_map)); ## Update bus speeds @@ -1309,7 +1345,8 @@ sub errorCheck } else { - $abus_error = sprintf("proc not connected to proc via Abus or Xbus (Target=%s)",$child); + $abus_error = sprintf( +"proc not connected to proc via Abus or Xbus (Target=%s)",$child); } } } diff --git a/xml/attribute_types.xml b/xml/attribute_types.xml index 84f241d..f928f2c 100644 --- a/xml/attribute_types.xml +++ b/xml/attribute_types.xml @@ -301,225 +301,6 @@ </enumerator> <default>NO_MASTER</default> </enumerationType> - - - -<enumerationType> - <id>ENTITY_ID</id> - <description>Enumeration indicating the IPMI entity ID, these values are - defined in the IPMI specification. These values will be used in place - of target type when events are sent to the BMC.</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>OTHER</name> - <value>0x01</value> - </enumerator> - <enumerator> - <name>PROCESSOR</name> - <value>0x03</value> - </enumerator> - <enumerator> - <name>SYSTEM_BOARD</name> - <value>0x07</value> - </enumerator> - <enumerator> - <name>POWER_MGMT</name> - <value>0x15</value> - </enumerator> - <enumerator> - <name>CHASSIS</name> - <value>0x17</value> - </enumerator> - <enumerator> - <name>MEMORY_DEVICE</name> - <value>0x20</value> - </enumerator> - <enumerator> - <name>BIOS</name> - <value>0x22</value> - </enumerator> - <enumerator> - <name>OS</name> - <value>0x23</value> - </enumerator> - <enumerator> - <name>CORE</name> - <value>0xD0</value> - </enumerator> - <enumerator> - <name>CENTAUR</name> - <value>0xD1</value> - </enumerator> - <enumerator> - <name>OCC</name> - <value>0xD2</value> - </enumerator> - <enumerator> - <name>REF_CLOCK</name> - <value>0xD4</value> - </enumerator> - <enumerator> - <name>PCI_CLOCK</name> - <value>0xD5</value> - </enumerator> - <enumerator> - <name>TOD_CLOCK</name> - <value>0xD6</value> - </enumerator> - <enumerator> - <name>APSS</name> - <value>0xD7</value> - </enumerator> -</enumerationType> -<enumerationType> - <id>SENSOR_NAME</id> - <description>Enumeration indicating the IPMI sensor name, which will - be used by hostboot when determining the sensor number to return. - The name is unique per hostboot sensor type, actual IPMI sensor - types have been overloaded to map our needs. The sensor name consists - of one byte of sensor type plus one byte of sub-type, to differentiate - similar sensors under the same target</description> - <enumerator> - <name>TEMPERATURE</name> - <value>0x0100</value> - </enumerator> - <enumerator> - <name>VOLTAGE</name> - <value>0x0200</value> - </enumerator> - <enumerator> - <name>CURRENT</name> - <value>0x0300</value> - </enumerator> - <enumerator> - <name>INTRUSION</name> - <value>0x0400</value> - </enumerator> - <enumerator> - <name>STATE</name> - <value>0x0500</value> - </enumerator> - <enumerator> - <name>POWER_UNIT</name> - <value>0x0600</value> - </enumerator> - <enumerator> - <name>OS_BOOT</name> - <value>0x0700</value> - </enumerator> - <enumerator> - <name>HOST_STATUS</name> - <value>0x0800</value> - </enumerator> - <enumerator> - <name>FW_BOOT_PROGRESS</name> - <value>0x0900</value> - </enumerator> - <enumerator> - <name>OCC_ACTIVE</name> - <value>0x0A00</value> - </enumerator> - <enumerator> - <name>SYSTEM_POWER_CAP</name> - <value>0x0b00</value> - </enumerator> - <enumerator> - <name>PCI_ACTIVE</name> - <value>0x0c00</value> - </enumerator> - <enumerator> - <name>BOOT_WATCHDOG</name> - <value>0x0d00</value> - </enumerator> - <enumerator> - <name>REBOOT_COUNT</name> - <value>0x0e00</value> - </enumerator> - <enumerator> - <name>FAULT</name> - <value>0x1000</value> - </enumerator> - <enumerator> - <name>APSS_FAULT</name> <!-- APSS Fault --> - <value>0x1010</value> - </enumerator> - <enumerator> - <name>TOD_CLOCK_FAULT</name> - <value>0x1017</value> - </enumerator> - <enumerator> - <name>REF_CLOCK_FAULT</name> - <value>0x101A</value> - </enumerator> - <enumerator> - <name>PCI_CLOCK_FAULT</name> - <value>0x101B</value> - </enumerator> - <enumerator> - <name>APSS_CHANNEL</name> <!-- Power sensors --> - <value>0x1100</value> <!-- 16 channels --> - </enumerator> - -</enumerationType> - -<enumerationType> - <id>SENSOR_TYPE</id> - <description>Enumeration indicating the IPMI sensor type, these values - are defined in the IPMI specification. These values will be used when - sending sensor reading events to the BMC.</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>TEMPERATURE</name> - <value>0x01</value> - </enumerator> - <enumerator> - <name>VOLTAGE</name> - <value>0x02</value> - </enumerator> - <enumerator> - <name>CURRENT</name> - <value>0x03</value> - </enumerator> - <enumerator> - <name>PHYSICAL_SECURITY</name> - <value>0x05</value> - </enumerator> - <enumerator> - <name>PROCESSOR</name> - <value>0x07</value> - </enumerator> - <enumerator> - <name>MEMORY</name> - <value>0x0c</value> - </enumerator> - <enumerator> - <name>POWER_UNIT</name> - <value>0x09</value> - </enumerator> - <enumerator> - <name>OS_BOOT</name> - <value>0x1F</value> - </enumerator> - <enumerator> - <name>APCI_POWER_STATE</name> - <value>0x22</value> - </enumerator> - <enumerator> - <name>SYSTEM_FIRMWARE_PROGRESS</name> - <value>0x0F</value> - </enumerator> - <enumerator> - <name>REBOOT_COUNT</name> - <value>0xC0</value> - </enumerator> -</enumerationType> - <attribute> <id>CLASS</id> <description>Attribute indicating the target's class</description> @@ -531,7 +312,6 @@ <persistency>non-volatile</persistency> <readable/> <hasStringConversion/> - <serverwizHide/> </attribute> <attribute> @@ -544,7 +324,6 @@ </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> <hasStringConversion/> </attribute> @@ -558,7 +337,6 @@ </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> <hasStringConversion/> </attribute> @@ -574,42 +352,6 @@ <readable/> <hasStringConversion/> </attribute> - -<!-- IPMI Sensor numbers are defined in the IPMI spec as 8 bit values. However -in the hostboot code they will be defined as a uint16_t to allow us to add -additonal information. An example relates to error logs returned by the OCC, -we might want to pass the Entity ID in the upper byte of the sensor ID, this -would allow hostboot to search only the target type identifed by the Entity -ID for the sensor number returned with the elog. --> - -<!-- attribute to hold 16 pairs of sensor type, sensor number values --> -<attribute> - <id>IPMI_SENSORS</id> - <description>Attribute to hold 16 pairs of sensor name, sensor number - pairs. A sensor name consists of one byte of general sensor type - and one byte of sub-type</description> - <simpleType> - <uint16_t></uint16_t> - <array>16,2</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<enumerationType> - <id>IPMI_SENSOR_ARRAY</id> - <description>Enumeration defining the offsets into the - IPMI_SENSORS array.</description> - <enumerator> - <name>NAME_OFFSET</name> - <value>0x00</value> - </enumerator> - <enumerator> - <name>NUMBER_OFFSET</name> - <value>0x01</value> - </enumerator> -</enumerationType> - <attribute> <id>SCRATCH_UINT8_1</id> <description>Scratch attribute that can be used for dev/test</description> @@ -1113,7 +855,6 @@ ID for the sensor number returned with the elog. --> <id>ATTR_EXECUTION_PLATFORM</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -1189,6 +930,16 @@ ID for the sensor number returned with the elog. --> <bits>1</bits> <default>0</default> </field> + <field> + <name>specdeconfig</name> + <description>Set for speculative deconfig; + 0b0: target not speculative deconfig; + 0b1: target is speculatively deconfigured; + </description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> </complexType> <persistency>volatile</persistency> <readable/> @@ -1425,13 +1176,11 @@ ID for the sensor number returned with the elog. --> </complexType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> - <id>EEPROM_VPD_FRU_INFO</id> - <description>Information needed to address the EEPROM slaves for - IPMI Fru Inventory Purposes</description> + <id>EEPROM_VPD_BACKUP_INFO</id> + <description>Information needed to address the EERPROM slaves</description> <complexType> <description>Structure to define the addressing for an I2C slave device.</description> @@ -1493,23 +1242,13 @@ ID for the sensor number returned with the elog. --> <type>uint64_t</type> <default>0x0</default> </field> - <field> - <name>fruId</name> - <description>The IPMI Fru Inventory ID number. This must be a - unique number for every individual FRU within a - system.</description> - <type>uint8_t</type> - <default>0x0</default> - </field> </complexType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> - <attribute> - <id>EEPROM_VPD_BACKUP_INFO</id> + <id>EEPROM_SBE_PRIMARY_INFO</id> <description>Information needed to address the EERPROM slaves</description> <complexType> <description>Structure to define the addressing for an I2C @@ -1575,11 +1314,10 @@ ID for the sensor number returned with the elog. --> </complexType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> - <id>EEPROM_SBE_PRIMARY_INFO</id> + <id>EEPROM_SBE_BACKUP_INFO</id> <description>Information needed to address the EERPROM slaves</description> <complexType> <description>Structure to define the addressing for an I2C @@ -1645,15 +1383,21 @@ ID for the sensor number returned with the elog. --> </complexType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> - <id>EEPROM_SBE_BACKUP_INFO</id> - <description>Information needed to address the EERPROM slaves</description> + <id>TPM_PRIMARY_INFO</id> + <description>Information needed to address the TPM slaves</description> <complexType> <description>Structure to define the addressing for an I2C - slave device.</description> + TPM.</description> + <field> + <name>tpmEnabled</name> + <description>Boolean indicating whether this TPM is available + in the system</description> + <type>uint8_t</type> + <default>0x0</default> + </field> <field> <name>i2cMasterPath</name> <description>Entity path to the chip that contains the I2C @@ -1666,56 +1410,103 @@ ID for the sensor number returned with the elog. --> <description>Port from the I2C Master device. This is a 6-bit value.</description> <type>uint8_t</type> - <default>0x80</default> + <default>0x01</default> </field> <field> - <name>devAddr</name> - <description>Device address on the I2C bus. This is a 7-bit value, - but then shifted 1 bit left.</description> + <name>devAddrLocality0</name> + <description>Device address on the I2C bus for Locality 0. + This is a 7-bit value, but then shifted 1 + bit left.</description> <type>uint8_t</type> - <default>0x80</default> + <default>0xAE</default> + </field> + <field> + <name>devAddrLocality4</name> + <description>Device address on the I2C bus for Locality 4. + This is a 7-bit value, but then shifted 1 + bit left.</description> + <type>uint8_t</type> + <default>0xFF</default> </field> <field> <name>engine</name> <description>I2C master engine. This is a 2-bit value.</description> <type>uint8_t</type> - <default>0x80</default> + <default>0x00</default> </field> <field> <name>byteAddrOffset</name> <description>The number of bytes a device requires to set its internal address/offset.</description> <type>uint8_t</type> - <default>0x02</default> + <default>0x01</default> </field> + </complexType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> + +<attribute> + <id>TPM_BACKUP_INFO</id> + <description>Information needed to address the TPM slaves</description> + <complexType> + <description>Structure to define the addressing for an I2C + TPM device.</description> <field> - <name>maxMemorySizeKB</name> - <description>The number of kilobytes a device can hold. 'Zero' - value possible for some devices.</description> - <type>uint64_t</type> + <name>tpmEnabled</name> + <description>Boolean indicating whether this TPM is available + in the system</description> + <type>uint8_t</type> <default>0x0</default> </field> <field> - <name>writePageSize</name> - <description>The maximum number of bytes that can be written to - a device at one time. 'Zero' value means no maximum - value is expected or checked.</description> - <type>uint64_t</type> - <default>0x0</default> + <name>i2cMasterPath</name> + <description>Entity path to the chip that contains the I2C + master</description> + <type>EntityPath</type> + <default>physical:sys-0</default> </field> <field> - <name>writeCycleTime</name> - <description>The amount of time in milliseconds a device requires - on the completion of a write command to update its - internal memory.</description> - <type>uint64_t</type> - <default>0x0</default> + <name>port</name> + <description>Port from the I2C Master device. This is a 6-bit + value.</description> + <type>uint8_t</type> + <default>0x01</default> + </field> + <field> + <name>devAddrLocality0</name> + <description>Device address on the I2C bus for Locality 0. + This is a 7-bit value, but then shifted 1 + bit left.</description> + <type>uint8_t</type> + <default>0xAE</default> + </field> + <field> + <name>devAddrLocality4</name> + <description>Device address on the I2C bus for Locality 4. + This is a 7-bit value, but then shifted 1 + bit left.</description> + <type>uint8_t</type> + <default>0xFF</default> + </field> + <field> + <name>engine</name> + <description>I2C master engine. This is a 2-bit + value.</description> + <type>uint8_t</type> + <default>0x00</default> + </field> + <field> + <name>byteAddrOffset</name> + <description>The number of bytes a device requires to set its + internal address/offset.</description> + <type>uint8_t</type> + <default>0x01</default> </field> </complexType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -1748,7 +1539,6 @@ ID for the sensor number returned with the elog. --> <id>ATTR_CHIP_ID</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -2397,7 +2187,6 @@ ID for the sensor number returned with the elog. --> </complexType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -3000,6 +2789,119 @@ ID for the sensor number returned with the elog. --> <!-- ===== Processor Chip Attributes ===== --> +<enumerationType> + <id>NPU_MMIO_BAR_ENABLE</id> + <description>Enumeration indicating whether MMIO BAR is enabled or not to be + used with ATTR_PROC_NPU_MMIO_BAR_ENABLE</description> + <enumerator> + <name>DISABLE</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ENABLE</name> + <value>1</value> + </enumerator> +</enumerationType> + +<attribute> + <id>NPU_MMIO_BAR_ENABLE</id> + <description>NPU MMIO BAR enables + creator: platform + consumer: proc_setup_bars + firmware notes: none + first dimension: unit number (0:3) + second dimension: BAR number (0:1) + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>4,2</array> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> +<attribute> + <id>NPU_MMIO_BAR_BASE_ADDR</id> + <description>NPU MMIO BAR base address values + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit address representing BAR RA + NOTE: BAR register covers RA 14:51 + first dimension: unit number (0:3) + second dimension: BAR number (0:1) + </description> + <simpleType> + <uint64_t> + <default>0</default> + </uint64_t> + <array>4,2</array> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<enumerationType> + <id>NPU_MMIO_BAR_SIZE</id> + <description>Enumeration indicating the BAR size + used with ATTR_PROC_NPU_MMIO_BAR_SIZE</description> + <enumerator> + <name>2_MB</name> + <value>0x0000000000200000</value> + </enumerator> + <enumerator> + <name>1_MB</name> + <value>0x0000000000100000</value> + </enumerator> + <enumerator> + <name>512_KB</name> + <value>0x0000000000080000</value> + </enumerator> + <enumerator> + <name>256_KB</name> + <value>0x0000000000040000</value> + </enumerator> + <enumerator> + <name>128_KB</name> + <value>0x0000000000020000</value> + </enumerator> + <enumerator> + <name>64_KB</name> + <value>0x0000000000010000</value> + </enumerator> +</enumerationType> +<attribute> + <id>NPU_MMIO_BAR_SIZE</id> + <description>NPU MMIO BAR size values + creator: platform + consumer: proc_setup_bars + firmware notes: none + first dimension: unit number (0:3) + second dimension: BAR number (0:1) + </description> + <simpleType> + <uint64_t> + <default>0</default> + </uint64_t> + <array>4,2</array> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_NPU_MMIO_BAR_SIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + <attribute> <id>FSP_BASE_ADDR</id> <description>Base Address of FSP IO Region</description> @@ -3435,6 +3337,11 @@ ID for the sensor number returned with the elog. --> <name>FSP_UPDATE_SBE_IMAGE</name> <value>0x00020000</value> </enumerator> + <enumerator> + <!-- Update both sides of SBE Image if update is needed --> + <name>UPDATE_BOTH_SIDES_OF_SBE</name> + <value>0x00040000</value> + </enumerator> </enumerationType> <!-- Support for pm_hwp_attributes.xml --> @@ -4436,7 +4343,6 @@ Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C, <id>ATTR_PM_IVRMS_ENABLED</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -4489,7 +4395,6 @@ The value of Psafe needs to be at or below the nominal Pstate to make sure safe <id>ATTR_PM_RESONANT_CLOCK_ENABLE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -4508,7 +4413,6 @@ Defines the Pstate for the point at which clock sector buffers should be at full <id>ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -4526,7 +4430,6 @@ Defines the Pstate for the point at which clock sector buffers should be at full <id>ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -4544,7 +4447,6 @@ Defines the Pstate for the point at which clock sector buffers should be at full <id>ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -4562,7 +4464,6 @@ Defines the Pstate for the point at which clock sector buffers should be at full <id>ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -4580,7 +4481,6 @@ Defines the Pstate for the point at which clock sector buffers should be at full <id>ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -5046,7 +4946,6 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <id>ATTR_PM_SAFE_FREQUENCY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -5068,7 +4967,6 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <id>ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -5089,7 +4987,6 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -5110,7 +5007,6 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -5131,7 +5027,6 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -5152,7 +5047,6 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -5176,7 +5070,6 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <id>ATTR_PM_SPIPSS_FREQUENCY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -5785,11 +5678,11 @@ firmware notes: Used as override attribute for pstate procedure consumer: proc_pcie_scominit firmware notes: Encoded PCIE IOP swap configuration - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint8_t></uint8_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5807,7 +5700,7 @@ firmware notes: Used as override attribute for pstate procedure consumer: proc_pcie_scominit firmware notes: Bit mask defining set of active/valid PHBs - bit0=PHB0, bit1=PHB1, bit2=PHB2 + bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3 </description> <simpleType><uint8_t></uint8_t></simpleType> <persistency>non-volatile</persistency> @@ -5827,11 +5720,11 @@ firmware notes: Used as override attribute for pstate procedure firmware notes: PCIe Gen3 PLL Control Register 0. ATUNE/CPISEL. - Array index: IOP number(0:1) + Array index: IOP number(0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5849,11 +5742,11 @@ firmware notes: Used as override attribute for pstate procedure firmware notes: PCIe Gen2/Gen1 PLL Control Register 0. ATUNE/CPISEL. - Array index: IOP number(0:1) + Array index: IOP number(0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5871,11 +5764,11 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe PLL Global Control Register 0. REFISRC/REFISINK. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5893,11 +5786,11 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe PLL Global Control Register 1. ENBGDOCPSRC/ENBGDOCAMP/REFVREG. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5916,11 +5809,11 @@ firmware notes: Used as override attribute for pstate procedure PCIe PCS Control Register 0. BITLOCKTIME/ADDDREMDELTA_810_B/STARTUPDELTA_810_B/ADDDREMDELTA_810_A/ STARTUPDELTA_A/RXREJECTHANDLING/EQCOMLETERESPONSE. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5939,11 +5832,11 @@ firmware notes: Used as override attribute for pstate procedure PCIe PCS Control Register 1. RXSIGDETSETTING/ADDDREMDELTA_128130_B/STARTUPDELTA_128130_B/ ADDDREMDELTA_128130_A/STARTUPDELTA_128130_A. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5961,12 +5854,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe TX FIFO Offset Register. G3OFFSET/G2OFFSET/G1OFFSET. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5984,12 +5877,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe TX Receiver Detect Control Register. VREFSEL/RCVRDETCNT/DETDRVC/PH1WAIT. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -6007,12 +5900,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe TX Bandwidth Loss Coefficient Register. GEN3BWCOEFF/GEN2BWCOEFF/GEN1BWCOEFF. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -6030,12 +5923,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe RX VGA Control Register 2. GAIN2/GAIN1. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -6053,12 +5946,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe RX Receiver Peaking Value Register. PEAK1/PEAK2/PEAK3. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -6076,12 +5969,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe RX Signal Detect Level Register. SDLVL3/SDLVL2/SDLVL1. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -6099,11 +5992,11 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe ZCAL Control Register. CMPEVALDLY. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -10923,11 +10816,10 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript consumer: proc_pcie_scominit firmware notes: Bit mask defining state of refclock drive enables - bit0=PCI0, bit1=PCI1, bit2=PCI2 + bit0=PCI0, bit1=PCI1, bit2=PCI2, bit3=PCI3 </description> <simpleType> <uint8_t> - <default>0xE0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> @@ -10987,7 +10879,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_PROC_DCM_INSTALLED</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> @@ -11010,7 +10901,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_X_EREPAIR_THRESHOLD_FIELD</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -11031,7 +10921,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_A_EREPAIR_THRESHOLD_FIELD</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -11052,7 +10941,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_DMI_EREPAIR_THRESHOLD_FIELD</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -11073,7 +10961,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_X_EREPAIR_THRESHOLD_MNFG</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -11094,7 +10981,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_A_EREPAIR_THRESHOLD_MNFG</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -11115,7 +11001,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_DMI_EREPAIR_THRESHOLD_MNFG</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <!-- ===== End Attributes supporting erepair_thresholds.xml HWPF Attributes ===== --> @@ -11775,11 +11660,29 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <attribute> <id>FRU_ID</id> - <description>FRU ID attribute for chip class</description> + <description>FRU ID attribute used to report FRU information to the BMC for each + fru in the system.</description> + <simpleType><uint32_t><default>0</default></uint32_t></simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> + +<attribute> + <id>BMC_FRU_ID</id> + <description>BMC FRU ID attribute to report the system firmware levels to the BMC.</description> <simpleType><uint32_t><default>0</default></uint32_t></simpleType> <persistency>non-volatile</persistency> <readable/> - <global/> +</attribute> + +<attribute> + <id>CENTAUR_ECID_FRU_ID</id> + <description>FRU ID attribute for centaur ECID data. This fru ID is used to + report the ECID data to the BMC and make it available for systems which + have then centaur chips soldered to the backplane.</description> + <simpleType><uint8_t><default>0xFF</default></uint8_t></simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> @@ -12184,7 +12087,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <description> MFG_Guard policy: Used in MFG only to prevent and disable the following: - . Storing or creation of new Guard records from Diagnostic or other + . Storing or creation of new Guard records from Diagno`stic or other faults through error logs. This is all domains, CEC processor/memory, VPD, FSP, etc. . Storing or creation of Manual Guard record from user. @@ -12991,6 +12894,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> <id>ATTR_PROC_VRM_VOFFSET_VDD</id> <macro>DIRECT</macro> @@ -13012,6 +12916,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> <id>ATTR_PROC_VRM_VOFFSET_VCS</id> <macro>DIRECT</macro> @@ -13059,6 +12964,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> <id>ATTR_PROC_R_LOADLINE_VDD</id> <macro>DIRECT</macro> @@ -13080,6 +12986,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> <id>ATTR_PROC_R_LOADLINE_VCS</id> <macro>DIRECT</macro> @@ -13101,6 +13008,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> <id>ATTR_PROC_R_DISTLOSS_VDD</id> <macro>DIRECT</macro> @@ -13122,6 +13030,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> <id>ATTR_PROC_R_DISTLOSS_VCS</id> <macro>DIRECT</macro> @@ -13154,7 +13063,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_PM_UNDERVOLTING_FRQ_MINIMUM</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13183,7 +13091,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_PM_UNDERVOLTING_FREQ_MAXIMUM</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13207,7 +13114,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_PM_WINKLE_ENTRY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13233,7 +13139,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_PM_WINKLE_EXIT</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <enumerationType> @@ -13367,7 +13272,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -13392,12 +13296,12 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript consumer: proc_pcie_scominit notes: PCIe TX FFE (Gen1) - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -13414,12 +13318,12 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript consumer: proc_pcie_scominit notes: PCIe TX FFE (Gen2) - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -13541,7 +13445,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_PM_SYSTEM_IVRMS_ENABLED</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13561,7 +13464,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13761,7 +13663,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_REDUNDANT_CLOCKS</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13850,7 +13751,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_MNFG_DMI_MIN_EYE_WIDTH</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13872,7 +13772,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_MNFG_DMI_MIN_EYE_HEIGHT</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13894,7 +13793,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_MNFG_ABUS_MIN_EYE_WIDTH</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13916,7 +13814,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_MNFG_ABUS_MIN_EYE_HEIGHT</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -13938,7 +13835,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <id>ATTR_MNFG_XBUS_MIN_EYE_WIDTH</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <serverwizHide/> </attribute> <attribute> @@ -14285,10 +14181,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VDD_SLOPE_ACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> @@ -14302,10 +14195,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VDD_SLOPE_INACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> @@ -14319,10 +14209,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VDD_SLOPE_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> @@ -14336,10 +14223,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VCS_SLOPE_ACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> @@ -14353,10 +14237,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VCS_SLOPE_INACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> @@ -14370,10 +14251,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VCS_SLOPE_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> @@ -14387,10 +14265,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPP_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -14404,10 +14278,34 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPP_SLOPE_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT</id> + <description>Units: uV/DRAM + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> +</attribute> + +<attribute> + <id>MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT</id> + <description>Units: mV + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> @@ -14421,10 +14319,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DDR3_VDDR_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -14438,10 +14332,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DDR3_VDDR_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -14456,10 +14346,49 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_DDR3_VDDR_MAX_LIMIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id> + <description>Units: 1/Amps + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> +</attribute> + +<attribute> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <description>Units: mV + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> +</attribute> + +<attribute> + <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + <description>Maximum voltage limit for the dynamic VID DDR3 VDDR + voltage setpoint. In mV. + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> @@ -14473,10 +14402,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DDR4_VDDR_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -14490,10 +14415,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DDR4_VDDR_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -14508,10 +14429,49 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_DDR4_VDDR_MAX_LIMIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id> + <description>Units: 1/Amps + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> +</attribute> + +<attribute> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <description>Units: mV + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> +</attribute> + +<attribute> + <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage + setpoint. In mV. + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> @@ -14538,6 +14498,26 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </attribute> <attribute> + <id>MSS_VOLT_COMPLIANT_DIMMS</id> + <description> + Compliant Voltages. Created to call out non-compliant dimms + if they exist in the system. + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_VOLT_COMPLIANT_DIMMS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> <id>MSS_VDDR_OVERIDE_SPD</id> <description> DIMM SPD voltage override for VDDR voltage calculations. @@ -14805,22 +14785,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </attribute> <attribute> - <id>IOP_LANES_PER_PROC</id> - <description>Number of PCIE lanes per processor - Creator: Targeting definition - Purpose: Determines which IOP configuration table is used to build the - PE lane config value and PHB active masks for the HWPs - Data format: value of 24 or 32 (lanes per processor) - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> <id>PROC_PCIE_LANE_MASK</id> <description>Effective PCIE Lane Mask Creator: Firmware @@ -15155,7 +15119,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15171,6 +15134,60 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <readable/> <writeable/> </attribute> +<enumerationType> + <id>SUPPORTED_HOT_PLUG</id> + <description> + Enumeration indication which Hot Plug Controllers are supported by + the current system. + </description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>MAX5961</name> + <value>0x01</value> + </enumerator> + <enumerator> + <name>PCA9551</name> + <value>0x02</value> + </enumerator> + <default>NA</default> +</enumerationType> + +<attribute> + <id>HOT_PLUG_POWER_CONTROLLER_INFO</id> + <description>Hot Plug Controller values for a specific processor. + Purpose: Holds information about the hot plug controllers so that a + Hardware procedure is able to turn them on and off. + Data Format: up to 8 Hot Plug Controllers x 7 variables of information + This data is at the processor level. + The needed information and their individual sizes are as follows: + (1) I2C Master processor engine (uint8_t) + (2) I2C Master processor port (uint8_t) + (3) Bus Speed (uint16_t value: 2 uint8_t values: MSB, LSB) + (4) Slave address (uint8_t) + (5) Device type (uint8_t: see SUPPORTED_HOT_PLUG enum) + (6) I2C Master processor node (uint8_t) + (7) I2C Master processor position (uint8_t) + Thus, the information will be 8 bytes. + </description> + <simpleType> + <uint8_t> + <default>0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + </default> + </uint8_t> + <array>8,8</array> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_HOT_PLUG_POWER_CONTROLLER_INFO</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> <attribute> <id>ISTEP_PAUSE_CONFIG</id> @@ -15219,6 +15236,64 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> +<attribute> + <id>PROC_PCIE_NUM_PHB</id> + <description> + creator: platform + Number of PCIe PHB units present on target + Murano/Venice: 3 + Naples: 4 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_NUM_PHB</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_PCIE_NUM_IOP</id> + <description> + creator: platform + Number of PCIe IOP units present on target + Murano/Venice: 2 + Naples: 3 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_NUM_IOP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_PCIE_NUM_LANES</id> + <description> + creator: platform + Number of PCIe I/O lanes supported by target + Murano: 24 + Venice: 32 + Naples: 40 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_NUM_LANES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + <!-- === Manufacturing threshold Attributes of PRD === --> <attribute> @@ -15230,11 +15305,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>1</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15246,11 +15321,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>1</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15262,11 +15337,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>3</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15278,11 +15353,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>1</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15294,11 +15369,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>6</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15310,11 +15385,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>6</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15326,11 +15401,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>7</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15342,11 +15417,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>7</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15358,11 +15433,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15374,11 +15449,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15390,11 +15465,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15406,11 +15481,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15422,11 +15497,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>2</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15438,11 +15513,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>2</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15454,11 +15529,11 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>2</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> <attribute> @@ -15469,40 +15544,268 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </description> <simpleType> <uint8_t> + <default>2</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <serverwizHide/> </attribute> -<!-- === Manufacturing threshold Attributes of PRD === --> <attribute> - <id>OPAL_MODEL</id> + <id>RESOURCE_IS_CRITICAL</id> <description> - Specifies the compatible model name for Opal to key off of. - This is sourced from the MRW and should be of the format - 'vendor,model', e.g. 'tyan,palmetto'. + Used to tell if a resource is critical to perform an IPL. If this + attribute is set to 1 and the target is deconfigured, the IPL MUST + terminate. </description> <simpleType> - <string> - <default>tyan,palmetto</default><!-- @fixme-RTC:120092 --> - <sizeInclNull>32</sizeInclNull> - </string> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> + + +<attribute> + <id>BRAZOS_RX_FIFO_OVERRIDE</id> + <description> + Defines where to apply Brazos rx_fifo_final_l2u_dly override settings for SW299500. + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> + <hwpfToHbAttrMap> + <id>ATTR_BRAZOS_RX_FIFO_OVERRIDE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<!-- === Manufacturing threshold Attributes of PRD === --> + +<attribute> + <id>MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id> + <description>Maximum number of installed DIMMs per VMEM regulator for all + VMEM regulators in the system. + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> + +<attribute> + <id>MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id> + <description>Machine Readable Workbook enablement of the HWP code to adjust + the VMEM regulator power limit based on number of installed DIMMs. + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id> + <description>Machine Readable Workbook value for the maximum possible number + of dimms that can be installed under any of the VMEM regulators. + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id> + <description>Machine Readable Workbook VMEM regulator power limit per CDIMM + assuming a full configuration. Units in cW. + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<enumerationType> + <id>MRW_NEST_CAPABLE_FREQUENCIES_SYS</id> + <description>Enumeration of MRW_NEST_CAPABLE_FREQUENCIES_SYS</description> + <enumerator> + <name>UNSUPPORTED_FREQ</name> + <value>0</value> + </enumerator> + <enumerator> + <name>2000_MHZ</name> + <value>1</value> + </enumerator> + <enumerator> + <name>2400_MHZ</name> + <value>2</value> + </enumerator> + <enumerator> + <name>2000_MHZ_OR_2400_MHZ</name> + <value>3</value> + </enumerator> +</enumerationType> + <attribute> - <id>ENTITY_ID</id> - <description></description> + <id>MRW_NEST_CAPABLE_FREQUENCIES_SYS</id> + <description>The NEST frequencies that the system can support. This is a bit-wise value that represents which of the possible nest frequencies are supported : 2.0GHz, 2.4GHz, or both. + </description> <simpleType> <enumeration> - <id>ENTITY_ID</id> + <id>MRW_NEST_CAPABLE_FREQUENCIES_SYS</id> + <default>UNSUPPORTED_FREQ</default> </enumeration> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hasStringConversion/> </attribute> + +<attribute> + <id>WOF_ENABLED</id> + <description> + Defines if the Workload Optimization Frequency (WOF) system feature + where OCC algorithms will change (typically boost) the operational + frequency based on measured power available and any currently idling + cores. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_WOF_ENABLED</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>TRUSTED_SLAVE_SCAN_PATH_ACTIVE</id> + <description> + Set to indicate state of master->slave scan path. + Platform should default to false at beginning of IPL, and set to + true once trusted XSCOM path is active to all slave chips in drawer + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_TRUSTED_SLAVE_SCAN_PATH_ACTIVE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>FORCE_SKIP_SBE_MASTER_INTR_SERVICE</id> + <description> + Set to force skip of SBE interrupt service for master chip. + Default is to disable the use of the SBE interrupt service. + </description> + <simpleType> + <uint8_t> + <default>1</default> + </uint8_t> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_FORCE_SKIP_SBE_MASTER_INTR_SERVICE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>FORCE_USE_SBE_SLAVE_SCAN_SERVICE</id> + <description> + Set to force use of SBE scan service for slave chips. + Default is to enable the use of the SBE scan service + only for slave chips with security enabled. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>SBE_MASTER_INTR_SERVICE_DELAY_CYCLES</id> + <description> + Cycle delay of SBE master interrupt service loop wait statement. + Paces rate of decrementer progress and prevents SBE from consuming PIB. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_SBE_MASTER_INTR_SERVICE_DELAY_CYCLES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>SBE_MASTER_INTR_SERVICE_DELAY_US</id> + <description> + Execution delay (in microseconds) of SBE master interrupt service loop. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_SBE_MASTER_INTR_SERVICE_DELAY_US</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/xml/attribute_types_hb.xml b/xml/attribute_types_hb.xml index 57fb8e6..c30e652 100644 --- a/xml/attribute_types_hb.xml +++ b/xml/attribute_types_hb.xml @@ -31,6 +31,46 @@ Contains the definition of hostboot attributes which should not be synced to/from FSP ================================================================= --> +<attribute> + <id>HIDDEN_ERRLOGS_ENABLE</id> + <description> + Used to decide whether or not to prevent INFORMATIONAL/RECOVERED error + logs from being sent to the BMC via SEL/eSEL, saved to the PNOR, and + displayed to the console. + 0 = Prevent INFORMATIONAL/RECOVERED error logs from being processed. + 1 = Send only INFORMATIONAL error logs. + 2 = Send only RECOVERED error logs. + 3 = Allow all hidden error logs to be processed. + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile</persistency> + <readable/> +</attribute> + +<enumerationType> + <id>HIDDEN_ERRLOGS_ENABLE</id> + <description>Enumeration of HIDDEN_ERRLOGS_ENABLE</description> + <enumerator> + <name>NO_HIDDEN_LOGS</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ALLOW_INFORMATIONAL</name> + <value>1</value> + </enumerator> + <enumerator> + <name>ALLOW_RECOVERED</name> + <value>2</value> + </enumerator> + <enumerator> + <name>ALLOW_ALL_LOGS</name> + <value>3</value> + </enumerator> +</enumerationType> <attribute> <id>IS_MPIPL_HB</id> @@ -239,7 +279,7 @@ <attribute> <id>HB_EXISTING_IMAGE</id> <description>Indicates which logical nodes have a hostboot image.</description> - <!-- Bit position [0-7] (left to right) represents logical node. + <!-- Bit position [0-7] (left to right) represents logical node. '1' means the logical node has an active hostboot image. --> <simpleType> @@ -339,6 +379,20 @@ </attribute> <attribute> + <id>OCC_COMMON_AREA_PHYS_ADDR</id> + <description> + Physical address where OCC Common Area is placed in mainstore. + </description> + <simpleType> + <uint64_t></uint64_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> <id>HOMER_PHYS_ADDR</id> <description> Physical address where HOMER image is placed in mainstore. @@ -570,7 +624,16 @@ <persistency>non-volatile</persistency> <readable/> </attribute> - +<attribute> + <id>ADC_CHANNEL_SENSOR_NUMBERS</id> + <description>ADC Channel IPMI sensor numbers. 16 channels.</description> + <simpleType> + <uint16_t></uint16_t> + <array>16</array> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> <attribute> <id>ADC_CHANNEL_GNDS</id> <description>ADC Channel ground. 16 channels.</description> @@ -642,6 +705,18 @@ </attribute> <attribute> + <id>PSTATE_TABLE_MFG</id> + <description>HTMGT PSTATE data for mfg</description> + <simpleType> + <uint8_t></uint8_t> + <array>1904</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> +</attribute> + +<attribute> <id>OCC_CONTROL_DATA</id> <description>OCC operational data </description> @@ -743,9 +818,26 @@ <complexType> <description>VPD flags</description> <field> - <name>pnorLoaded</name> + <name>pnorCacheValid</name> <description>Set when this target's VPD data has been loaded - into the PNOR. + from EEPROM into the PNOR. + </description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>pnorCacheValidRT</name> + <description>See pnorCacheValid. Allows runtime version to be + set separately from common version. + </description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>disableWriteToPnorRT</name> + <description>Set to disable write-thru to PNOR at runtime </description> <type>uint8_t</type> <bits>1</bits> @@ -755,7 +847,7 @@ <name>reserved</name> <description>Reserved for future expansion</description> <type>uint8_t</type> - <bits>7</bits> + <bits>5</bits> <default>0</default> </field> </complexType> @@ -773,7 +865,7 @@ </description> <simpleType> <string> - <default>tyan,palmetto</default><!-- @fixme-RTC:120092 --> + <default>ibm,miscopenpower</default> <sizeInclNull>32</sizeInclNull> </string> </simpleType> @@ -801,4 +893,508 @@ </hwpfToHbAttrMap> </attribute> +<attribute> + <id>HTMGT_SAFEMODE</id> + <description>1 = in safemode. 0 = in normal mode.</description> + <simpleType> + <uint8_t> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> +<attribute> + <id>IPMI_INSTANCE</id> + <description>Holds the IPMI instance number for this entity.</description> + <simpleType> + <uint32_t> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> +<enumerationType> + <id>ENTITY_ID</id> + <description>Enumeration indicating the IPMI entity ID, these values are + defined in the IPMI specification. These values will be used in place + of target type when events are sent to the BMC.</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>OTHER</name> + <value>0x01</value> + </enumerator> + <enumerator> + <name>PROCESSOR</name> + <value>0x03</value> + </enumerator> + <enumerator> + <name>SYSTEM_BOARD</name> + <value>0x07</value> + </enumerator> + <enumerator> + <name>POWER_MGMT</name> + <value>0x15</value> + </enumerator> + <enumerator> + <name>CHASSIS</name> + <value>0x17</value> + </enumerator> + <enumerator> + <name>MEMORY_DEVICE</name> + <value>0x20</value> + </enumerator> + <enumerator> + <name>BIOS</name> + <value>0x22</value> + </enumerator> + <enumerator> + <name>OS</name> + <value>0x23</value> + </enumerator> + <enumerator> + <name>CORE</name> + <value>0xD0</value> + </enumerator> + <enumerator> + <name>MEMBUF</name> + <value>0xD1</value> + </enumerator> + <enumerator> + <name>OCC</name> + <value>0xD2</value> + </enumerator> + <enumerator> + <name>REF_CLOCK</name> + <value>0xD4</value> + </enumerator> + <enumerator> + <name>PCI_CLOCK</name> + <value>0xD5</value> + </enumerator> + <enumerator> + <name>TOD_CLOCK</name> + <value>0xD6</value> + </enumerator> + <enumerator> + <name>APSS</name> + <value>0xD7</value> + </enumerator> +</enumerationType> + +<enumerationType> + <id>SENSOR_NAME</id> + <description>Enumeration indicating the IPMI sensor name, which will + be used by hostboot when determining the sensor number to return. + he sensor name consists of one byte of sensor type plus one byte of + sub-type, to differentiate similar sensors under the same target. + Our implementaion uses the IPMI defined entity ID as the sub-type. + </description> + <enumerator> + <name>PROC_TEMP</name> + <value>0x0103</value> + </enumerator> + <enumerator> + <name>DIMM_TEMP</name> + <value>0x0120</value> + </enumerator> + <enumerator> + <name>CORE_TEMP</name> + <value>0x01D0</value> + </enumerator> + <enumerator> + <name>STATE</name> + <value>0x0500</value> + </enumerator> + <enumerator> + <name>MEMBUF_TEMP</name> + <value>0x01D1</value> + </enumerator> + <enumerator> + <name>PROC_STATE</name> + <value>0x0703</value> + </enumerator> + <enumerator> + <name>CORE_STATE</name> + <value>0x07D0</value> + </enumerator> + <enumerator> + <name>DIMM_STATE</name> + <value>0x0C20</value> + </enumerator> + <enumerator> + <name>MEMBUF_STATE</name> + <value>0x0CD1</value> + </enumerator> + <enumerator> + <name>FW_BOOT_PROGRESS</name> + <value>0x0F22</value> + </enumerator> + <enumerator> + <name>SYSTEM_EVENT</name> + <value>0x1201</value> + </enumerator> + <enumerator> + <name>OS_BOOT</name> + <value>0x1F23</value> + </enumerator> + <enumerator> + <name>HOST_STATUS</name> + <value>0x2223</value> + </enumerator> + <enumerator> + <name>OCC_ACTIVE</name> + <value>0x07D2</value> + </enumerator> + <enumerator> + <name>CORE_FREQ</name> + <value>0xC1D0</value> + </enumerator> + <enumerator> + <name>APSS_CHANNEL</name> + <value>0xC2D7</value> + </enumerator> + <enumerator> + <name>PCI_ACTIVE</name> + <value>0xC423</value> + </enumerator> + <enumerator> + <name>REBOOT_COUNT</name> + <value>0xC322</value> + </enumerator> + <enumerator> + <name>FAULT</name> + <value>0xC700</value> + </enumerator> + <enumerator> + <name>BACKPLANE_FAULT</name> + <value>0xC707</value> + </enumerator> + <enumerator> + <name>REF_CLOCK_FAULT</name> + <value>0xC7D4</value> + </enumerator> + <enumerator> + <name>PCI_CLOCK_FAULT</name> + <value>0xC7D5</value> + </enumerator> + <enumerator> + <name>TOD_CLOCK_FAULT</name> + <value>0xC7D6</value> + </enumerator> + <enumerator> + <name>APSS_FAULT</name> + <value>0xC7D7</value> + </enumerator> + <enumerator> + <name>DERATING_FACTOR</name> + <value>0xC815</value> + </enumerator> +</enumerationType> + +<enumerationType> + <id>SENSOR_TYPE</id> + <description>Enumeration indicating the IPMI sensor type, these values + are defined in the IPMI specification. These values will be used when + sending sensor reading events to the BMC.</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>TEMPERATURE</name> + <value>0x01</value> + </enumerator> + <enumerator> + <name>PROCESSOR</name> + <value>0x07</value> + </enumerator> + <enumerator> + <name>MEMORY</name> + <value>0x0c</value> + </enumerator> + <enumerator> + <name>SYS_FW_PROGRESS</name> + <value>0x0F</value> + </enumerator> + <enumerator> + <name>SYS_EVENT</name> + <value>0x12</value> + </enumerator> + <enumerator> + <name>OS_BOOT</name> + <value>0x1F</value> + </enumerator> + <enumerator> + <name>APCI_POWER_STATE</name> + <value>0x22</value> + </enumerator> + <enumerator> + <name>FREQ</name> + <value>0xC1</value> + </enumerator> + <enumerator> + <name>POWER</name> + <value>0xC2</value> + </enumerator> + <enumerator> + <name>BOOT_COUNT</name> + <value>0xC3</value> + </enumerator> + <enumerator> + <name>PCI_LINK_PRES</name> + <value>0xC4</value> + </enumerator> + <enumerator> + <name>PWR_LIMIT_ACTIVE</name> + <value>0xC4</value> + </enumerator> + <enumerator> + <name>FAULT</name> + <value>0xC7</value> + </enumerator> +</enumerationType> + +<!-- IPMI Sensor numbers are defined in the IPMI spec as 8 bit values. However +in the hostboot code they will be defined as a uint16_t to allow us to add +additonal information. An example relates to error logs returned by the OCC, +we might want to pass the Entity ID in the upper byte of the sensor ID, this +would allow hostboot to search only the target type identifed by the Entity +ID for the sensor number returned with the elog. --> + +<!-- attribute to hold 16 pairs of sensor type, sensor number values --> +<attribute> + <id>IPMI_SENSORS</id> + <description>Attribute to hold 16 pairs of sensor name, sensor number + pairs. A sensor name consists of one byte of general sensor type + and one byte of sub-type</description> + <simpleType> + <uint16_t></uint16_t> + <array>16,2</array> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> +<enumerationType> + <id>IPMI_SENSOR_ARRAY</id> + <description>Enumeration defining the offsets into the + IPMI_SENSORS array.</description> + <enumerator> + <name>NAME_OFFSET</name> + <value>0x00</value> + </enumerator> + <enumerator> + <name>NUMBER_OFFSET</name> + <value>0x01</value> + </enumerator> +</enumerationType> + +<attribute> + <id>IPMI_MAX_BUFFER_SIZE</id> + <description>max buffer size to use for ipmi messages</description> + <simpleType> + <uint32_t> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>SERIAL_NUMBER</id> + <description>The serial number for a particular FRU target</description> + <simpleType> + <uint8_t> + <default>0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0</default> + </uint8_t> + <array>18</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_SERIAL_NUMBER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + <hbOnly/> +</attribute> + +<attribute> + <id>PART_NUMBER</id> + <description>The part number for a particular FRU target</description> + <simpleType> + <uint8_t> + <default>0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0</default> + </uint8_t> + <array>18</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PART_NUMBER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + <hbOnly/> +</attribute> + +<attribute> + <id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id> + <description>Units: uV/DRAM + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id> + <description>Units: mV + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id> + <description>Units: 1/Amps + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id> + <description>Units: mV + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id> + <description>Maximum voltage limit for the dynamic VID DDR3 VDDR + voltage setpoint. In mV. + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id> + <description>Units: 1/Amps + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id> + <description>Units: mV + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id> + <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage + setpoint. In mV. + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>SBE_MASTER_INTR_SERVICE_ENABLED</id> + <description> + Indicator whether the SBE interupt service is anabled. + 0=Not Enabled + 1=Enabled + </description> + <simpleType> + <uint8_t> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> +</attribute> + +<attribute> + <id>CLEAR_DIMM_SPD_ENABLE</id> + <description> + Used to enable clearing of SPD on all present DIMMs. This attribute is + set via attribute override. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> +</attribute> + </attributes> diff --git a/xml/target_types_mrw.xml b/xml/target_types_mrw.xml index a292e57..f980dde 100644 --- a/xml/target_types_mrw.xml +++ b/xml/target_types_mrw.xml @@ -22,6 +22,11 @@ <default></default> </attribute> <attribute> + <attribute> + <id>BMC_FRU_ID</id> + <default></default> + </attribute> + <attribute> <id>OPAL_MODEL</id> <default></default> </attribute> @@ -34,10 +39,6 @@ <default></default> </attribute> <attribute> - <id>MSS_INTERLEAVE_ENABLE</id> - <default></default> - </attribute> - <attribute> <id>MODEL</id> <default>POWER8</default> </attribute> @@ -514,6 +515,10 @@ <attribute> <id>MODEL</id> </attribute> + <attribute> + <id>RESOURCE_IS_CRITICAL</id> + <default>0</default> + </attribute> </targetType> <targetType> <id>chip</id> @@ -859,7 +864,11 @@ <attribute> <id>IBSCOM_PROC_BASE_ADDR</id> <default>1,0x0003E00000000000,0x40000000000,0x10000000000,0</default> - </attribute> + </attribute> + <attribute> + <id>MSS_INTERLEAVE_ENABLE</id> + <default></default> + </attribute> <attribute> <id>EEPROM_SBE_BACKUP_INFO</id> <default> @@ -1147,7 +1156,11 @@ <attribute> <id>IBSCOM_PROC_BASE_ADDR</id> <default>1,0x0003E00000000000,0x40000000000,0x10000000000,0</default> - </attribute> + </attribute> + <attribute> + <id>MSS_INTERLEAVE_ENABLE</id> + <default></default> + </attribute> <attribute> <id>EEPROM_SBE_BACKUP_INFO</id> <default> @@ -1732,6 +1745,10 @@ <attribute> <id>FRU_ID</id> </attribute> + <attribute> + <id>CENTAUR_ECID_FRU_ID</id> + <default>0xFF</default> + </attribute> </targetType> <!-- Centaur L4 --> |
