1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
|
/* IEEE-754 double-precision functions for Xtensa
Copyright (C) 2006-2013 Free Software Foundation, Inc.
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifdef __XTENSA_EB__
#define xh a2
#define xl a3
#define yh a4
#define yl a5
#else
#define xh a3
#define xl a2
#define yh a5
#define yl a4
#endif
/* Warning! The branch displacements for some Xtensa branch instructions
are quite small, and this code has been carefully laid out to keep
branch targets in range. If you change anything, be sure to check that
the assembler is not relaxing anything to branch over a jump. */
#ifdef L_negdf2
.align 4
.global __negdf2
.type __negdf2, @function
__negdf2:
leaf_entry sp, 16
movi a4, 0x80000000
xor xh, xh, a4
leaf_return
#endif /* L_negdf2 */
#ifdef L_addsubdf3
/* Addition */
__adddf3_aux:
/* Handle NaNs and Infinities. (This code is placed before the
start of the function just to keep it in range of the limited
branch displacements.) */
.Ladd_xnan_or_inf:
/* If y is neither Infinity nor NaN, return x. */
bnall yh, a6, 1f
/* If x is a NaN, return it. Otherwise, return y. */
slli a7, xh, 12
or a7, a7, xl
beqz a7, .Ladd_ynan_or_inf
1: leaf_return
.Ladd_ynan_or_inf:
/* Return y. */
mov xh, yh
mov xl, yl
leaf_return
.Ladd_opposite_signs:
/* Operand signs differ. Do a subtraction. */
slli a7, a6, 11
xor yh, yh, a7
j .Lsub_same_sign
.align 4
.global __adddf3
.type __adddf3, @function
__adddf3:
leaf_entry sp, 16
movi a6, 0x7ff00000
/* Check if the two operands have the same sign. */
xor a7, xh, yh
bltz a7, .Ladd_opposite_signs
.Ladd_same_sign:
/* Check if either exponent == 0x7ff (i.e., NaN or Infinity). */
ball xh, a6, .Ladd_xnan_or_inf
ball yh, a6, .Ladd_ynan_or_inf
/* Compare the exponents. The smaller operand will be shifted
right by the exponent difference and added to the larger
one. */
extui a7, xh, 20, 12
extui a8, yh, 20, 12
bltu a7, a8, .Ladd_shiftx
.Ladd_shifty:
/* Check if the smaller (or equal) exponent is zero. */
bnone yh, a6, .Ladd_yexpzero
/* Replace yh sign/exponent with 0x001. */
or yh, yh, a6
slli yh, yh, 11
srli yh, yh, 11
.Ladd_yexpdiff:
/* Compute the exponent difference. Optimize for difference < 32. */
sub a10, a7, a8
bgeui a10, 32, .Ladd_bigshifty
/* Shift yh/yl right by the exponent difference. Any bits that are
shifted out of yl are saved in a9 for rounding the result. */
ssr a10
movi a9, 0
src a9, yl, a9
src yl, yh, yl
srl yh, yh
.Ladd_addy:
/* Do the 64-bit addition. */
add xl, xl, yl
add xh, xh, yh
bgeu xl, yl, 1f
addi xh, xh, 1
1:
/* Check if the add overflowed into the exponent. */
extui a10, xh, 20, 12
beq a10, a7, .Ladd_round
mov a8, a7
j .Ladd_carry
.Ladd_yexpzero:
/* y is a subnormal value. Replace its sign/exponent with zero,
i.e., no implicit "1.0", and increment the apparent exponent
because subnormals behave as if they had the minimum (nonzero)
exponent. Test for the case when both exponents are zero. */
slli yh, yh, 12
srli yh, yh, 12
bnone xh, a6, .Ladd_bothexpzero
addi a8, a8, 1
j .Ladd_yexpdiff
.Ladd_bothexpzero:
/* Both exponents are zero. Handle this as a special case. There
is no need to shift or round, and the normal code for handling
a carry into the exponent field will not work because it
assumes there is an implicit "1.0" that needs to be added. */
add xl, xl, yl
add xh, xh, yh
bgeu xl, yl, 1f
addi xh, xh, 1
1: leaf_return
.Ladd_bigshifty:
/* Exponent difference > 64 -- just return the bigger value. */
bgeui a10, 64, 1b
/* Shift yh/yl right by the exponent difference. Any bits that are
shifted out are saved in a9 for rounding the result. */
ssr a10
sll a11, yl /* lost bits shifted out of yl */
src a9, yh, yl
srl yl, yh
movi yh, 0
beqz a11, .Ladd_addy
or a9, a9, a10 /* any positive, nonzero value will work */
j .Ladd_addy
.Ladd_xexpzero:
/* Same as "yexpzero" except skip handling the case when both
exponents are zero. */
slli xh, xh, 12
srli xh, xh, 12
addi a7, a7, 1
j .Ladd_xexpdiff
.Ladd_shiftx:
/* Same thing as the "shifty" code, but with x and y swapped. Also,
because the exponent difference is always nonzero in this version,
the shift sequence can use SLL and skip loading a constant zero. */
bnone xh, a6, .Ladd_xexpzero
or xh, xh, a6
slli xh, xh, 11
srli xh, xh, 11
.Ladd_xexpdiff:
sub a10, a8, a7
bgeui a10, 32, .Ladd_bigshiftx
ssr a10
sll a9, xl
src xl, xh, xl
srl xh, xh
.Ladd_addx:
add xl, xl, yl
add xh, xh, yh
bgeu xl, yl, 1f
addi xh, xh, 1
1:
/* Check if the add overflowed into the exponent. */
extui a10, xh, 20, 12
bne a10, a8, .Ladd_carry
.Ladd_round:
/* Round up if the leftover fraction is >= 1/2. */
bgez a9, 1f
addi xl, xl, 1
beqz xl, .Ladd_roundcarry
/* Check if the leftover fraction is exactly 1/2. */
slli a9, a9, 1
beqz a9, .Ladd_exactlyhalf
1: leaf_return
.Ladd_bigshiftx:
/* Mostly the same thing as "bigshifty".... */
bgeui a10, 64, .Ladd_returny
ssr a10
sll a11, xl
src a9, xh, xl
srl xl, xh
movi xh, 0
beqz a11, .Ladd_addx
or a9, a9, a10
j .Ladd_addx
.Ladd_returny:
mov xh, yh
mov xl, yl
leaf_return
.Ladd_carry:
/* The addition has overflowed into the exponent field, so the
value needs to be renormalized. The mantissa of the result
can be recovered by subtracting the original exponent and
adding 0x100000 (which is the explicit "1.0" for the
mantissa of the non-shifted operand -- the "1.0" for the
shifted operand was already added). The mantissa can then
be shifted right by one bit. The explicit "1.0" of the
shifted mantissa then needs to be replaced by the exponent,
incremented by one to account for the normalizing shift.
It is faster to combine these operations: do the shift first
and combine the additions and subtractions. If x is the
original exponent, the result is:
shifted mantissa - (x << 19) + (1 << 19) + (x << 20)
or:
shifted mantissa + ((x + 1) << 19)
Note that the exponent is incremented here by leaving the
explicit "1.0" of the mantissa in the exponent field. */
/* Shift xh/xl right by one bit. Save the lsb of xl. */
mov a10, xl
ssai 1
src xl, xh, xl
srl xh, xh
/* See explanation above. The original exponent is in a8. */
addi a8, a8, 1
slli a8, a8, 19
add xh, xh, a8
/* Return an Infinity if the exponent overflowed. */
ball xh, a6, .Ladd_infinity
/* Same thing as the "round" code except the msb of the leftover
fraction is bit 0 of a10, with the rest of the fraction in a9. */
bbci.l a10, 0, 1f
addi xl, xl, 1
beqz xl, .Ladd_roundcarry
beqz a9, .Ladd_exactlyhalf
1: leaf_return
.Ladd_infinity:
/* Clear the mantissa. */
movi xl, 0
srli xh, xh, 20
slli xh, xh, 20
/* The sign bit may have been lost in a carry-out. Put it back. */
slli a8, a8, 1
or xh, xh, a8
leaf_return
.Ladd_exactlyhalf:
/* Round down to the nearest even value. */
srli xl, xl, 1
slli xl, xl, 1
leaf_return
.Ladd_roundcarry:
/* xl is always zero when the rounding increment overflows, so
there's no need to round it to an even value. */
addi xh, xh, 1
/* Overflow to the exponent is OK. */
leaf_return
/* Subtraction */
__subdf3_aux:
/* Handle NaNs and Infinities. (This code is placed before the
start of the function just to keep it in range of the limited
branch displacements.) */
.Lsub_xnan_or_inf:
/* If y is neither Infinity nor NaN, return x. */
bnall yh, a6, 1f
/* Both x and y are either NaN or Inf, so the result is NaN. */
movi a4, 0x80000 /* make it a quiet NaN */
or xh, xh, a4
1: leaf_return
.Lsub_ynan_or_inf:
/* Negate y and return it. */
slli a7, a6, 11
xor xh, yh, a7
mov xl, yl
leaf_return
.Lsub_opposite_signs:
/* Operand signs differ. Do an addition. */
slli a7, a6, 11
xor yh, yh, a7
j .Ladd_same_sign
.align 4
.global __subdf3
.type __subdf3, @function
__subdf3:
leaf_entry sp, 16
movi a6, 0x7ff00000
/* Check if the two operands have the same sign. */
xor a7, xh, yh
bltz a7, .Lsub_opposite_signs
.Lsub_same_sign:
/* Check if either exponent == 0x7ff (i.e., NaN or Infinity). */
ball xh, a6, .Lsub_xnan_or_inf
ball yh, a6, .Lsub_ynan_or_inf
/* Compare the operands. In contrast to addition, the entire
value matters here. */
extui a7, xh, 20, 11
extui a8, yh, 20, 11
bltu xh, yh, .Lsub_xsmaller
beq xh, yh, .Lsub_compare_low
.Lsub_ysmaller:
/* Check if the smaller (or equal) exponent is zero. */
bnone yh, a6, .Lsub_yexpzero
/* Replace yh sign/exponent with 0x001. */
or yh, yh, a6
slli yh, yh, 11
srli yh, yh, 11
.Lsub_yexpdiff:
/* Compute the exponent difference. Optimize for difference < 32. */
sub a10, a7, a8
bgeui a10, 32, .Lsub_bigshifty
/* Shift yh/yl right by the exponent difference. Any bits that are
shifted out of yl are saved in a9 for rounding the result. */
ssr a10
movi a9, 0
src a9, yl, a9
src yl, yh, yl
srl yh, yh
.Lsub_suby:
/* Do the 64-bit subtraction. */
sub xh, xh, yh
bgeu xl, yl, 1f
addi xh, xh, -1
1: sub xl, xl, yl
/* Subtract the leftover bits in a9 from zero and propagate any
borrow from xh/xl. */
neg a9, a9
beqz a9, 1f
addi a5, xh, -1
moveqz xh, a5, xl
addi xl, xl, -1
1:
/* Check if the subtract underflowed into the exponent. */
extui a10, xh, 20, 11
beq a10, a7, .Lsub_round
j .Lsub_borrow
.Lsub_compare_low:
/* The high words are equal. Compare the low words. */
bltu xl, yl, .Lsub_xsmaller
bltu yl, xl, .Lsub_ysmaller
/* The operands are equal. Return 0.0. */
movi xh, 0
movi xl, 0
1: leaf_return
.Lsub_yexpzero:
/* y is a subnormal value. Replace its sign/exponent with zero,
i.e., no implicit "1.0". Unless x is also a subnormal, increment
y's apparent exponent because subnormals behave as if they had
the minimum (nonzero) exponent. */
slli yh, yh, 12
srli yh, yh, 12
bnone xh, a6, .Lsub_yexpdiff
addi a8, a8, 1
j .Lsub_yexpdiff
.Lsub_bigshifty:
/* Exponent difference > 64 -- just return the bigger value. */
bgeui a10, 64, 1b
/* Shift yh/yl right by the exponent difference. Any bits that are
shifted out are saved in a9 for rounding the result. */
ssr a10
sll a11, yl /* lost bits shifted out of yl */
src a9, yh, yl
srl yl, yh
movi yh, 0
beqz a11, .Lsub_suby
or a9, a9, a10 /* any positive, nonzero value will work */
j .Lsub_suby
.Lsub_xsmaller:
/* Same thing as the "ysmaller" code, but with x and y swapped and
with y negated. */
bnone xh, a6, .Lsub_xexpzero
or xh, xh, a6
slli xh, xh, 11
srli xh, xh, 11
.Lsub_xexpdiff:
sub a10, a8, a7
bgeui a10, 32, .Lsub_bigshiftx
ssr a10
movi a9, 0
src a9, xl, a9
src xl, xh, xl
srl xh, xh
/* Negate y. */
slli a11, a6, 11
xor yh, yh, a11
.Lsub_subx:
sub xl, yl, xl
sub xh, yh, xh
bgeu yl, xl, 1f
addi xh, xh, -1
1:
/* Subtract the leftover bits in a9 from zero and propagate any
borrow from xh/xl. */
neg a9, a9
beqz a9, 1f
addi a5, xh, -1
moveqz xh, a5, xl
addi xl, xl, -1
1:
/* Check if the subtract underflowed into the exponent. */
extui a10, xh, 20, 11
bne a10, a8, .Lsub_borrow
.Lsub_round:
/* Round up if the leftover fraction is >= 1/2. */
bgez a9, 1f
addi xl, xl, 1
beqz xl, .Lsub_roundcarry
/* Check if the leftover fraction is exactly 1/2. */
slli a9, a9, 1
beqz a9, .Lsub_exactlyhalf
1: leaf_return
.Lsub_xexpzero:
/* Same as "yexpzero". */
slli xh, xh, 12
srli xh, xh, 12
bnone yh, a6, .Lsub_xexpdiff
addi a7, a7, 1
j .Lsub_xexpdiff
.Lsub_bigshiftx:
/* Mostly the same thing as "bigshifty", but with the sign bit of the
shifted value set so that the subsequent subtraction flips the
sign of y. */
bgeui a10, 64, .Lsub_returny
ssr a10
sll a11, xl
src a9, xh, xl
srl xl, xh
slli xh, a6, 11 /* set sign bit of xh */
beqz a11, .Lsub_subx
or a9, a9, a10
j .Lsub_subx
.Lsub_returny:
/* Negate and return y. */
slli a7, a6, 11
xor xh, yh, a7
mov xl, yl
leaf_return
.Lsub_borrow:
/* The subtraction has underflowed into the exponent field, so the
value needs to be renormalized. Shift the mantissa left as
needed to remove any leading zeros and adjust the exponent
accordingly. If the exponent is not large enough to remove
all the leading zeros, the result will be a subnormal value. */
slli a8, xh, 12
beqz a8, .Lsub_xhzero
do_nsau a6, a8, a7, a11
srli a8, a8, 12
bge a6, a10, .Lsub_subnormal
addi a6, a6, 1
.Lsub_shift_lt32:
/* Shift the mantissa (a8/xl/a9) left by a6. */
ssl a6
src a8, a8, xl
src xl, xl, a9
sll a9, a9
/* Combine the shifted mantissa with the sign and exponent,
decrementing the exponent by a6. (The exponent has already
been decremented by one due to the borrow from the subtraction,
but adding the mantissa will increment the exponent by one.) */
srli xh, xh, 20
sub xh, xh, a6
slli xh, xh, 20
add xh, xh, a8
j .Lsub_round
.Lsub_exactlyhalf:
/* Round down to the nearest even value. */
srli xl, xl, 1
slli xl, xl, 1
leaf_return
.Lsub_roundcarry:
/* xl is always zero when the rounding increment overflows, so
there's no need to round it to an even value. */
addi xh, xh, 1
/* Overflow to the exponent is OK. */
leaf_return
.Lsub_xhzero:
/* When normalizing the result, all the mantissa bits in the high
word are zero. Shift by "20 + (leading zero count of xl) + 1". */
do_nsau a6, xl, a7, a11
addi a6, a6, 21
blt a10, a6, .Lsub_subnormal
.Lsub_normalize_shift:
bltui a6, 32, .Lsub_shift_lt32
ssl a6
src a8, xl, a9
sll xl, a9
movi a9, 0
srli xh, xh, 20
sub xh, xh, a6
slli xh, xh, 20
add xh, xh, a8
j .Lsub_round
.Lsub_subnormal:
/* The exponent is too small to shift away all the leading zeros.
Set a6 to the current exponent (which has already been
decremented by the borrow) so that the exponent of the result
will be zero. Do not add 1 to a6 in this case, because: (1)
adding the mantissa will not increment the exponent, so there is
no need to subtract anything extra from the exponent to
compensate, and (2) the effective exponent of a subnormal is 1
not 0 so the shift amount must be 1 smaller than normal. */
mov a6, a10
j .Lsub_normalize_shift
#endif /* L_addsubdf3 */
#ifdef L_muldf3
/* Multiplication */
#if !XCHAL_HAVE_MUL16 && !XCHAL_HAVE_MUL32 && !XCHAL_HAVE_MAC16
#define XCHAL_NO_MUL 1
#endif
__muldf3_aux:
/* Handle unusual cases (zeros, subnormals, NaNs and Infinities).
(This code is placed before the start of the function just to
keep it in range of the limited branch displacements.) */
.Lmul_xexpzero:
/* Clear the sign bit of x. */
slli xh, xh, 1
srli xh, xh, 1
/* If x is zero, return zero. */
or a10, xh, xl
beqz a10, .Lmul_return_zero
/* Normalize x. Adjust the exponent in a8. */
beqz xh, .Lmul_xh_zero
do_nsau a10, xh, a11, a12
addi a10, a10, -11
ssl a10
src xh, xh, xl
sll xl, xl
movi a8, 1
sub a8, a8, a10
j .Lmul_xnormalized
.Lmul_xh_zero:
do_nsau a10, xl, a11, a12
addi a10, a10, -11
movi a8, -31
sub a8, a8, a10
ssl a10
bltz a10, .Lmul_xl_srl
sll xh, xl
movi xl, 0
j .Lmul_xnormalized
.Lmul_xl_srl:
srl xh, xl
sll xl, xl
j .Lmul_xnormalized
.Lmul_yexpzero:
/* Clear the sign bit of y. */
slli yh, yh, 1
srli yh, yh, 1
/* If y is zero, return zero. */
or a10, yh, yl
beqz a10, .Lmul_return_zero
/* Normalize y. Adjust the exponent in a9. */
beqz yh, .Lmul_yh_zero
do_nsau a10, yh, a11, a12
addi a10, a10, -11
ssl a10
src yh, yh, yl
sll yl, yl
movi a9, 1
sub a9, a9, a10
j .Lmul_ynormalized
.Lmul_yh_zero:
do_nsau a10, yl, a11, a12
addi a10, a10, -11
movi a9, -31
sub a9, a9, a10
ssl a10
bltz a10, .Lmul_yl_srl
sll yh, yl
movi yl, 0
j .Lmul_ynormalized
.Lmul_yl_srl:
srl yh, yl
sll yl, yl
j .Lmul_ynormalized
.Lmul_return_zero:
/* Return zero with the appropriate sign bit. */
srli xh, a7, 31
slli xh, xh, 31
movi xl, 0
j .Lmul_done
.Lmul_xnan_or_inf:
/* If y is zero, return NaN. */
bnez yl, 1f
slli a8, yh, 1
bnez a8, 1f
movi a4, 0x80000 /* make it a quiet NaN */
or xh, xh, a4
j .Lmul_done
1:
/* If y is NaN, return y. */
bnall yh, a6, .Lmul_returnx
slli a8, yh, 12
or a8, a8, yl
beqz a8, .Lmul_returnx
.Lmul_returny:
mov xh, yh
mov xl, yl
.Lmul_returnx:
/* Set the sign bit and return. */
extui a7, a7, 31, 1
slli xh, xh, 1
ssai 1
src xh, a7, xh
j .Lmul_done
.Lmul_ynan_or_inf:
/* If x is zero, return NaN. */
bnez xl, .Lmul_returny
slli a8, xh, 1
bnez a8, .Lmul_returny
movi a7, 0x80000 /* make it a quiet NaN */
or xh, yh, a7
j .Lmul_done
.align 4
.global __muldf3
.type __muldf3, @function
__muldf3:
#if __XTENSA_CALL0_ABI__
leaf_entry sp, 32
addi sp, sp, -32
s32i a12, sp, 16
s32i a13, sp, 20
s32i a14, sp, 24
s32i a15, sp, 28
#elif XCHAL_NO_MUL
/* This is not really a leaf function; allocate enough stack space
to allow CALL12s to a helper function. */
leaf_entry sp, 64
#else
leaf_entry sp, 32
#endif
movi a6, 0x7ff00000
/* Get the sign of the result. */
xor a7, xh, yh
/* Check for NaN and infinity. */
ball xh, a6, .Lmul_xnan_or_inf
ball yh, a6, .Lmul_ynan_or_inf
/* Extract the exponents. */
extui a8, xh, 20, 11
extui a9, yh, 20, 11
beqz a8, .Lmul_xexpzero
.Lmul_xnormalized:
beqz a9, .Lmul_yexpzero
.Lmul_ynormalized:
/* Add the exponents. */
add a8, a8, a9
/* Replace sign/exponent fields with explicit "1.0". */
movi a10, 0x1fffff
or xh, xh, a6
and xh, xh, a10
or yh, yh, a6
and yh, yh, a10
/* Multiply 64x64 to 128 bits. The result ends up in xh/xl/a6.
The least-significant word of the result is thrown away except
that if it is nonzero, the lsb of a6 is set to 1. */
#if XCHAL_HAVE_MUL32_HIGH
/* Compute a6 with any carry-outs in a10. */
movi a10, 0
mull a6, xl, yh
mull a11, xh, yl
add a6, a6, a11
bgeu a6, a11, 1f
addi a10, a10, 1
1:
muluh a11, xl, yl
add a6, a6, a11
bgeu a6, a11, 1f
addi a10, a10, 1
1:
/* If the low word of the result is nonzero, set the lsb of a6. */
mull a11, xl, yl
beqz a11, 1f
movi a9, 1
or a6, a6, a9
1:
/* Compute xl with any carry-outs in a9. */
movi a9, 0
mull a11, xh, yh
add a10, a10, a11
bgeu a10, a11, 1f
addi a9, a9, 1
1:
muluh a11, xh, yl
add a10, a10, a11
bgeu a10, a11, 1f
addi a9, a9, 1
1:
muluh xl, xl, yh
add xl, xl, a10
bgeu xl, a10, 1f
addi a9, a9, 1
1:
/* Compute xh. */
muluh xh, xh, yh
add xh, xh, a9
#else /* ! XCHAL_HAVE_MUL32_HIGH */
/* Break the inputs into 16-bit chunks and compute 16 32-bit partial
products. These partial products are:
0 xll * yll
1 xll * ylh
2 xlh * yll
3 xll * yhl
4 xlh * ylh
5 xhl * yll
6 xll * yhh
7 xlh * yhl
8 xhl * ylh
9 xhh * yll
10 xlh * yhh
11 xhl * yhl
12 xhh * ylh
13 xhl * yhh
14 xhh * yhl
15 xhh * yhh
where the input chunks are (hh, hl, lh, ll). If using the Mul16
or Mul32 multiplier options, these input chunks must be stored in
separate registers. For Mac16, the UMUL.AA.* opcodes can specify
that the inputs come from either half of the registers, so there
is no need to shift them out ahead of time. If there is no
multiply hardware, the 16-bit chunks can be extracted when setting
up the arguments to the separate multiply function. */
/* Save a7 since it is needed to hold a temporary value. */
s32i a7, sp, 4
#if __XTENSA_CALL0_ABI__ && XCHAL_NO_MUL
/* Calling a separate multiply function will clobber a0 and requires
use of a8 as a temporary, so save those values now. (The function
uses a custom ABI so nothing else needs to be saved.) */
s32i a0, sp, 0
s32i a8, sp, 8
#endif
#if XCHAL_HAVE_MUL16 || XCHAL_HAVE_MUL32
#define xlh a12
#define ylh a13
#define xhh a14
#define yhh a15
/* Get the high halves of the inputs into registers. */
srli xlh, xl, 16
srli ylh, yl, 16
srli xhh, xh, 16
srli yhh, yh, 16
#define xll xl
#define yll yl
#define xhl xh
#define yhl yh
#if XCHAL_HAVE_MUL32 && !XCHAL_HAVE_MUL16
/* Clear the high halves of the inputs. This does not matter
for MUL16 because the high bits are ignored. */
extui xl, xl, 0, 16
extui xh, xh, 0, 16
extui yl, yl, 0, 16
extui yh, yh, 0, 16
#endif
#endif /* MUL16 || MUL32 */
#if XCHAL_HAVE_MUL16
#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
mul16u dst, xreg ## xhalf, yreg ## yhalf
#elif XCHAL_HAVE_MUL32
#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
mull dst, xreg ## xhalf, yreg ## yhalf
#elif XCHAL_HAVE_MAC16
/* The preprocessor insists on inserting a space when concatenating after
a period in the definition of do_mul below. These macros are a workaround
using underscores instead of periods when doing the concatenation. */
#define umul_aa_ll umul.aa.ll
#define umul_aa_lh umul.aa.lh
#define umul_aa_hl umul.aa.hl
#define umul_aa_hh umul.aa.hh
#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
umul_aa_ ## xhalf ## yhalf xreg, yreg; \
rsr dst, ACCLO
#else /* no multiply hardware */
#define set_arg_l(dst, src) \
extui dst, src, 0, 16
#define set_arg_h(dst, src) \
srli dst, src, 16
#if __XTENSA_CALL0_ABI__
#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
set_arg_ ## xhalf (a13, xreg); \
set_arg_ ## yhalf (a14, yreg); \
call0 .Lmul_mulsi3; \
mov dst, a12
#else
#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
set_arg_ ## xhalf (a14, xreg); \
set_arg_ ## yhalf (a15, yreg); \
call12 .Lmul_mulsi3; \
mov dst, a14
#endif /* __XTENSA_CALL0_ABI__ */
#endif /* no multiply hardware */
/* Add pp1 and pp2 into a10 with carry-out in a9. */
do_mul(a10, xl, l, yl, h) /* pp 1 */
do_mul(a11, xl, h, yl, l) /* pp 2 */
movi a9, 0
add a10, a10, a11
bgeu a10, a11, 1f
addi a9, a9, 1
1:
/* Initialize a6 with a9/a10 shifted into position. Note that
this value can be safely incremented without any carry-outs. */
ssai 16
src a6, a9, a10
/* Compute the low word into a10. */
do_mul(a11, xl, l, yl, l) /* pp 0 */
sll a10, a10
add a10, a10, a11
bgeu a10, a11, 1f
addi a6, a6, 1
1:
/* Compute the contributions of pp0-5 to a6, with carry-outs in a9.
This is good enough to determine the low half of a6, so that any
nonzero bits from the low word of the result can be collapsed
into a6, freeing up a register. */
movi a9, 0
do_mul(a11, xl, l, yh, l) /* pp 3 */
add a6, a6, a11
bgeu a6, a11, 1f
addi a9, a9, 1
1:
do_mul(a11, xl, h, yl, h) /* pp 4 */
add a6, a6, a11
bgeu a6, a11, 1f
addi a9, a9, 1
1:
do_mul(a11, xh, l, yl, l) /* pp 5 */
add a6, a6, a11
bgeu a6, a11, 1f
addi a9, a9, 1
1:
/* Collapse any nonzero bits from the low word into a6. */
beqz a10, 1f
movi a11, 1
or a6, a6, a11
1:
/* Add pp6-9 into a11 with carry-outs in a10. */
do_mul(a7, xl, l, yh, h) /* pp 6 */
do_mul(a11, xh, h, yl, l) /* pp 9 */
movi a10, 0
add a11, a11, a7
bgeu a11, a7, 1f
addi a10, a10, 1
1:
do_mul(a7, xl, h, yh, l) /* pp 7 */
add a11, a11, a7
bgeu a11, a7, 1f
addi a10, a10, 1
1:
do_mul(a7, xh, l, yl, h) /* pp 8 */
add a11, a11, a7
bgeu a11, a7, 1f
addi a10, a10, 1
1:
/* Shift a10/a11 into position, and add low half of a11 to a6. */
src a10, a10, a11
add a10, a10, a9
sll a11, a11
add a6, a6, a11
bgeu a6, a11, 1f
addi a10, a10, 1
1:
/* Add pp10-12 into xl with carry-outs in a9. */
movi a9, 0
do_mul(xl, xl, h, yh, h) /* pp 10 */
add xl, xl, a10
bgeu xl, a10, 1f
addi a9, a9, 1
1:
do_mul(a10, xh, l, yh, l) /* pp 11 */
add xl, xl, a10
bgeu xl, a10, 1f
addi a9, a9, 1
1:
do_mul(a10, xh, h, yl, h) /* pp 12 */
add xl, xl, a10
bgeu xl, a10, 1f
addi a9, a9, 1
1:
/* Add pp13-14 into a11 with carry-outs in a10. */
do_mul(a11, xh, l, yh, h) /* pp 13 */
do_mul(a7, xh, h, yh, l) /* pp 14 */
movi a10, 0
add a11, a11, a7
bgeu a11, a7, 1f
addi a10, a10, 1
1:
/* Shift a10/a11 into position, and add low half of a11 to a6. */
src a10, a10, a11
add a10, a10, a9
sll a11, a11
add xl, xl, a11
bgeu xl, a11, 1f
addi a10, a10, 1
1:
/* Compute xh. */
do_mul(xh, xh, h, yh, h) /* pp 15 */
add xh, xh, a10
/* Restore values saved on the stack during the multiplication. */
l32i a7, sp, 4
#if __XTENSA_CALL0_ABI__ && XCHAL_NO_MUL
l32i a0, sp, 0
l32i a8, sp, 8
#endif
#endif /* ! XCHAL_HAVE_MUL32_HIGH */
/* Shift left by 12 bits, unless there was a carry-out from the
multiply, in which case, shift by 11 bits and increment the
exponent. Note: It is convenient to use the constant 0x3ff
instead of 0x400 when removing the extra exponent bias (so that
it is easy to construct 0x7fe for the overflow check). Reverse
the logic here to decrement the exponent sum by one unless there
was a carry-out. */
movi a4, 11
srli a5, xh, 21 - 12
bnez a5, 1f
addi a4, a4, 1
addi a8, a8, -1
1: ssl a4
src xh, xh, xl
src xl, xl, a6
sll a6, a6
/* Subtract the extra bias from the exponent sum (plus one to account
for the explicit "1.0" of the mantissa that will be added to the
exponent in the final result). */
movi a4, 0x3ff
sub a8, a8, a4
/* Check for over/underflow. The value in a8 is one less than the
final exponent, so values in the range 0..7fd are OK here. */
slli a4, a4, 1 /* 0x7fe */
bgeu a8, a4, .Lmul_overflow
.Lmul_round:
/* Round. */
bgez a6, .Lmul_rounded
addi xl, xl, 1
beqz xl, .Lmul_roundcarry
slli a6, a6, 1
beqz a6, .Lmul_exactlyhalf
.Lmul_rounded:
/* Add the exponent to the mantissa. */
slli a8, a8, 20
add xh, xh, a8
.Lmul_addsign:
/* Add the sign bit. */
srli a7, a7, 31
slli a7, a7, 31
or xh, xh, a7
.Lmul_done:
#if __XTENSA_CALL0_ABI__
l32i a12, sp, 16
l32i a13, sp, 20
l32i a14, sp, 24
l32i a15, sp, 28
addi sp, sp, 32
#endif
leaf_return
.Lmul_exactlyhalf:
/* Round down to the nearest even value. */
srli xl, xl, 1
slli xl, xl, 1
j .Lmul_rounded
.Lmul_roundcarry:
/* xl is always zero when the rounding increment overflows, so
there's no need to round it to an even value. */
addi xh, xh, 1
/* Overflow is OK -- it will be added to the exponent. */
j .Lmul_rounded
.Lmul_overflow:
bltz a8, .Lmul_underflow
/* Return +/- Infinity. */
addi a8, a4, 1 /* 0x7ff */
slli xh, a8, 20
movi xl, 0
j .Lmul_addsign
.Lmul_underflow:
/* Create a subnormal value, where the exponent field contains zero,
but the effective exponent is 1. The value of a8 is one less than
the actual exponent, so just negate it to get the shift amount. */
neg a8, a8
mov a9, a6
ssr a8
bgeui a8, 32, .Lmul_bigshift
/* Shift xh/xl right. Any bits that are shifted out of xl are saved
in a6 (combined with the shifted-out bits currently in a6) for
rounding the result. */
sll a6, xl
src xl, xh, xl
srl xh, xh
j 1f
.Lmul_bigshift:
bgeui a8, 64, .Lmul_flush_to_zero
sll a10, xl /* lost bits shifted out of xl */
src a6, xh, xl
srl xl, xh
movi xh, 0
or a9, a9, a10
/* Set the exponent to zero. */
1: movi a8, 0
/* Pack any nonzero bits shifted out into a6. */
beqz a9, .Lmul_round
movi a9, 1
or a6, a6, a9
j .Lmul_round
.Lmul_flush_to_zero:
/* Return zero with the appropriate sign bit. */
srli xh, a7, 31
slli xh, xh, 31
movi xl, 0
j .Lmul_done
#if XCHAL_NO_MUL
/* For Xtensa processors with no multiply hardware, this simplified
version of _mulsi3 is used for multiplying 16-bit chunks of
the floating-point mantissas. When using CALL0, this function
uses a custom ABI: the inputs are passed in a13 and a14, the
result is returned in a12, and a8 and a15 are clobbered. */
.align 4
.Lmul_mulsi3:
leaf_entry sp, 16
.macro mul_mulsi3_body dst, src1, src2, tmp1, tmp2
movi \dst, 0
1: add \tmp1, \src2, \dst
extui \tmp2, \src1, 0, 1
movnez \dst, \tmp1, \tmp2
do_addx2 \tmp1, \src2, \dst, \tmp1
extui \tmp2, \src1, 1, 1
movnez \dst, \tmp1, \tmp2
do_addx4 \tmp1, \src2, \dst, \tmp1
extui \tmp2, \src1, 2, 1
movnez \dst, \tmp1, \tmp2
do_addx8 \tmp1, \src2, \dst, \tmp1
extui \tmp2, \src1, 3, 1
movnez \dst, \tmp1, \tmp2
srli \src1, \src1, 4
slli \src2, \src2, 4
bnez \src1, 1b
.endm
#if __XTENSA_CALL0_ABI__
mul_mulsi3_body a12, a13, a14, a15, a8
#else
/* The result will be written into a2, so save that argument in a4. */
mov a4, a2
mul_mulsi3_body a2, a4, a3, a5, a6
#endif
leaf_return
#endif /* XCHAL_NO_MUL */
#endif /* L_muldf3 */
#ifdef L_divdf3
/* Division */
__divdf3_aux:
/* Handle unusual cases (zeros, subnormals, NaNs and Infinities).
(This code is placed before the start of the function just to
keep it in range of the limited branch displacements.) */
.Ldiv_yexpzero:
/* Clear the sign bit of y. */
slli yh, yh, 1
srli yh, yh, 1
/* Check for division by zero. */
or a10, yh, yl
beqz a10, .Ldiv_yzero
/* Normalize y. Adjust the exponent in a9. */
beqz yh, .Ldiv_yh_zero
do_nsau a10, yh, a11, a9
addi a10, a10, -11
ssl a10
src yh, yh, yl
sll yl, yl
movi a9, 1
sub a9, a9, a10
j .Ldiv_ynormalized
.Ldiv_yh_zero:
do_nsau a10, yl, a11, a9
addi a10, a10, -11
movi a9, -31
sub a9, a9, a10
ssl a10
bltz a10, .Ldiv_yl_srl
sll yh, yl
movi yl, 0
j .Ldiv_ynormalized
.Ldiv_yl_srl:
srl yh, yl
sll yl, yl
j .Ldiv_ynormalized
.Ldiv_yzero:
/* y is zero. Return NaN if x is also zero; otherwise, infinity. */
slli xh, xh, 1
srli xh, xh, 1
or xl, xl, xh
srli xh, a7, 31
slli xh, xh, 31
or xh, xh, a6
bnez xl, 1f
movi a4, 0x80000 /* make it a quiet NaN */
or xh, xh, a4
1: movi xl, 0
leaf_return
.Ldiv_xexpzero:
/* Clear the sign bit of x. */
slli xh, xh, 1
srli xh, xh, 1
/* If x is zero, return zero. */
or a10, xh, xl
beqz a10, .Ldiv_return_zero
/* Normalize x. Adjust the exponent in a8. */
beqz xh, .Ldiv_xh_zero
do_nsau a10, xh, a11, a8
addi a10, a10, -11
ssl a10
src xh, xh, xl
sll xl, xl
movi a8, 1
sub a8, a8, a10
j .Ldiv_xnormalized
.Ldiv_xh_zero:
do_nsau a10, xl, a11, a8
addi a10, a10, -11
movi a8, -31
sub a8, a8, a10
ssl a10
bltz a10, .Ldiv_xl_srl
sll xh, xl
movi xl, 0
j .Ldiv_xnormalized
.Ldiv_xl_srl:
srl xh, xl
sll xl, xl
j .Ldiv_xnormalized
.Ldiv_return_zero:
/* Return zero with the appropriate sign bit. */
srli xh, a7, 31
slli xh, xh, 31
movi xl, 0
leaf_return
.Ldiv_xnan_or_inf:
/* Set the sign bit of the result. */
srli a7, yh, 31
slli a7, a7, 31
xor xh, xh, a7
/* If y is NaN or Inf, return NaN. */
bnall yh, a6, 1f
movi a4, 0x80000 /* make it a quiet NaN */
or xh, xh, a4
1: leaf_return
.Ldiv_ynan_or_inf:
/* If y is Infinity, return zero. */
slli a8, yh, 12
or a8, a8, yl
beqz a8, .Ldiv_return_zero
/* y is NaN; return it. */
mov xh, yh
mov xl, yl
leaf_return
.Ldiv_highequal1:
bltu xl, yl, 2f
j 3f
.align 4
.global __divdf3
.type __divdf3, @function
__divdf3:
leaf_entry sp, 16
movi a6, 0x7ff00000
/* Get the sign of the result. */
xor a7, xh, yh
/* Check for NaN and infinity. */
ball xh, a6, .Ldiv_xnan_or_inf
ball yh, a6, .Ldiv_ynan_or_inf
/* Extract the exponents. */
extui a8, xh, 20, 11
extui a9, yh, 20, 11
beqz a9, .Ldiv_yexpzero
.Ldiv_ynormalized:
beqz a8, .Ldiv_xexpzero
.Ldiv_xnormalized:
/* Subtract the exponents. */
sub a8, a8, a9
/* Replace sign/exponent fields with explicit "1.0". */
movi a10, 0x1fffff
or xh, xh, a6
and xh, xh, a10
or yh, yh, a6
and yh, yh, a10
/* Set SAR for left shift by one. */
ssai (32 - 1)
/* The first digit of the mantissa division must be a one.
Shift x (and adjust the exponent) as needed to make this true. */
bltu yh, xh, 3f
beq yh, xh, .Ldiv_highequal1
2: src xh, xh, xl
sll xl, xl
addi a8, a8, -1
3:
/* Do the first subtraction and shift. */
sub xh, xh, yh
bgeu xl, yl, 1f
addi xh, xh, -1
1: sub xl, xl, yl
src xh, xh, xl
sll xl, xl
/* Put the quotient into a10/a11. */
movi a10, 0
movi a11, 1
/* Divide one bit at a time for 52 bits. */
movi a9, 52
#if XCHAL_HAVE_LOOPS
loop a9, .Ldiv_loopend
#endif
.Ldiv_loop:
/* Shift the quotient << 1. */
src a10, a10, a11
sll a11, a11
/* Is this digit a 0 or 1? */
bltu xh, yh, 3f
beq xh, yh, .Ldiv_highequal2
/* Output a 1 and subtract. */
2: addi a11, a11, 1
sub xh, xh, yh
bgeu xl, yl, 1f
addi xh, xh, -1
1: sub xl, xl, yl
/* Shift the dividend << 1. */
3: src xh, xh, xl
sll xl, xl
#if !XCHAL_HAVE_LOOPS
addi a9, a9, -1
bnez a9, .Ldiv_loop
#endif
.Ldiv_loopend:
/* Add the exponent bias (less one to account for the explicit "1.0"
of the mantissa that will be added to the exponent in the final
result). */
movi a9, 0x3fe
add a8, a8, a9
/* Check for over/underflow. The value in a8 is one less than the
final exponent, so values in the range 0..7fd are OK here. */
addmi a9, a9, 0x400 /* 0x7fe */
bgeu a8, a9, .Ldiv_overflow
.Ldiv_round:
/* Round. The remainder (<< 1) is in xh/xl. */
bltu xh, yh, .Ldiv_rounded
beq xh, yh, .Ldiv_highequal3
.Ldiv_roundup:
addi a11, a11, 1
beqz a11, .Ldiv_roundcarry
.Ldiv_rounded:
mov xl, a11
/* Add the exponent to the mantissa. */
slli a8, a8, 20
add xh, a10, a8
.Ldiv_addsign:
/* Add the sign bit. */
srli a7, a7, 31
slli a7, a7, 31
or xh, xh, a7
leaf_return
.Ldiv_highequal2:
bgeu xl, yl, 2b
j 3b
.Ldiv_highequal3:
bltu xl, yl, .Ldiv_rounded
bne xl, yl, .Ldiv_roundup
/* Remainder is exactly half the divisor. Round even. */
addi a11, a11, 1
beqz a11, .Ldiv_roundcarry
srli a11, a11, 1
slli a11, a11, 1
j .Ldiv_rounded
.Ldiv_overflow:
bltz a8, .Ldiv_underflow
/* Return +/- Infinity. */
addi a8, a9, 1 /* 0x7ff */
slli xh, a8, 20
movi xl, 0
j .Ldiv_addsign
.Ldiv_underflow:
/* Create a subnormal value, where the exponent field contains zero,
but the effective exponent is 1. The value of a8 is one less than
the actual exponent, so just negate it to get the shift amount. */
neg a8, a8
ssr a8
bgeui a8, 32, .Ldiv_bigshift
/* Shift a10/a11 right. Any bits that are shifted out of a11 are
saved in a6 for rounding the result. */
sll a6, a11
src a11, a10, a11
srl a10, a10
j 1f
.Ldiv_bigshift:
bgeui a8, 64, .Ldiv_flush_to_zero
sll a9, a11 /* lost bits shifted out of a11 */
src a6, a10, a11
srl a11, a10
movi a10, 0
or xl, xl, a9
/* Set the exponent to zero. */
1: movi a8, 0
/* Pack any nonzero remainder (in xh/xl) into a6. */
or xh, xh, xl
beqz xh, 1f
movi a9, 1
or a6, a6, a9
/* Round a10/a11 based on the bits shifted out into a6. */
1: bgez a6, .Ldiv_rounded
addi a11, a11, 1
beqz a11, .Ldiv_roundcarry
slli a6, a6, 1
bnez a6, .Ldiv_rounded
srli a11, a11, 1
slli a11, a11, 1
j .Ldiv_rounded
.Ldiv_roundcarry:
/* a11 is always zero when the rounding increment overflows, so
there's no need to round it to an even value. */
addi a10, a10, 1
/* Overflow to the exponent field is OK. */
j .Ldiv_rounded
.Ldiv_flush_to_zero:
/* Return zero with the appropriate sign bit. */
srli xh, a7, 31
slli xh, xh, 31
movi xl, 0
leaf_return
#endif /* L_divdf3 */
#ifdef L_cmpdf2
/* Equal and Not Equal */
.align 4
.global __eqdf2
.global __nedf2
.set __nedf2, __eqdf2
.type __eqdf2, @function
__eqdf2:
leaf_entry sp, 16
bne xl, yl, 2f
bne xh, yh, 4f
/* The values are equal but NaN != NaN. Check the exponent. */
movi a6, 0x7ff00000
ball xh, a6, 3f
/* Equal. */
movi a2, 0
leaf_return
/* Not equal. */
2: movi a2, 1
leaf_return
/* Check if the mantissas are nonzero. */
3: slli a7, xh, 12
or a7, a7, xl
j 5f
/* Check if x and y are zero with different signs. */
4: or a7, xh, yh
slli a7, a7, 1
or a7, a7, xl /* xl == yl here */
/* Equal if a7 == 0, where a7 is either abs(x | y) or the mantissa
or x when exponent(x) = 0x7ff and x == y. */
5: movi a2, 0
movi a3, 1
movnez a2, a3, a7
leaf_return
/* Greater Than */
.align 4
.global __gtdf2
.type __gtdf2, @function
__gtdf2:
leaf_entry sp, 16
movi a6, 0x7ff00000
ball xh, a6, 2f
1: bnall yh, a6, .Lle_cmp
/* Check if y is a NaN. */
slli a7, yh, 12
or a7, a7, yl
beqz a7, .Lle_cmp
movi a2, 0
leaf_return
/* Check if x is a NaN. */
2: slli a7, xh, 12
or a7, a7, xl
beqz a7, 1b
movi a2, 0
leaf_return
/* Less Than or Equal */
.align 4
.global __ledf2
.type __ledf2, @function
__ledf2:
leaf_entry sp, 16
movi a6, 0x7ff00000
ball xh, a6, 2f
1: bnall yh, a6, .Lle_cmp
/* Check if y is a NaN. */
slli a7, yh, 12
or a7, a7, yl
beqz a7, .Lle_cmp
movi a2, 1
leaf_return
/* Check if x is a NaN. */
2: slli a7, xh, 12
or a7, a7, xl
beqz a7, 1b
movi a2, 1
leaf_return
.Lle_cmp:
/* Check if x and y have different signs. */
xor a7, xh, yh
bltz a7, .Lle_diff_signs
/* Check if x is negative. */
bltz xh, .Lle_xneg
/* Check if x <= y. */
bltu xh, yh, 4f
bne xh, yh, 5f
bltu yl, xl, 5f
4: movi a2, 0
leaf_return
.Lle_xneg:
/* Check if y <= x. */
bltu yh, xh, 4b
bne yh, xh, 5f
bgeu xl, yl, 4b
5: movi a2, 1
leaf_return
.Lle_diff_signs:
bltz xh, 4b
/* Check if both x and y are zero. */
or a7, xh, yh
slli a7, a7, 1
or a7, a7, xl
or a7, a7, yl
movi a2, 1
movi a3, 0
moveqz a2, a3, a7
leaf_return
/* Greater Than or Equal */
.align 4
.global __gedf2
.type __gedf2, @function
__gedf2:
leaf_entry sp, 16
movi a6, 0x7ff00000
ball xh, a6, 2f
1: bnall yh, a6, .Llt_cmp
/* Check if y is a NaN. */
slli a7, yh, 12
or a7, a7, yl
beqz a7, .Llt_cmp
movi a2, -1
leaf_return
/* Check if x is a NaN. */
2: slli a7, xh, 12
or a7, a7, xl
beqz a7, 1b
movi a2, -1
leaf_return
/* Less Than */
.align 4
.global __ltdf2
.type __ltdf2, @function
__ltdf2:
leaf_entry sp, 16
movi a6, 0x7ff00000
ball xh, a6, 2f
1: bnall yh, a6, .Llt_cmp
/* Check if y is a NaN. */
slli a7, yh, 12
or a7, a7, yl
beqz a7, .Llt_cmp
movi a2, 0
leaf_return
/* Check if x is a NaN. */
2: slli a7, xh, 12
or a7, a7, xl
beqz a7, 1b
movi a2, 0
leaf_return
.Llt_cmp:
/* Check if x and y have different signs. */
xor a7, xh, yh
bltz a7, .Llt_diff_signs
/* Check if x is negative. */
bltz xh, .Llt_xneg
/* Check if x < y. */
bltu xh, yh, 4f
bne xh, yh, 5f
bgeu xl, yl, 5f
4: movi a2, -1
leaf_return
.Llt_xneg:
/* Check if y < x. */
bltu yh, xh, 4b
bne yh, xh, 5f
bltu yl, xl, 4b
5: movi a2, 0
leaf_return
.Llt_diff_signs:
bgez xh, 5b
/* Check if both x and y are nonzero. */
or a7, xh, yh
slli a7, a7, 1
or a7, a7, xl
or a7, a7, yl
movi a2, 0
movi a3, -1
movnez a2, a3, a7
leaf_return
/* Unordered */
.align 4
.global __unorddf2
.type __unorddf2, @function
__unorddf2:
leaf_entry sp, 16
movi a6, 0x7ff00000
ball xh, a6, 3f
1: ball yh, a6, 4f
2: movi a2, 0
leaf_return
3: slli a7, xh, 12
or a7, a7, xl
beqz a7, 1b
movi a2, 1
leaf_return
4: slli a7, yh, 12
or a7, a7, yl
beqz a7, 2b
movi a2, 1
leaf_return
#endif /* L_cmpdf2 */
#ifdef L_fixdfsi
.align 4
.global __fixdfsi
.type __fixdfsi, @function
__fixdfsi:
leaf_entry sp, 16
/* Check for NaN and Infinity. */
movi a6, 0x7ff00000
ball xh, a6, .Lfixdfsi_nan_or_inf
/* Extract the exponent and check if 0 < (exp - 0x3fe) < 32. */
extui a4, xh, 20, 11
extui a5, a6, 19, 10 /* 0x3fe */
sub a4, a4, a5
bgei a4, 32, .Lfixdfsi_maxint
blti a4, 1, .Lfixdfsi_zero
/* Add explicit "1.0" and shift << 11. */
or a7, xh, a6
ssai (32 - 11)
src a5, a7, xl
/* Shift back to the right, based on the exponent. */
ssl a4 /* shift by 32 - a4 */
srl a5, a5
/* Negate the result if sign != 0. */
neg a2, a5
movgez a2, a5, a7
leaf_return
.Lfixdfsi_nan_or_inf:
/* Handle Infinity and NaN. */
slli a4, xh, 12
or a4, a4, xl
beqz a4, .Lfixdfsi_maxint
/* Translate NaN to +maxint. */
movi xh, 0
.Lfixdfsi_maxint:
slli a4, a6, 11 /* 0x80000000 */
addi a5, a4, -1 /* 0x7fffffff */
movgez a4, a5, xh
mov a2, a4
leaf_return
.Lfixdfsi_zero:
movi a2, 0
leaf_return
#endif /* L_fixdfsi */
#ifdef L_fixdfdi
.align 4
.global __fixdfdi
.type __fixdfdi, @function
__fixdfdi:
leaf_entry sp, 16
/* Check for NaN and Infinity. */
movi a6, 0x7ff00000
ball xh, a6, .Lfixdfdi_nan_or_inf
/* Extract the exponent and check if 0 < (exp - 0x3fe) < 64. */
extui a4, xh, 20, 11
extui a5, a6, 19, 10 /* 0x3fe */
sub a4, a4, a5
bgei a4, 64, .Lfixdfdi_maxint
blti a4, 1, .Lfixdfdi_zero
/* Add explicit "1.0" and shift << 11. */
or a7, xh, a6
ssai (32 - 11)
src xh, a7, xl
sll xl, xl
/* Shift back to the right, based on the exponent. */
ssl a4 /* shift by 64 - a4 */
bgei a4, 32, .Lfixdfdi_smallshift
srl xl, xh
movi xh, 0
.Lfixdfdi_shifted:
/* Negate the result if sign != 0. */
bgez a7, 1f
neg xl, xl
neg xh, xh
beqz xl, 1f
addi xh, xh, -1
1: leaf_return
.Lfixdfdi_smallshift:
src xl, xh, xl
srl xh, xh
j .Lfixdfdi_shifted
.Lfixdfdi_nan_or_inf:
/* Handle Infinity and NaN. */
slli a4, xh, 12
or a4, a4, xl
beqz a4, .Lfixdfdi_maxint
/* Translate NaN to +maxint. */
movi xh, 0
.Lfixdfdi_maxint:
slli a7, a6, 11 /* 0x80000000 */
bgez xh, 1f
mov xh, a7
movi xl, 0
leaf_return
1: addi xh, a7, -1 /* 0x7fffffff */
movi xl, -1
leaf_return
.Lfixdfdi_zero:
movi xh, 0
movi xl, 0
leaf_return
#endif /* L_fixdfdi */
#ifdef L_fixunsdfsi
.align 4
.global __fixunsdfsi
.type __fixunsdfsi, @function
__fixunsdfsi:
leaf_entry sp, 16
/* Check for NaN and Infinity. */
movi a6, 0x7ff00000
ball xh, a6, .Lfixunsdfsi_nan_or_inf
/* Extract the exponent and check if 0 <= (exp - 0x3ff) < 32. */
extui a4, xh, 20, 11
extui a5, a6, 20, 10 /* 0x3ff */
sub a4, a4, a5
bgei a4, 32, .Lfixunsdfsi_maxint
bltz a4, .Lfixunsdfsi_zero
/* Add explicit "1.0" and shift << 11. */
or a7, xh, a6
ssai (32 - 11)
src a5, a7, xl
/* Shift back to the right, based on the exponent. */
addi a4, a4, 1
beqi a4, 32, .Lfixunsdfsi_bigexp
ssl a4 /* shift by 32 - a4 */
srl a5, a5
/* Negate the result if sign != 0. */
neg a2, a5
movgez a2, a5, a7
leaf_return
.Lfixunsdfsi_nan_or_inf:
/* Handle Infinity and NaN. */
slli a4, xh, 12
or a4, a4, xl
beqz a4, .Lfixunsdfsi_maxint
/* Translate NaN to 0xffffffff. */
movi a2, -1
leaf_return
.Lfixunsdfsi_maxint:
slli a4, a6, 11 /* 0x80000000 */
movi a5, -1 /* 0xffffffff */
movgez a4, a5, xh
mov a2, a4
leaf_return
.Lfixunsdfsi_zero:
movi a2, 0
leaf_return
.Lfixunsdfsi_bigexp:
/* Handle unsigned maximum exponent case. */
bltz xh, 1f
mov a2, a5 /* no shift needed */
leaf_return
/* Return 0x80000000 if negative. */
1: slli a2, a6, 11
leaf_return
#endif /* L_fixunsdfsi */
#ifdef L_fixunsdfdi
.align 4
.global __fixunsdfdi
.type __fixunsdfdi, @function
__fixunsdfdi:
leaf_entry sp, 16
/* Check for NaN and Infinity. */
movi a6, 0x7ff00000
ball xh, a6, .Lfixunsdfdi_nan_or_inf
/* Extract the exponent and check if 0 <= (exp - 0x3ff) < 64. */
extui a4, xh, 20, 11
extui a5, a6, 20, 10 /* 0x3ff */
sub a4, a4, a5
bgei a4, 64, .Lfixunsdfdi_maxint
bltz a4, .Lfixunsdfdi_zero
/* Add explicit "1.0" and shift << 11. */
or a7, xh, a6
ssai (32 - 11)
src xh, a7, xl
sll xl, xl
/* Shift back to the right, based on the exponent. */
addi a4, a4, 1
beqi a4, 64, .Lfixunsdfdi_bigexp
ssl a4 /* shift by 64 - a4 */
bgei a4, 32, .Lfixunsdfdi_smallshift
srl xl, xh
movi xh, 0
.Lfixunsdfdi_shifted:
/* Negate the result if sign != 0. */
bgez a7, 1f
neg xl, xl
neg xh, xh
beqz xl, 1f
addi xh, xh, -1
1: leaf_return
.Lfixunsdfdi_smallshift:
src xl, xh, xl
srl xh, xh
j .Lfixunsdfdi_shifted
.Lfixunsdfdi_nan_or_inf:
/* Handle Infinity and NaN. */
slli a4, xh, 12
or a4, a4, xl
beqz a4, .Lfixunsdfdi_maxint
/* Translate NaN to 0xffffffff.... */
1: movi xh, -1
movi xl, -1
leaf_return
.Lfixunsdfdi_maxint:
bgez xh, 1b
2: slli xh, a6, 11 /* 0x80000000 */
movi xl, 0
leaf_return
.Lfixunsdfdi_zero:
movi xh, 0
movi xl, 0
leaf_return
.Lfixunsdfdi_bigexp:
/* Handle unsigned maximum exponent case. */
bltz a7, 2b
leaf_return /* no shift needed */
#endif /* L_fixunsdfdi */
#ifdef L_floatsidf
.align 4
.global __floatunsidf
.type __floatunsidf, @function
__floatunsidf:
leaf_entry sp, 16
beqz a2, .Lfloatsidf_return_zero
/* Set the sign to zero and jump to the floatsidf code. */
movi a7, 0
j .Lfloatsidf_normalize
.align 4
.global __floatsidf
.type __floatsidf, @function
__floatsidf:
leaf_entry sp, 16
/* Check for zero. */
beqz a2, .Lfloatsidf_return_zero
/* Save the sign. */
extui a7, a2, 31, 1
/* Get the absolute value. */
#if XCHAL_HAVE_ABS
abs a2, a2
#else
neg a4, a2
movltz a2, a4, a2
#endif
.Lfloatsidf_normalize:
/* Normalize with the first 1 bit in the msb. */
do_nsau a4, a2, a5, a6
ssl a4
sll a5, a2
/* Shift the mantissa into position. */
srli xh, a5, 11
slli xl, a5, (32 - 11)
/* Set the exponent. */
movi a5, 0x41d /* 0x3fe + 31 */
sub a5, a5, a4
slli a5, a5, 20
add xh, xh, a5
/* Add the sign and return. */
slli a7, a7, 31
or xh, xh, a7
leaf_return
.Lfloatsidf_return_zero:
movi a3, 0
leaf_return
#endif /* L_floatsidf */
#ifdef L_floatdidf
.align 4
.global __floatundidf
.type __floatundidf, @function
__floatundidf:
leaf_entry sp, 16
/* Check for zero. */
or a4, xh, xl
beqz a4, 2f
/* Set the sign to zero and jump to the floatdidf code. */
movi a7, 0
j .Lfloatdidf_normalize
.align 4
.global __floatdidf
.type __floatdidf, @function
__floatdidf:
leaf_entry sp, 16
/* Check for zero. */
or a4, xh, xl
beqz a4, 2f
/* Save the sign. */
extui a7, xh, 31, 1
/* Get the absolute value. */
bgez xh, .Lfloatdidf_normalize
neg xl, xl
neg xh, xh
beqz xl, .Lfloatdidf_normalize
addi xh, xh, -1
.Lfloatdidf_normalize:
/* Normalize with the first 1 bit in the msb of xh. */
beqz xh, .Lfloatdidf_bigshift
do_nsau a4, xh, a5, a6
ssl a4
src xh, xh, xl
sll xl, xl
.Lfloatdidf_shifted:
/* Shift the mantissa into position, with rounding bits in a6. */
ssai 11
sll a6, xl
src xl, xh, xl
srl xh, xh
/* Set the exponent. */
movi a5, 0x43d /* 0x3fe + 63 */
sub a5, a5, a4
slli a5, a5, 20
add xh, xh, a5
/* Add the sign. */
slli a7, a7, 31
or xh, xh, a7
/* Round up if the leftover fraction is >= 1/2. */
bgez a6, 2f
addi xl, xl, 1
beqz xl, .Lfloatdidf_roundcarry
/* Check if the leftover fraction is exactly 1/2. */
slli a6, a6, 1
beqz a6, .Lfloatdidf_exactlyhalf
2: leaf_return
.Lfloatdidf_bigshift:
/* xh is zero. Normalize with first 1 bit of xl in the msb of xh. */
do_nsau a4, xl, a5, a6
ssl a4
sll xh, xl
movi xl, 0
addi a4, a4, 32
j .Lfloatdidf_shifted
.Lfloatdidf_exactlyhalf:
/* Round down to the nearest even value. */
srli xl, xl, 1
slli xl, xl, 1
leaf_return
.Lfloatdidf_roundcarry:
/* xl is always zero when the rounding increment overflows, so
there's no need to round it to an even value. */
addi xh, xh, 1
/* Overflow to the exponent is OK. */
leaf_return
#endif /* L_floatdidf */
#ifdef L_truncdfsf2
.align 4
.global __truncdfsf2
.type __truncdfsf2, @function
__truncdfsf2:
leaf_entry sp, 16
/* Adjust the exponent bias. */
movi a4, (0x3ff - 0x7f) << 20
sub a5, xh, a4
/* Check for underflow. */
xor a6, xh, a5
bltz a6, .Ltrunc_underflow
extui a6, a5, 20, 11
beqz a6, .Ltrunc_underflow
/* Check for overflow. */
movi a4, 255
bge a6, a4, .Ltrunc_overflow
/* Shift a5/xl << 3 into a5/a4. */
ssai (32 - 3)
src a5, a5, xl
sll a4, xl
.Ltrunc_addsign:
/* Add the sign bit. */
extui a6, xh, 31, 1
slli a6, a6, 31
or a2, a6, a5
/* Round up if the leftover fraction is >= 1/2. */
bgez a4, 1f
addi a2, a2, 1
/* Overflow to the exponent is OK. The answer will be correct. */
/* Check if the leftover fraction is exactly 1/2. */
slli a4, a4, 1
beqz a4, .Ltrunc_exactlyhalf
1: leaf_return
.Ltrunc_exactlyhalf:
/* Round down to the nearest even value. */
srli a2, a2, 1
slli a2, a2, 1
leaf_return
.Ltrunc_overflow:
/* Check if exponent == 0x7ff. */
movi a4, 0x7ff00000
bnall xh, a4, 1f
/* Check if mantissa is nonzero. */
slli a5, xh, 12
or a5, a5, xl
beqz a5, 1f
/* Shift a4 to set a bit in the mantissa, making a quiet NaN. */
srli a4, a4, 1
1: slli a4, a4, 4 /* 0xff000000 or 0xff800000 */
/* Add the sign bit. */
extui a6, xh, 31, 1
ssai 1
src a2, a6, a4
leaf_return
.Ltrunc_underflow:
/* Find shift count for a subnormal. Flush to zero if >= 32. */
extui a6, xh, 20, 11
movi a5, 0x3ff - 0x7f
sub a6, a5, a6
addi a6, a6, 1
bgeui a6, 32, 1f
/* Replace the exponent with an explicit "1.0". */
slli a5, a5, 13 /* 0x700000 */
or a5, a5, xh
slli a5, a5, 11
srli a5, a5, 11
/* Shift the mantissa left by 3 bits (into a5/a4). */
ssai (32 - 3)
src a5, a5, xl
sll a4, xl
/* Shift right by a6. */
ssr a6
sll a7, a4
src a4, a5, a4
srl a5, a5
beqz a7, .Ltrunc_addsign
or a4, a4, a6 /* any positive, nonzero value will work */
j .Ltrunc_addsign
/* Return +/- zero. */
1: extui a2, xh, 31, 1
slli a2, a2, 31
leaf_return
#endif /* L_truncdfsf2 */
#ifdef L_extendsfdf2
.align 4
.global __extendsfdf2
.type __extendsfdf2, @function
__extendsfdf2:
leaf_entry sp, 16
/* Save the sign bit and then shift it off. */
extui a5, a2, 31, 1
slli a5, a5, 31
slli a4, a2, 1
/* Extract and check the exponent. */
extui a6, a2, 23, 8
beqz a6, .Lextend_expzero
addi a6, a6, 1
beqi a6, 256, .Lextend_nan_or_inf
/* Shift >> 3 into a4/xl. */
srli a4, a4, 4
slli xl, a2, (32 - 3)
/* Adjust the exponent bias. */
movi a6, (0x3ff - 0x7f) << 20
add a4, a4, a6
/* Add the sign bit. */
or xh, a4, a5
leaf_return
.Lextend_nan_or_inf:
movi a4, 0x7ff00000
/* Check for NaN. */
slli a7, a2, 9
beqz a7, 1f
slli a6, a6, 11 /* 0x80000 */
or a4, a4, a6
/* Add the sign and return. */
1: or xh, a4, a5
movi xl, 0
leaf_return
.Lextend_expzero:
beqz a4, 1b
/* Normalize it to have 8 zero bits before the first 1 bit. */
do_nsau a7, a4, a2, a3
addi a7, a7, -8
ssl a7
sll a4, a4
/* Shift >> 3 into a4/xl. */
slli xl, a4, (32 - 3)
srli a4, a4, 3
/* Set the exponent. */
movi a6, 0x3fe - 0x7f
sub a6, a6, a7
slli a6, a6, 20
add a4, a4, a6
/* Add the sign and return. */
or xh, a4, a5
leaf_return
#endif /* L_extendsfdf2 */
|