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-rw-r--r--gcc/doc/invoke.texi10
1 files changed, 10 insertions, 0 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e019e3d2cdb..d5d5658a69f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -929,6 +929,7 @@ See RS/6000 and PowerPC Options.
-munaligned-doubles -mno-unaligned-doubles @gol
-mv8plus -mno-v8plus -mvis -mno-vis @gol
-mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol
+-mcbcond -mno-cbcond @gol
-mfmaf -mno-fmaf -mpopc -mno-popc @gol
-mfix-at697f}
@@ -19153,6 +19154,15 @@ default is @option{-mvis3} when targeting a cpu that supports such
instructions, such as niagara-3 and later. Setting @option{-mvis3}
also sets @option{-mvis2} and @option{-mvis}.
+@item -mcbcond
+@itemx -mno-cbcond
+@opindex mcbcond
+@opindex mno-cbcond
+With @option{-mcbcond}, GCC generates code that takes advantage of
+compare-and-branch instructions, as defined in the Sparc Architecture 2011.
+The default is @option{-mcbcond} when targeting a cpu that supports such
+instructions, such as niagara-4 and later.
+
@item -mpopc
@itemx -mno-popc
@opindex mpopc
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