diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 1622 |
1 files changed, 812 insertions, 810 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 46837e15389..47aa2398fe2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -28,7 +28,7 @@ [(FIRST_GPR_REGNO 0) (STACK_POINTER_REGNUM 1) (TOC_REGNUM 2) - (STATIC_CHAIN_REGNUM 11) + (STATIC_CHAIN_REGNUM 10) (HARD_FRAME_POINTER_REGNUM 31) (LAST_GPR_REGNO 31) (FIRST_FPR_REGNO 32) @@ -1211,7 +1211,7 @@ (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] "rs6000_gen_cell_microcode" "@ - lha%U1%X1 %0,%1 + lhz%U1%X1 %0,%1\;extsh %0,%0 extsh %0,%1" [(set_attr_alternative "type" [(if_then_else @@ -1284,415 +1284,415 @@ ;; IBM 405, 440, 464 and 476 half-word multiplication operations. -(define_insn "*macchwc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (plus:SI (mult:SI (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r"))) - (match_operand:SI 4 "gpc_reg_operand" "0")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (ashiftrt:SI - (match_dup 2) - (const_int 16)) - (sign_extend:SI - (match_dup 1))) - (match_dup 4)))] - "TARGET_MULHW" - "macchw. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*macchw" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r"))) - (match_operand:SI 3 "gpc_reg_operand" "0")))] - "TARGET_MULHW" - "macchw %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*macchwuc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (plus:SI (mult:SI (lshiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (zero_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r"))) - (match_operand:SI 4 "gpc_reg_operand" "0")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (lshiftrt:SI - (match_dup 2) - (const_int 16)) - (zero_extend:SI - (match_dup 1))) - (match_dup 4)))] - "TARGET_MULHW" - "macchwu. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*macchwu" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (lshiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (zero_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r"))) - (match_operand:SI 3 "gpc_reg_operand" "0")))] - "TARGET_MULHW" - "macchwu %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*machhwc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (plus:SI (mult:SI (ashiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16))) - (match_operand:SI 4 "gpc_reg_operand" "0")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (ashiftrt:SI - (match_dup 1) - (const_int 16)) - (ashiftrt:SI - (match_dup 2) - (const_int 16))) - (match_dup 4)))] - "TARGET_MULHW" - "machhw. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*machhw" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (ashiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16))) - (match_operand:SI 3 "gpc_reg_operand" "0")))] - "TARGET_MULHW" - "machhw %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*machhwuc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (plus:SI (mult:SI (lshiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (lshiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16))) - (match_operand:SI 4 "gpc_reg_operand" "0")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (lshiftrt:SI - (match_dup 1) - (const_int 16)) - (lshiftrt:SI - (match_dup 2) - (const_int 16))) - (match_dup 4)))] - "TARGET_MULHW" - "machhwu. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*machhwu" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (lshiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (lshiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16))) - (match_operand:SI 3 "gpc_reg_operand" "0")))] - "TARGET_MULHW" - "machhwu %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*maclhwc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (plus:SI (mult:SI (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "%r")) - (sign_extend:SI - (match_operand:HI 2 "gpc_reg_operand" "r"))) - (match_operand:SI 4 "gpc_reg_operand" "0")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (sign_extend:SI - (match_dup 1)) - (sign_extend:SI - (match_dup 2))) - (match_dup 4)))] - "TARGET_MULHW" - "maclhw. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*maclhw" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "%r")) - (sign_extend:SI - (match_operand:HI 2 "gpc_reg_operand" "r"))) - (match_operand:SI 3 "gpc_reg_operand" "0")))] - "TARGET_MULHW" - "maclhw %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*maclhwuc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (plus:SI (mult:SI (zero_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "%r")) - (zero_extend:SI - (match_operand:HI 2 "gpc_reg_operand" "r"))) - (match_operand:SI 4 "gpc_reg_operand" "0")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (zero_extend:SI - (match_dup 1)) - (zero_extend:SI - (match_dup 2))) - (match_dup 4)))] - "TARGET_MULHW" - "maclhwu. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*maclhwu" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (mult:SI (zero_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "%r")) - (zero_extend:SI - (match_operand:HI 2 "gpc_reg_operand" "r"))) - (match_operand:SI 3 "gpc_reg_operand" "0")))] - "TARGET_MULHW" - "maclhwu %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*nmacchwc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") - (mult:SI (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r")))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (minus:SI (match_dup 4) - (mult:SI (ashiftrt:SI - (match_dup 2) - (const_int 16)) - (sign_extend:SI - (match_dup 1)))))] - "TARGET_MULHW" - "nmacchw. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*nmacchw" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") - (mult:SI (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r")))))] - "TARGET_MULHW" - "nmacchw %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*nmachhwc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") - (mult:SI (ashiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (minus:SI (match_dup 4) - (mult:SI (ashiftrt:SI - (match_dup 1) - (const_int 16)) - (ashiftrt:SI - (match_dup 2) - (const_int 16)))))] - "TARGET_MULHW" - "nmachhw. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*nmachhw" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") - (mult:SI (ashiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)))))] - "TARGET_MULHW" - "nmachhw %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*nmaclhwc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") - (mult:SI (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "%r")) - (sign_extend:SI - (match_operand:HI 2 "gpc_reg_operand" "r")))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (minus:SI (match_dup 4) - (mult:SI (sign_extend:SI - (match_dup 1)) - (sign_extend:SI - (match_dup 2)))))] - "TARGET_MULHW" - "nmaclhw. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*nmaclhw" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") - (mult:SI (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "%r")) - (sign_extend:SI - (match_operand:HI 2 "gpc_reg_operand" "r")))))] - "TARGET_MULHW" - "nmaclhw %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*mulchwc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (mult:SI (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r"))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mult:SI (ashiftrt:SI - (match_dup 2) - (const_int 16)) - (sign_extend:SI - (match_dup 1))))] - "TARGET_MULHW" - "mulchw. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*mulchw" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mult:SI (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (sign_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r"))))] - "TARGET_MULHW" - "mulchw %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*mulchwuc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (mult:SI (lshiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (zero_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r"))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mult:SI (lshiftrt:SI - (match_dup 2) - (const_int 16)) - (zero_extend:SI - (match_dup 1))))] - "TARGET_MULHW" - "mulchwu. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*mulchwu" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mult:SI (lshiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16)) - (zero_extend:SI - (match_operand:HI 1 "gpc_reg_operand" "r"))))] - "TARGET_MULHW" - "mulchwu %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*mulhhwc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (mult:SI (ashiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mult:SI (ashiftrt:SI - (match_dup 1) - (const_int 16)) - (ashiftrt:SI - (match_dup 2) - (const_int 16))))] - "TARGET_MULHW" - "mulhhw. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*mulhhw" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mult:SI (ashiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (ashiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16))))] - "TARGET_MULHW" - "mulhhw %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*mulhhwuc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (mult:SI (lshiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (lshiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mult:SI (lshiftrt:SI - (match_dup 1) - (const_int 16)) - (lshiftrt:SI - (match_dup 2) - (const_int 16))))] - "TARGET_MULHW" - "mulhhwu. %0,%1,%2" - [(set_attr "type" "imul3")]) - -(define_insn "*mulhhwu" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mult:SI (lshiftrt:SI - (match_operand:SI 1 "gpc_reg_operand" "%r") - (const_int 16)) - (lshiftrt:SI - (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 16))))] - "TARGET_MULHW" - "mulhhwu %0,%1,%2" - [(set_attr "type" "imul3")]) +;;(define_insn "*macchwc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (plus:SI (mult:SI (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r"))) +;; (match_operand:SI 4 "gpc_reg_operand" "0")) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (ashiftrt:SI +;; (match_dup 2) +;; (const_int 16)) +;; (sign_extend:SI +;; (match_dup 1))) +;; (match_dup 4)))] +;; "TARGET_MULHW" +;; "macchw. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*macchw" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r"))) +;; (match_operand:SI 3 "gpc_reg_operand" "0")))] +;; "TARGET_MULHW" +;; "macchw %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*macchwuc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (plus:SI (mult:SI (lshiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (zero_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r"))) +;; (match_operand:SI 4 "gpc_reg_operand" "0")) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (lshiftrt:SI +;; (match_dup 2) +;; (const_int 16)) +;; (zero_extend:SI +;; (match_dup 1))) +;; (match_dup 4)))] +;; "TARGET_MULHW" +;; "macchwu. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*macchwu" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (lshiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (zero_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r"))) +;; (match_operand:SI 3 "gpc_reg_operand" "0")))] +;; "TARGET_MULHW" +;; "macchwu %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*machhwc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (plus:SI (mult:SI (ashiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16))) +;; (match_operand:SI 4 "gpc_reg_operand" "0")) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (ashiftrt:SI +;; (match_dup 1) +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_dup 2) +;; (const_int 16))) +;; (match_dup 4)))] +;; "TARGET_MULHW" +;; "machhw. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*machhw" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (ashiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16))) +;; (match_operand:SI 3 "gpc_reg_operand" "0")))] +;; "TARGET_MULHW" +;; "machhw %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*machhwuc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (plus:SI (mult:SI (lshiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (lshiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16))) +;; (match_operand:SI 4 "gpc_reg_operand" "0")) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (lshiftrt:SI +;; (match_dup 1) +;; (const_int 16)) +;; (lshiftrt:SI +;; (match_dup 2) +;; (const_int 16))) +;; (match_dup 4)))] +;; "TARGET_MULHW" +;; "machhwu. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*machhwu" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (lshiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (lshiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16))) +;; (match_operand:SI 3 "gpc_reg_operand" "0")))] +;; "TARGET_MULHW" +;; "machhwu %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*maclhwc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (plus:SI (mult:SI (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "%r")) +;; (sign_extend:SI +;; (match_operand:HI 2 "gpc_reg_operand" "r"))) +;; (match_operand:SI 4 "gpc_reg_operand" "0")) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (sign_extend:SI +;; (match_dup 1)) +;; (sign_extend:SI +;; (match_dup 2))) +;; (match_dup 4)))] +;; "TARGET_MULHW" +;; "maclhw. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*maclhw" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "%r")) +;; (sign_extend:SI +;; (match_operand:HI 2 "gpc_reg_operand" "r"))) +;; (match_operand:SI 3 "gpc_reg_operand" "0")))] +;; "TARGET_MULHW" +;; "maclhw %0,%1,%2" +;; [(set_attr "type" "imul3")]) +;; +;;(define_insn "*maclhwuc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (plus:SI (mult:SI (zero_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "%r")) +;; (zero_extend:SI +;; (match_operand:HI 2 "gpc_reg_operand" "r"))) +;; (match_operand:SI 4 "gpc_reg_operand" "0")) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (zero_extend:SI +;; (match_dup 1)) +;; (zero_extend:SI +;; (match_dup 2))) +;; (match_dup 4)))] +;; "TARGET_MULHW" +;; "maclhwu. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*maclhwu" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (plus:SI (mult:SI (zero_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "%r")) +;; (zero_extend:SI +;; (match_operand:HI 2 "gpc_reg_operand" "r"))) +;; (match_operand:SI 3 "gpc_reg_operand" "0")))] +;; "TARGET_MULHW" +;; "maclhwu %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*nmacchwc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") +;; (mult:SI (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r")))) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (minus:SI (match_dup 4) +;; (mult:SI (ashiftrt:SI +;; (match_dup 2) +;; (const_int 16)) +;; (sign_extend:SI +;; (match_dup 1)))))] +;; "TARGET_MULHW" +;; "nmacchw. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*nmacchw" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") +;; (mult:SI (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r")))))] +;; "TARGET_MULHW" +;; "nmacchw %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*nmachhwc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") +;; (mult:SI (ashiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)))) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (minus:SI (match_dup 4) +;; (mult:SI (ashiftrt:SI +;; (match_dup 1) +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_dup 2) +;; (const_int 16)))))] +;; "TARGET_MULHW" +;; "nmachhw. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*nmachhw" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") +;; (mult:SI (ashiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)))))] +;; "TARGET_MULHW" +;; "nmachhw %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*nmaclhwc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") +;; (mult:SI (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "%r")) +;; (sign_extend:SI +;; (match_operand:HI 2 "gpc_reg_operand" "r")))) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (minus:SI (match_dup 4) +;; (mult:SI (sign_extend:SI +;; (match_dup 1)) +;; (sign_extend:SI +;; (match_dup 2)))))] +;; "TARGET_MULHW" +;; "nmaclhw. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*nmaclhw" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") +;; (mult:SI (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "%r")) +;; (sign_extend:SI +;; (match_operand:HI 2 "gpc_reg_operand" "r")))))] +;; "TARGET_MULHW" +;; "nmaclhw %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*mulchwc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (mult:SI (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r"))) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (mult:SI (ashiftrt:SI +;; (match_dup 2) +;; (const_int 16)) +;; (sign_extend:SI +;; (match_dup 1))))] +;; "TARGET_MULHW" +;; "mulchw. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*mulchw" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (mult:SI (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (sign_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r"))))] +;; "TARGET_MULHW" +;; "mulchw %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*mulchwuc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (mult:SI (lshiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (zero_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r"))) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (mult:SI (lshiftrt:SI +;; (match_dup 2) +;; (const_int 16)) +;; (zero_extend:SI +;; (match_dup 1))))] +;; "TARGET_MULHW" +;; "mulchwu. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*mulchwu" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (mult:SI (lshiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16)) +;; (zero_extend:SI +;; (match_operand:HI 1 "gpc_reg_operand" "r"))))] +;; "TARGET_MULHW" +;; "mulchwu %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*mulhhwc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (mult:SI (ashiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16))) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (mult:SI (ashiftrt:SI +;; (match_dup 1) +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_dup 2) +;; (const_int 16))))] +;; "TARGET_MULHW" +;; "mulhhw. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*mulhhw" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (mult:SI (ashiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (ashiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16))))] +;; "TARGET_MULHW" +;; "mulhhw %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*mulhhwuc" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x") +;; (compare:CC (mult:SI (lshiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (lshiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16))) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (mult:SI (lshiftrt:SI +;; (match_dup 1) +;; (const_int 16)) +;; (lshiftrt:SI +;; (match_dup 2) +;; (const_int 16))))] +;; "TARGET_MULHW" +;; "mulhhwu. %0,%1,%2" +;; [(set_attr "type" "imul3")]) + +;;(define_insn "*mulhhwu" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (mult:SI (lshiftrt:SI +;; (match_operand:SI 1 "gpc_reg_operand" "%r") +;; (const_int 16)) +;; (lshiftrt:SI +;; (match_operand:SI 2 "gpc_reg_operand" "r") +;; (const_int 16))))] +;; "TARGET_MULHW" +;; "mulhhwu %0,%1,%2" +;; [(set_attr "type" "imul3")]) (define_insn "*mullhwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -2277,14 +2277,14 @@ [(set_attr "length" "4") (set_attr "type" "load")]) -(define_insn "*bswaphi2_extendsi" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (zero_extend:SI - (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))] - "" - "lhbrx %0,%y1" - [(set_attr "length" "4") - (set_attr "type" "load")]) +;;(define_insn "*bswaphi2_extendsi" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (zero_extend:SI +;; (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))] +;; "" +;; "lhbrx %0,%y1" +;; [(set_attr "length" "4") +;; (set_attr "type" "load")]) (define_expand "bswaphi2" [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "") @@ -2297,18 +2297,18 @@ operands[1] = force_reg (HImode, operands[1]); }) -(define_insn "bswaphi2_internal" - [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r") - (bswap:HI - (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r"))) - (clobber (match_scratch:SI 2 "=X,X,&r"))] - "" - "@ - lhbrx %0,%y1 - sthbrx %1,%y0 - #" - [(set_attr "length" "4,4,12") - (set_attr "type" "load,store,*")]) +;;(define_insn "bswaphi2_internal" +;; [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r") +;; (bswap:HI +;; (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r"))) +;; (clobber (match_scratch:SI 2 "=X,X,&r"))] +;; "" +;; "@ +;; lhbrx %0,%y1 +;; sthbrx %1,%y0 +;; #" +;; [(set_attr "length" "4,4,12") +;; (set_attr "type" "load,store,*")]) ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is ;; correct for -mlittle as well as -mbig. @@ -2353,17 +2353,17 @@ operands[1] = force_reg (SImode, operands[1]); }) -(define_insn "*bswapsi2_internal" - [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r") - (bswap:SI - (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))] - "" - "@ - lwbrx %0,%y1 - stwbrx %1,%y0 - #" - [(set_attr "length" "4,4,12") - (set_attr "type" "load,store,*")]) +;;(define_insn "*bswapsi2_internal" +;; [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r") +;; (bswap:SI +;; (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))] +;; "" +;; "@ +;; lwbrx %0,%y1 +;; stwbrx %1,%y0 +;; #" +;; [(set_attr "length" "4,4,12") +;; (set_attr "type" "load,store,*")]) ;; We are always BITS_BIG_ENDIAN, so the bit positions below in ;; zero_extract insns do not change for -mlittle. @@ -2711,33 +2711,33 @@ emit_insn (gen_bswapsi2 (dest2, src1)); }") -(define_insn "mulsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,I")))] - "" - "@ - mullw %0,%1,%2 - mulli %0,%1,%2" - [(set (attr "type") - (cond [(match_operand:SI 2 "s8bit_cint_operand" "") - (const_string "imul3") - (match_operand:SI 2 "short_cint_operand" "") - (const_string "imul2")] - (const_string "imul")))]) - -(define_insn "*mulsi3_internal1" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] - "TARGET_32BIT" - "@ - mullw. %3,%1,%2 - #" - [(set_attr "type" "imul_compare") - (set_attr "length" "4,8")]) +;;(define_insn "mulsi3" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") +;; (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") +;; (match_operand:SI 2 "reg_or_short_operand" "r,I")))] +;; "" +;; "@ +;; mullhw %0,%1,%2 +;; mulli %0,%1,%2" +;; [(set (attr "type") +;; (cond [(match_operand:SI 2 "s8bit_cint_operand" "") +;; (const_string "imul3") +;; (match_operand:SI 2 "short_cint_operand" "") +;; (const_string "imul2")] +;; (const_string "imul")))]) + +;;(define_insn "*mulsi3_internal1" +;; [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") +;; (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") +;; (match_operand:SI 2 "gpc_reg_operand" "r,r")) +;; (const_int 0))) +;; (clobber (match_scratch:SI 3 "=r,r"))] +;; "TARGET_32BIT" +;; "@ +;; mullw. %3,%1,%2 +;; #" +;; [(set_attr "type" "imul_compare") +;; (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -2753,19 +2753,19 @@ (const_int 0)))] "") -(define_insn "*mulsi3_internal2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (mult:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" - "@ - mullw. %0,%1,%2 - #" - [(set_attr "type" "imul_compare") - (set_attr "length" "4,8")]) +;;(define_insn "*mulsi3_internal2" +;; [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") +;; (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") +;; (match_operand:SI 2 "gpc_reg_operand" "r,r")) +;; (const_int 0))) +;; (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") +;; (mult:SI (match_dup 1) (match_dup 2)))] +;; "TARGET_32BIT" +;; "@ +;; mullw. %0,%1,%2 +;; #" +;; [(set_attr "type" "imul_compare") +;; (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -2783,62 +2783,64 @@ "") -(define_insn "udiv<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "gpc_reg_operand" "r")))] - "" - "div<wd>u %0,%1,%2" - [(set_attr "type" "<idiv_ldiv>")]) +;;(define_insn "udiv<mode>3" +;; [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") +;; (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") +;; (match_operand:GPR 2 "gpc_reg_operand" "r")))] +;; "" +;;;; "div<wd>u %0,%1,%2" +;; "*return \"mr 3,%1\;mr 4,%2\;bl __udiv<mode>3\;mr %0,3\";" +;; [(set_attr "type" "<idiv_ldiv>")]) ;; For powers of two we can do srai/aze for divide and then adjust for ;; modulus. If it isn't a power of two, force operands into register and do ;; a normal divide. -(define_expand "div<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "reg_or_cint_operand" "")))] - "" -{ - if (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) <= 0 - || exact_log2 (INTVAL (operands[2])) < 0) - operands[2] = force_reg (<MODE>mode, operands[2]); -}) - -(define_insn "*div<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "gpc_reg_operand" "r")))] - "" - "div<wd> %0,%1,%2" - [(set_attr "type" "<idiv_ldiv>")]) - -(define_expand "mod<mode>3" - [(use (match_operand:GPR 0 "gpc_reg_operand" "")) - (use (match_operand:GPR 1 "gpc_reg_operand" "")) - (use (match_operand:GPR 2 "reg_or_cint_operand" ""))] - "" - " -{ - int i; - rtx temp1; - rtx temp2; - - if (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) <= 0 - || (i = exact_log2 (INTVAL (operands[2]))) < 0) - FAIL; - - temp1 = gen_reg_rtx (<MODE>mode); - temp2 = gen_reg_rtx (<MODE>mode); - - emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2])); - emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i))); - emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2)); - DONE; -}") +;;(define_expand "div<mode>3" +;; [(set (match_operand:GPR 0 "gpc_reg_operand" "") +;; (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") +;; (match_operand:GPR 2 "reg_or_cint_operand" "")))] +;; "" +;;{ +;; if (GET_CODE (operands[2]) != CONST_INT +;; || INTVAL (operands[2]) <= 0 +;; || exact_log2 (INTVAL (operands[2])) < 0) +;; operands[2] = force_reg (<MODE>mode, operands[2]); +;;}) + +;;(define_insn "*div<mode>3" +;; [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") +;; (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") +;; (match_operand:GPR 2 "gpc_reg_operand" "r")))] +;; "" +;; "div<wd> %0,%1,%2" +;; "*return \"mr 3,%1\;mr 4,%2\;bl __div<mode>3\;mr %0,3\";" +;; [(set_attr "type" "<idiv_ldiv>")]) + +;;(define_expand "mod<mode>3" +;; [(use (match_operand:GPR 0 "gpc_reg_operand" "")) +;; (use (match_operand:GPR 1 "gpc_reg_operand" "")) +;; (use (match_operand:GPR 2 "reg_or_cint_operand" ""))] +;; "" +;; " +;;{ +;; int i; +;; rtx temp1; +;; rtx temp2; +;; +;; if (GET_CODE (operands[2]) != CONST_INT +;; || INTVAL (operands[2]) <= 0 +;; || (i = exact_log2 (INTVAL (operands[2]))) < 0) +;; FAIL; +;; +;; temp1 = gen_reg_rtx (<MODE>mode); +;; temp2 = gen_reg_rtx (<MODE>mode); +;; +;; emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2])); +;; emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i))); +;; emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2)); +;; DONE; +;;}") (define_insn "" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") @@ -6662,18 +6664,18 @@ [(set_attr "type" "two") (set_attr "length" "8")]) -(define_insn "mulsidi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] - "! TARGET_POWERPC64" -{ - return (WORDS_BIG_ENDIAN) - ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" - : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; -} - [(set_attr "type" "imul") - (set_attr "length" "8")]) +;;(define_insn "mulsidi3" +;; [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") +;; (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) +;; (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] +;; "! TARGET_POWERPC64" +;;{ +;; return (WORDS_BIG_ENDIAN) +;; ? \"mulhw %0,%1,%2\;mullhw %L0,%1,%2\" +;; : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; +;;} +;; [(set_attr "type" "imul") +;; (set_attr "length" "8")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -6695,19 +6697,19 @@ operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); }") -(define_insn "umulsidi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") - (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] - "! TARGET_POWERPC64" - "* -{ - return (WORDS_BIG_ENDIAN) - ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" - : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; -}" - [(set_attr "type" "imul") - (set_attr "length" "8")]) +;;(define_insn "umulsidi3" +;; [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") +;; (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) +;; (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] +;; "! TARGET_POWERPC64" +;; "* +;;{ +;; return (WORDS_BIG_ENDIAN) +;; ? \"mulhwu %0,%1,%2\;mullhw %L0,%1,%2\" +;; : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; +;;}" +;; [(set_attr "type" "imul") +;; (set_attr "length" "8")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -6729,29 +6731,29 @@ operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); }") -(define_insn "smulsi3_highpart" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (truncate:SI - (lshiftrt:DI (mult:DI (sign_extend:DI - (match_operand:SI 1 "gpc_reg_operand" "%r")) - (sign_extend:DI - (match_operand:SI 2 "gpc_reg_operand" "r"))) - (const_int 32))))] - "" - "mulhw %0,%1,%2" - [(set_attr "type" "imul")]) - -(define_insn "umulsi3_highpart" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (truncate:SI - (lshiftrt:DI (mult:DI (zero_extend:DI - (match_operand:SI 1 "gpc_reg_operand" "%r")) - (zero_extend:DI - (match_operand:SI 2 "gpc_reg_operand" "r"))) - (const_int 32))))] - "" - "mulhwu %0,%1,%2" - [(set_attr "type" "imul")]) +;;(define_insn "smulsi3_highpart" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (truncate:SI +;; (lshiftrt:DI (mult:DI (sign_extend:DI +;; (match_operand:SI 1 "gpc_reg_operand" "%r")) +;; (sign_extend:DI +;; (match_operand:SI 2 "gpc_reg_operand" "r"))) +;; (const_int 32))))] +;; "" +;; "mulhw %0,%1,%2" +;; [(set_attr "type" "imul")]) + +;;(define_insn "umulsi3_highpart" +;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +;; (truncate:SI +;; (lshiftrt:DI (mult:DI (zero_extend:DI +;; (match_operand:SI 1 "gpc_reg_operand" "%r")) +;; (zero_extend:DI +;; (match_operand:SI 2 "gpc_reg_operand" "r"))) +;; (const_int 32))))] +;; "" +;; "*return \"mr 3,%2\;mr 4,%1\;bl __umulsi3_highpart\;mr %0,3\";" +;; [(set_attr "type" "imul")]) ;; Shift by a variable amount is too complex to be worth open-coding. We ;; just handle shifts by constants. @@ -10374,41 +10376,41 @@ ;; TImode/PTImode is similar, except that we usually want to compute the ;; address into a register and use lsi/stsi (the exception is during reload). -(define_insn "*mov<mode>_string" - [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r") - (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))] - "! TARGET_POWERPC64 - && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode)) - && (gpc_reg_operand (operands[0], <MODE>mode) - || gpc_reg_operand (operands[1], <MODE>mode))" - "* -{ - switch (which_alternative) - { - default: - gcc_unreachable (); - case 0: - if (TARGET_STRING) - return \"stswi %1,%P0,16\"; - case 1: - return \"#\"; - case 2: - /* If the address is not used in the output, we can use lsi. Otherwise, - fall through to generating four loads. */ - if (TARGET_STRING - && ! reg_overlap_mentioned_p (operands[0], operands[1])) - return \"lswi %0,%P1,16\"; - /* ... fall through ... */ - case 3: - case 4: - case 5: - return \"#\"; - } -}" - [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*") - (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") - (const_string "always") - (const_string "conditional")))]) +;;(define_insn "*mov<mode>_string" +;; [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r") +;; (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))] +;; "! TARGET_POWERPC64 +;; && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode)) +;; && (gpc_reg_operand (operands[0], <MODE>mode) +;; || gpc_reg_operand (operands[1], <MODE>mode))" +;; "* +;;{ +;; switch (which_alternative) +;; { +;; default: +;; gcc_unreachable (); +;; case 0: +;; if (TARGET_STRING) +;; return \"stswi %1,%P0,16\"; +;; case 1: +;; return \"#\"; +;; case 2: +;; /* If the address is not used in the output, we can use lsi. Otherwise, +;; fall through to generating four loads. */ +;; if (TARGET_STRING +;; && ! reg_overlap_mentioned_p (operands[0], operands[1])) +;; return \"lswi %0,%P1,16\"; +;; /* ... fall through ... */ +;; case 3: +;; case 4: +;; case 5: +;; return \"#\"; +;; } +;;}" +;; [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*") +;; (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") +;; (const_string "always") +;; (const_string "conditional")))]) (define_insn "*mov<mode>_ppc64" [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r") @@ -10809,172 +10811,172 @@ ;; Move up to 32 bytes at a time. The fixed registers are needed because the ;; register allocator doesn't have a clue about allocating 8 word registers. ;; rD/rS = r5 is preferred, efficient form. -(define_expand "movmemsi_8reg" - [(parallel [(set (match_operand 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (use (match_operand 3 "" "")) - (clobber (reg:SI 5)) - (clobber (reg:SI 6)) - (clobber (reg:SI 7)) - (clobber (reg:SI 8)) - (clobber (reg:SI 9)) - (clobber (reg:SI 10)) - (clobber (reg:SI 11)) - (clobber (reg:SI 12)) - (clobber (match_scratch:SI 4 ""))])] - "TARGET_STRING" - "") - -(define_insn "" - [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) - (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) - (use (match_operand:SI 2 "immediate_operand" "i")) - (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) - (clobber (reg:SI 6)) - (clobber (reg:SI 7)) - (clobber (reg:SI 8)) - (clobber (reg:SI 9)) - (clobber (reg:SI 10)) - (clobber (reg:SI 11)) - (clobber (reg:SI 12)) - (clobber (match_scratch:SI 5 "=X"))] - "TARGET_STRING - && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) - || INTVAL (operands[2]) == 0) - && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) - && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) - && REGNO (operands[4]) == 5" - "lswi %4,%1,%2\;stswi %4,%0,%2" - [(set_attr "type" "store_ux") - (set_attr "cell_micro" "always") - (set_attr "length" "8")]) +;;(define_expand "movmemsi_8reg" +;; [(parallel [(set (match_operand 0 "" "") +;; (match_operand 1 "" "")) +;; (use (match_operand 2 "" "")) +;; (use (match_operand 3 "" "")) +;; (clobber (reg:SI 5)) +;; (clobber (reg:SI 6)) +;; (clobber (reg:SI 7)) +;; (clobber (reg:SI 8)) +;; (clobber (reg:SI 9)) +;; (clobber (reg:SI 10)) +;; (clobber (reg:SI 11)) +;; (clobber (reg:SI 12)) +;; (clobber (match_scratch:SI 4 ""))])] +;; "TARGET_STRING" +;; "") + +;;(define_insn "" +;; [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) +;; (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) +;; (use (match_operand:SI 2 "immediate_operand" "i")) +;; (use (match_operand:SI 3 "immediate_operand" "i")) +;; (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) +;; (clobber (reg:SI 6)) +;; (clobber (reg:SI 7)) +;; (clobber (reg:SI 8)) +;; (clobber (reg:SI 9)) +;; (clobber (reg:SI 10)) +;; (clobber (reg:SI 11)) +;; (clobber (reg:SI 12)) +;; (clobber (match_scratch:SI 5 "=X"))] +;; "TARGET_STRING +;; && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) +;; || INTVAL (operands[2]) == 0) +;; && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) +;; && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) +;; && REGNO (operands[4]) == 5" +;; "lswi %4,%1,%2\;stswi %4,%0,%2" +;; [(set_attr "type" "store_ux") +;; (set_attr "cell_micro" "always") +;; (set_attr "length" "8")]) ;; Move up to 24 bytes at a time. The fixed registers are needed because the ;; register allocator doesn't have a clue about allocating 6 word registers. ;; rD/rS = r5 is preferred, efficient form. -(define_expand "movmemsi_6reg" - [(parallel [(set (match_operand 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (use (match_operand 3 "" "")) - (clobber (reg:SI 5)) - (clobber (reg:SI 6)) - (clobber (reg:SI 7)) - (clobber (reg:SI 8)) - (clobber (reg:SI 9)) - (clobber (reg:SI 10)) - (clobber (match_scratch:SI 4 ""))])] - "TARGET_STRING" - "") - -(define_insn "" - [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) - (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) - (use (match_operand:SI 2 "immediate_operand" "i")) - (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) - (clobber (reg:SI 6)) - (clobber (reg:SI 7)) - (clobber (reg:SI 8)) - (clobber (reg:SI 9)) - (clobber (reg:SI 10)) - (clobber (match_scratch:SI 5 "=X"))] - "TARGET_STRING - && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 - && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) - && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) - && REGNO (operands[4]) == 5" - "lswi %4,%1,%2\;stswi %4,%0,%2" - [(set_attr "type" "store_ux") - (set_attr "cell_micro" "always") - (set_attr "length" "8")]) +;;(define_expand "movmemsi_6reg" +;; [(parallel [(set (match_operand 0 "" "") +;; (match_operand 1 "" "")) +;; (use (match_operand 2 "" "")) +;; (use (match_operand 3 "" "")) +;; (clobber (reg:SI 5)) +;; (clobber (reg:SI 6)) +;; (clobber (reg:SI 7)) +;; (clobber (reg:SI 8)) +;; (clobber (reg:SI 9)) +;; (clobber (reg:SI 10)) +;; (clobber (match_scratch:SI 4 ""))])] +;; "TARGET_STRING" +;; "") + +;;(define_insn "" +;; [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) +;; (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) +;; (use (match_operand:SI 2 "immediate_operand" "i")) +;; (use (match_operand:SI 3 "immediate_operand" "i")) +;; (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) +;; (clobber (reg:SI 6)) +;; (clobber (reg:SI 7)) +;; (clobber (reg:SI 8)) +;; (clobber (reg:SI 9)) +;; (clobber (reg:SI 10)) +;; (clobber (match_scratch:SI 5 "=X"))] +;; "TARGET_STRING +;; && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 +;; && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) +;; && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) +;; && REGNO (operands[4]) == 5" +;; "lswi %4,%1,%2\;stswi %4,%0,%2" +;; [(set_attr "type" "store_ux") +;; (set_attr "cell_micro" "always") +;; (set_attr "length" "8")]) ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill ;; problems with TImode. ;; rD/rS = r5 is preferred, efficient form. -(define_expand "movmemsi_4reg" - [(parallel [(set (match_operand 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (use (match_operand 3 "" "")) - (clobber (reg:SI 5)) - (clobber (reg:SI 6)) - (clobber (reg:SI 7)) - (clobber (reg:SI 8)) - (clobber (match_scratch:SI 4 ""))])] - "TARGET_STRING" - "") - -(define_insn "" - [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) - (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) - (use (match_operand:SI 2 "immediate_operand" "i")) - (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) - (clobber (reg:SI 6)) - (clobber (reg:SI 7)) - (clobber (reg:SI 8)) - (clobber (match_scratch:SI 5 "=X"))] - "TARGET_STRING - && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 - && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) - && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) - && REGNO (operands[4]) == 5" - "lswi %4,%1,%2\;stswi %4,%0,%2" - [(set_attr "type" "store_ux") - (set_attr "cell_micro" "always") - (set_attr "length" "8")]) +;;(define_expand "movmemsi_4reg" +;; [(parallel [(set (match_operand 0 "" "") +;; (match_operand 1 "" "")) +;; (use (match_operand 2 "" "")) +;; (use (match_operand 3 "" "")) +;; (clobber (reg:SI 5)) +;; (clobber (reg:SI 6)) +;; (clobber (reg:SI 7)) +;; (clobber (reg:SI 8)) +;; (clobber (match_scratch:SI 4 ""))])] +;; "TARGET_STRING" +;; "") + +;;(define_insn "" +;; [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) +;; (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) +;; (use (match_operand:SI 2 "immediate_operand" "i")) +;; (use (match_operand:SI 3 "immediate_operand" "i")) +;; (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) +;; (clobber (reg:SI 6)) +;; (clobber (reg:SI 7)) +;; (clobber (reg:SI 8)) +;; (clobber (match_scratch:SI 5 "=X"))] +;; "TARGET_STRING +;; && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 +;; && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) +;; && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) +;; && REGNO (operands[4]) == 5" +;; "lswi %4,%1,%2\;stswi %4,%0,%2" +;; [(set_attr "type" "store_ux") +;; (set_attr "cell_micro" "always") +;; (set_attr "length" "8")]) ;; Move up to 8 bytes at a time. -(define_expand "movmemsi_2reg" - [(parallel [(set (match_operand 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (use (match_operand 3 "" "")) - (clobber (match_scratch:DI 4 "")) - (clobber (match_scratch:SI 5 ""))])] - "TARGET_STRING && ! TARGET_POWERPC64" - "") - -(define_insn "" - [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) - (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) - (use (match_operand:SI 2 "immediate_operand" "i")) - (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_scratch:DI 4 "=&r")) - (clobber (match_scratch:SI 5 "=X"))] - "TARGET_STRING && ! TARGET_POWERPC64 - && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" - "lswi %4,%1,%2\;stswi %4,%0,%2" - [(set_attr "type" "store_ux") - (set_attr "cell_micro" "always") - (set_attr "length" "8")]) +;;(define_expand "movmemsi_2reg" +;; [(parallel [(set (match_operand 0 "" "") +;; (match_operand 1 "" "")) +;; (use (match_operand 2 "" "")) +;; (use (match_operand 3 "" "")) +;; (clobber (match_scratch:DI 4 "")) +;; (clobber (match_scratch:SI 5 ""))])] +;; "TARGET_STRING && ! TARGET_POWERPC64" +;; "") + +;;(define_insn "" +;; [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) +;; (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) +;; (use (match_operand:SI 2 "immediate_operand" "i")) +;; (use (match_operand:SI 3 "immediate_operand" "i")) +;; (clobber (match_scratch:DI 4 "=&r")) +;; (clobber (match_scratch:SI 5 "=X"))] +;; "TARGET_STRING && ! TARGET_POWERPC64 +;; && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" +;; "lswi %4,%1,%2\;stswi %4,%0,%2" +;; [(set_attr "type" "store_ux") +;; (set_attr "cell_micro" "always") +;; (set_attr "length" "8")]) ;; Move up to 4 bytes at a time. -(define_expand "movmemsi_1reg" - [(parallel [(set (match_operand 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (use (match_operand 3 "" "")) - (clobber (match_scratch:SI 4 "")) - (clobber (match_scratch:SI 5 ""))])] - "TARGET_STRING" - "") - -(define_insn "" - [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) - (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) - (use (match_operand:SI 2 "immediate_operand" "i")) - (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_scratch:SI 4 "=&r")) - (clobber (match_scratch:SI 5 "=X"))] - "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" - "lswi %4,%1,%2\;stswi %4,%0,%2" - [(set_attr "type" "store_ux") - (set_attr "cell_micro" "always") - (set_attr "length" "8")]) +;;(define_expand "movmemsi_1reg" +;; [(parallel [(set (match_operand 0 "" "") +;; (match_operand 1 "" "")) +;; (use (match_operand 2 "" "")) +;; (use (match_operand 3 "" "")) +;; (clobber (match_scratch:SI 4 "")) +;; (clobber (match_scratch:SI 5 ""))])] +;; "TARGET_STRING" +;; "") + +;;(define_insn "" +;; [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) +;; (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) +;; (use (match_operand:SI 2 "immediate_operand" "i")) +;; (use (match_operand:SI 3 "immediate_operand" "i")) +;; (clobber (match_scratch:SI 4 "=&r")) +;; (clobber (match_scratch:SI 5 "=X"))] +;; "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" +;; "lswi %4,%1,%2\;stswi %4,%0,%2" +;; [(set_attr "type" "store_ux") +;; (set_attr "cell_micro" "always") +;; (set_attr "length" "8")]) ;; Define insns that do load or store with update. Some of these we can ;; get by using pre-decrement or pre-increment, but the hardware can also @@ -11039,7 +11041,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - lwzux %3,%0,%2 + lwzx %3,%0,%2\;add %0,%0,%2 lwzu %3,%2(%0)" [(set_attr "type" "load_ux,load_u")]) @@ -11067,7 +11069,7 @@ || (REG_P (operands[0]) && REGNO (operands[0]) == STACK_POINTER_REGNUM))" "@ - stwux %3,%0,%2 + stwx %3,%0,%2\;add %0,%0,%2 stwu %3,%2(%0)" [(set_attr "type" "store_ux,store_u")]) @@ -11081,7 +11083,7 @@ (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - stwux %3,%0,%2 + stwx %3,%0,%2\;add %0,%0,%2 stwu %3,%2(%0)" [(set_attr "type" "store_ux,store_u")]) @@ -11095,7 +11097,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - lhzux %3,%0,%2 + lhzx %3,%0,%2\;add %0,%0,%2 lhzu %3,%2(%0)" [(set_attr "type" "load_ux,load_u")]) @@ -11110,7 +11112,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - lhzux %3,%0,%2 + lhzx %3,%0,%2\;add %0,%0,%2 lhzu %3,%2(%0)" [(set_attr "type" "load_ux,load_u")]) @@ -11125,8 +11127,8 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - lhaux %3,%0,%2 - lhau %3,%2(%0)" + lhzx %3,%0,%2\;add %0,%0,%2\;extsh %3,%3 + lhzu %3,%2(%0)\;extsh %3,%3" [(set_attr "type" "load_ext_ux,load_ext_u")]) (define_insn "*movhi_update4" @@ -11139,7 +11141,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - sthux %3,%0,%2 + sthx %3,%0,%2\;add %0,%0,%2 sthu %3,%2(%0)" [(set_attr "type" "store_ux,store_u")]) @@ -11153,7 +11155,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - lbzux %3,%0,%2 + lbzx %3, %0, %2\;add %0,%0,%2 lbzu %3,%2(%0)" [(set_attr "type" "load_ux,load_u")]) @@ -11168,7 +11170,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - lbzux %3,%0,%2 + lbzx %3,%0,%2\;add %0,%0,%2 lbzu %3,%2(%0)" [(set_attr "type" "load_ux,load_u")]) @@ -11182,7 +11184,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - stbux %3,%0,%2 + stbx %3,%0,%2\;add %0,%0,%2 stbu %3,%2(%0)" [(set_attr "type" "store_ux,store_u")]) @@ -11224,7 +11226,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - lwzux %3,%0,%2 + lwzx %3,%0,%2\;add %0,%0,%2 lwzu %3,%2(%0)" [(set_attr "type" "load_ux,load_u")]) @@ -11238,7 +11240,7 @@ && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - stwux %3,%0,%2 + stwx %3,%0,%2\;add %0,%0,%2 stwu %3,%2(%0)" [(set_attr "type" "store_ux,store_u")]) @@ -15134,13 +15136,13 @@ "stw %2,%1" [(set_attr "type" "store")]) -(define_insn "*stmw" - [(match_parallel 0 "stmw_operation" - [(set (match_operand:SI 1 "memory_operand" "=m") - (match_operand:SI 2 "gpc_reg_operand" "r"))])] - "TARGET_MULTIPLE" - "stmw %2,%1" - [(set_attr "type" "store_ux")]) +;;(define_insn "*stmw" +;; [(match_parallel 0 "stmw_operation" +;; [(set (match_operand:SI 1 "memory_operand" "=m") +;; (match_operand:SI 2 "gpc_reg_operand" "r"))])] +;; "TARGET_MULTIPLE" +;; "stmw %2,%1" +;; [(set_attr "type" "store_ux")]) ; The following comment applies to: ; save_gpregs_* @@ -15155,13 +15157,13 @@ ; MATCH_OPERAND for that argument. That way the register rename ; optimization will not try to rename this register. ; Each pattern is repeated for each possible register number used in -; various ABIs (r11, r1, and for some functions r12) +; various ABIs (r9, r1, and for some functions r10) -(define_insn "*save_gpregs_<mode>_r11" +(define_insn "*save_gpregs_<mode>_r9" [(match_parallel 0 "any_parallel_operand" [(clobber (reg:P 65)) (use (match_operand:P 1 "symbol_ref_operand" "s")) - (use (reg:P 11)) + (use (reg:P 9)) (set (match_operand:P 2 "memory_operand" "=m") (match_operand:P 3 "gpc_reg_operand" "r"))])] "" @@ -15169,11 +15171,11 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) -(define_insn "*save_gpregs_<mode>_r12" +(define_insn "*save_gpregs_<mode>_r10" [(match_parallel 0 "any_parallel_operand" [(clobber (reg:P 65)) (use (match_operand:P 1 "symbol_ref_operand" "s")) - (use (reg:P 12)) + (use (reg:P 10)) (set (match_operand:P 2 "memory_operand" "=m") (match_operand:P 3 "gpc_reg_operand" "r"))])] "" @@ -15193,11 +15195,11 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) -(define_insn "*save_fpregs_<mode>_r11" +(define_insn "*save_fpregs_<mode>_r9" [(match_parallel 0 "any_parallel_operand" [(clobber (reg:P 65)) (use (match_operand:P 1 "symbol_ref_operand" "s")) - (use (reg:P 11)) + (use (reg:P 9)) (set (match_operand:DF 2 "memory_operand" "=m") (match_operand:DF 3 "gpc_reg_operand" "d"))])] "" @@ -15325,13 +15327,13 @@ ; MATCH_OPERAND for that argument. That way the register rename ; optimization will not try to rename this register. ; Each pattern is repeated for each possible register number used in -; various ABIs (r11, r1, and for some functions r12) +; various ABIs (r9, r1, and for some functions r12) -(define_insn "*restore_gpregs_<mode>_r11" +(define_insn "*restore_gpregs_<mode>_r9" [(match_parallel 0 "any_parallel_operand" [(clobber (match_operand:P 1 "register_operand" "=l")) (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 11)) + (use (reg:P 9)) (set (match_operand:P 3 "gpc_reg_operand" "=r") (match_operand:P 4 "memory_operand" "m"))])] "" @@ -15339,11 +15341,11 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) -(define_insn "*restore_gpregs_<mode>_r12" +(define_insn "*restore_gpregs_<mode>_r10" [(match_parallel 0 "any_parallel_operand" [(clobber (match_operand:P 1 "register_operand" "=l")) (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 12)) + (use (reg:P 10)) (set (match_operand:P 3 "gpc_reg_operand" "=r") (match_operand:P 4 "memory_operand" "m"))])] "" @@ -15363,12 +15365,12 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) -(define_insn "*return_and_restore_gpregs_<mode>_r11" +(define_insn "*return_and_restore_gpregs_<mode>_r9" [(match_parallel 0 "any_parallel_operand" [(return) (clobber (match_operand:P 1 "register_operand" "=l")) (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 11)) + (use (reg:P 9)) (set (match_operand:P 3 "gpc_reg_operand" "=r") (match_operand:P 4 "memory_operand" "m"))])] "" @@ -15376,12 +15378,12 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) -(define_insn "*return_and_restore_gpregs_<mode>_r12" +(define_insn "*return_and_restore_gpregs_<mode>_r10" [(match_parallel 0 "any_parallel_operand" [(return) (clobber (match_operand:P 1 "register_operand" "=l")) (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 12)) + (use (reg:P 10)) (set (match_operand:P 3 "gpc_reg_operand" "=r") (match_operand:P 4 "memory_operand" "m"))])] "" @@ -15402,12 +15404,12 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) -(define_insn "*return_and_restore_fpregs_<mode>_r11" +(define_insn "*return_and_restore_fpregs_<mode>_r9" [(match_parallel 0 "any_parallel_operand" [(return) (clobber (match_operand:P 1 "register_operand" "=l")) (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 11)) + (use (reg:P 9)) (set (match_operand:DF 3 "gpc_reg_operand" "=d") (match_operand:DF 4 "memory_operand" "m"))])] "" @@ -15441,12 +15443,12 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) -(define_insn "*return_and_restore_fpregs_aix_<mode>_r11" +(define_insn "*return_and_restore_fpregs_aix_<mode>_r9" [(match_parallel 0 "any_parallel_operand" [(return) (use (match_operand:P 1 "register_operand" "l")) (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 11)) + (use (reg:P 9)) (set (match_operand:DF 3 "gpc_reg_operand" "=d") (match_operand:DF 4 "memory_operand" "m"))])] "" |
