diff options
Diffstat (limited to 'gcc/config/ia64/ia64.md')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 41 |
1 files changed, 39 insertions, 2 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 4d9d4e0129f..bc4e8cbfd1b 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -4652,6 +4652,8 @@ ;; This prevents the scheduler from moving the SP decrement past FP-relative ;; stack accesses. This is the same as adddi3 plus the extra set. +;; Explicit predicated version of insn needed to check by CODE_FOR_ +;; in ia64_single_set, where despite of 2 sets this define_insn should be OK. (define_insn "prologue_allocate_stack" [(set (match_operand:DI 0 "register_operand" "=r,r,r") @@ -4664,10 +4666,31 @@ add %0 = %1, %2 adds %0 = %2, %1 addl %0 = %2, %1" - [(set_attr "itanium_class" "ialu")]) + [(set_attr "itanium_class" "ialu") + (set_attr "predicable" "no")]) + +(define_insn "prologue_allocate_stack_pr" + [(cond_exec (match_operator 0 ("predicate_operator") + [(match_operand:BI 1 ("register_operand") ("c,c,c")) + (const_int 0)]) + (parallel + [(set (match_operand:DI 2 "register_operand" "=r,r,r") + (plus:DI (match_operand:DI 3 "register_operand" "%r,r,a") + (match_operand:DI 4 "gr_reg_or_22bit_operand" "r,I,J"))) + (set (match_operand:DI 5 "register_operand" "+r,r,r") + (match_dup 5))]))] + "" + "@ + (%J0) add %2 = %3, %4 + (%J0) adds %2 = %3, %4 + (%J0) addl %2 = %3, %4" + [(set_attr "itanium_class" "ialu") + (set_attr "predicable" "no")]) ;; This prevents the scheduler from moving the SP restore past FP-relative ;; stack accesses. This is similar to movdi plus the extra set. +;; Explicit predicated version of insn needed to check by CODE_FOR_ +;; in ia64_single_set, where despite of 2 sets this define_insn should be OK. (define_insn "epilogue_deallocate_stack" [(set (match_operand:DI 0 "register_operand" "=r") @@ -4675,7 +4698,21 @@ (set (match_dup 1) (match_dup 1))] "" "mov %0 = %1" - [(set_attr "itanium_class" "ialu")]) + [(set_attr "itanium_class" "ialu") + (set_attr "predicable" "no")]) + +(define_insn "epilogue_deallocate_stack_pr" + [(cond_exec (match_operator 0 ("predicate_operator") + [(match_operand:BI 1 ("register_operand") ("c")) + (const_int 0)]) + (parallel + [(set (match_operand:DI 2 "register_operand" "=r") + (match_operand:DI 3 "register_operand" "+r")) + (set (match_dup 3) (match_dup 3))]))] + "" + "(%J0) mov %2 = %3" + [(set_attr "itanium_class" "ialu") + (set_attr "predicable" "no")]) ;; As USE insns aren't meaningful after reload, this is used instead ;; to prevent deleting instructions setting registers for EH handling |
