diff options
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/arm.c | 16 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 16 | ||||
| -rw-r--r-- | gcc/config/arm/riscix.h | 2 | ||||
| -rw-r--r-- | gcc/config/arm/riscix1-1.h | 2 |
5 files changed, 21 insertions, 21 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 181f1b02f3d..0121d0ec38c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -59,7 +59,7 @@ int arm_compare_fp; /* What type of cpu are we compiling for? */ enum processor_type arm_cpu; -/* Waht type of floating point are we compiling for? */ +/* What type of floating point are we compiling for? */ enum floating_point_type arm_fpu; /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we @@ -2425,7 +2425,7 @@ shift_op (op, amountp) multiplication by a power of 2 with the recognizer for a shift. >=32 is not a valid shift for "asl", so we must try and output a shift that produces the correct arithmetical result. - Using lsr #32 is idendical except for the fact that the carry bit + Using lsr #32 is identical except for the fact that the carry bit is not set correctly if we set the flags; but we never use the carry bit from such an operation, so we can ignore that. */ if (code == ROTATERT) @@ -3038,7 +3038,7 @@ arm_expand_prologue () if (live_regs_mask) { /* If we have to push any regs, then we must push lr as well, or - we won't get a propper return. */ + we won't get a proper return. */ live_regs_mask |= 0x4000; emit_multi_reg_push (live_regs_mask); } @@ -3075,13 +3075,13 @@ arm_expand_prologue () /* If CODE is 'd', then the X is a condition operand and the instruction should only be executed if the condition is true. - if CODE is 'D', then the X is a condition operand and the instruciton + if CODE is 'D', then the X is a condition operand and the instruction should only be executed if the condition is false: however, if the mode of the comparison is CCFPEmode, then always execute the instruction -- we do this because in these circumstances !GE does not necessarily imply LT; in these cases the instruction pattern will take care to make sure that an instruction containing %d will follow, thereby undoing the effects of - doing this instrucion unconditionally. + doing this instruction unconditionally. If CODE is 'N' then X is a floating point operand that must be negated before output. If CODE is 'B' then output a bitwise inverted value of X (a const int). @@ -3320,7 +3320,7 @@ output_load_symbol (insn, operands) abort (); /* When generating the instructions, we never mask out the bits that we - think will be always zero, then if a mistake has occured somewhere, the + think will be always zero, then if a mistake has occurred somewhere, the assembler will spot it and generate an error. */ /* If the symbol is word aligned then we might be able to reduce the @@ -3522,7 +3522,7 @@ final_prescan_insn (insn, opvec, noperands) if (GET_CODE (insn) != JUMP_INSN) return; - /* This jump might be paralled with a clobber of the condition codes + /* This jump might be paralleled with a clobber of the condition codes the jump should always come first */ if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) body = XVECEXP (body, 0, 0); @@ -3740,7 +3740,7 @@ final_prescan_insn (insn, opvec, noperands) } /* restore recog_operand (getting the attributes of other insns can destroy this array, but final.c assumes that it remains intact - accross this call; since the insn has been recognized already we + across this call; since the insn has been recognized already we call recog direct). */ recog (PATTERN (insn), insn, NULL_PTR); } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index cd783f4fefb..6241a20115d 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1278,7 +1278,7 @@ do \ #define MEMORY_MOVE_COST(MODE) 10 /* All address computations that can be done are free, but rtx cost returns - the same for practically all of them. So we weight the differnt types + the same for practically all of them. So we weight the different types of address here in the order (most pref first): PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ #define ADDRESS_COST(X) \ @@ -1306,9 +1306,9 @@ do \ /* Condition code information. */ /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, return the mode to be used for the comparison. - CCFPEmode should be used with floating inequalites, + CCFPEmode should be used with floating inequalities, CCFPmode should be used with floating equalities. - CC_NOOVmode should be used with SImode integer equalites + CC_NOOVmode should be used with SImode integer equalities. CCmode should be used otherwise. */ #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4c8717fd4ce..36d5f0697f6 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -54,7 +54,7 @@ ; but are if the branch wasn't taken; the effect is to limit the branch ; elimination scanning. -; NOCOND means that the condition codes are niether altered nor affect the +; NOCOND means that the condition codes are neither altered nor affect the ; output of this insn (define_attr "conds" "use,set,clob,jump_clob,nocond" @@ -2104,7 +2104,7 @@ ;; Operand 1 is the destination address in a register (SImode) ;; In both this routine and the next, we must be careful not to spill -;; a memory address of reg+large_const into a seperate PLUS insn, since this +;; a memory address of reg+large_const into a separate PLUS insn, since this ;; can generate unrecognizable rtl. (define_expand "storehi" @@ -3990,7 +3990,7 @@ ") ;; Don't match these patterns if we can use a conditional compare, since they -;; tell the final prescan branch elimator code that full branch inlining +;; tell the final prescan branch eliminator code that full branch inlining ;; can't be done. (define_insn "" @@ -4227,7 +4227,7 @@ ") ;; Don't match these patterns if we can use a conditional compare, since they -;; tell the final prescan branch elimator code that full branch inlining +;; tell the final prescan branch eliminator code that full branch inlining ;; can't be done. (define_insn "" @@ -4390,7 +4390,7 @@ "" "* /* If we have an operation where (op x 0) is the identity operation and - the condtional operator is LT or GE and we are comparing against zero and + the conditional operator is LT or GE and we are comparing against zero and everything is in registers then we can do this in two instructions */ if (operands[3] == const0_rtx && GET_CODE (operands[7]) != AND @@ -4435,7 +4435,7 @@ "" "* /* If we have an operation where (op x 0) is the identity operation and - the condtional operator is LT or GE and we are comparing against zero and + the conditional operator is LT or GE and we are comparing against zero and everything is in registers then we can do this in two instructions */ if (operands[5] == const0_rtx && GET_CODE (operands[7]) != AND @@ -5306,7 +5306,7 @@ ;; any of our local variables. If we call alloca then this is unsafe ;; since restoring the frame frees the memory, which is not what we want. ;; Sometimes the return might have been targeted by the final prescan: -;; if so then emit a propper return insn as well. +;; if so then emit a proper return insn as well. ;; Unfortunately, if the frame pointer is required, we don't know if the ;; current function has any implicit stack pointer adjustments that will ;; be restored by the return: we can't therefore do a tail call. @@ -5416,7 +5416,7 @@ ;; and jump direct to the subroutine. On return from the subroutine ;; execution continues at the branch; this avoids a prefetch stall. ;; We use the length attribute (via short_branch ()) to establish whether or -;; not this is possible, this is the same asthe sparc does. +;; not this is possible, this is the same as the sparc does. (define_peephole [(parallel[(call (mem:SI (match_operand:SI 0 "" "i")) diff --git a/gcc/config/arm/riscix.h b/gcc/config/arm/riscix.h index 0b6336455a6..8e60cfdd0b8 100644 --- a/gcc/config/arm/riscix.h +++ b/gcc/config/arm/riscix.h @@ -58,7 +58,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ %{!mbsd:%{!mxopen:%{!ansi: -D_BSD_C}}}" #endif -/* RISCiX has some wierd symbol name munging, that is done to the object module +/* RISCiX has some weird symbol name munging, that is done to the object module after assembly, which enables multiple libraries to be supported within one (possibly shared) library. It basically changes the symbol name of certain symbols (for example _bcopy is converted to _$bcopy if using BSD) diff --git a/gcc/config/arm/riscix1-1.h b/gcc/config/arm/riscix1-1.h index f6ceeaedb1e..826ec2f93f2 100644 --- a/gcc/config/arm/riscix1-1.h +++ b/gcc/config/arm/riscix1-1.h @@ -74,7 +74,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Some systems use __main in a way incompatible with its use in gcc, in these cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to give the same symbol without quotes for an alternative entry point. You - must define both, or niether. */ + must define both, or neither. */ #ifndef NAME__MAIN #define NAME__MAIN "__gccmain" #define SYMBOL__MAIN __gccmain |
