diff options
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 26 |
2 files changed, 26 insertions, 2 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 62c2a52b450..be5e111279d 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -19250,7 +19250,7 @@ output_fused_cbranch (rtx operands[], const char *label, rtx insn) { op3 = INTVAL(operands[3]); immed = "i"; - logical = ""; // There is no cmplwib.. instruction in PPE42 + //logical = ""; // There is no cmplwib.. instruction in PPE42 } else { diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8379598b90c..53229f0c911 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8933,6 +8933,31 @@ [(set_attr "type" "load") (set_attr "length" "4")]) +;; PPE42 lacks stwux use "stwx" then "add" +(define_insn "*movsi_internal2" + [(set (mem:SI + (pre_modify:SI (match_operand:SI 0 "gpc_reg_operand" "r") + (plus:SI (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "gpc_reg_operand" "r")))) + (match_operand:SI 1 "input_operand" "r"))] + "!TARGET_SINGLE_FPU && (rs6000_cpu == PROCESSOR_PPE42) && + REGNO (operands[0]) == REGNO (operands[2]) && + (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))" + "stwx %1,%0,%3\;add %0,%2,%3 #stwux %1,%0,%3" + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store")))]) + + (set_attr "length" "8")]) + +;; PPE42 lacks lwzux -> lwzx; then add +;; TODO + (define_insn "*movsi_internal1" [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h") (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))] @@ -13551,7 +13576,6 @@ ;; mem base reg the same ;; first mem offset is 8 byte aligned ;; second mem offset == first mem offset + 4 -;; FIXME (define_peephole [(set (match_operand:SI 0 "gpc_reg_operand" "r") (match_operand:SI 1 "offsettable_mem_operand" "m")) |
