diff options
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 1 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 1 | ||||
| -rw-r--r-- | gcc/config/rs6000/spe.md | 16 |
4 files changed, 24 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 42cbdb9eba9..c835f255d0d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2002-09-18 Nick Clifton <nickc@redhat.com> + + * config/rs60000/rs6000.c (rs6000_emit_move): Handle V1DImode moves. + * config/rs60000/rs6000.c (SPE_VECTOR_MODE): Include V1DImode. + * config/rs6000/spe.md (movv1di, movv1di_internal): New patterns. + 2002-09-17 Zack Weinberg <zack@codesourcery.com> * ABOUT-GCC-NLS: Remove reference to enquire, and out-of-date diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 0354031b0b7..fa9fb0548f2 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2645,6 +2645,7 @@ rs6000_emit_move (dest, source, mode) case V4HImode: case V2SFmode: case V2SImode: + case V1DImode: if (CONSTANT_P (operands[1]) && !easy_vector_constant (operands[1])) operands[1] = force_const_mem (mode, operands[1]); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 930bbced084..80c365d49a6 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -876,6 +876,7 @@ extern int rs6000_default_long_calls; #define SPE_VECTOR_MODE(MODE) \ ((MODE) == V4HImode \ || (MODE) == V2SFmode \ + || (MODE) == V1DImode \ || (MODE) == V2SImode) /* Define this macro to be nonzero if the port is prepared to handle diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 58423c2fff3..ab02b546ea8 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -2253,6 +2253,22 @@ evor %0,%1,%1" [(set_attr "type" "vecload")]) +(define_expand "movv1di" + [(set (match_operand:V1DI 0 "nonimmediate_operand" "") + (match_operand:V1DI 1 "any_operand" ""))] + "TARGET_SPE" + "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }") + +(define_insn "*movv1di_internal" + [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r") + (match_operand:V1DI 1 "input_operand" "r,m,r"))] + "TARGET_SPE" + "@ + evstdd%X0 %1,%y0 + evldd%X1 %0,%y1 + evor %0,%1,%1" + [(set_attr "type" "vecload")]) + (define_expand "movv4hi" [(set (match_operand:V4HI 0 "nonimmediate_operand" "") (match_operand:V4HI 1 "any_operand" ""))] |
