diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/pa/pa.md | 20 |
2 files changed, 15 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c1775ce935b..bc7f0018efb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2006-01-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * pa.md: Disparage copies between general and floating-point registers + in 32-bit move patterns. + 2006-01-16 H.J. Lu <hongjiu.lu@intel.com> PR testsuite/25741 diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index b51feb0ee16..b8131a8cf8f 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2307,9 +2307,9 @@ (define_insn "" [(set (match_operand:SI 0 "move_dest_operand" - "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,r,f") + "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,!r,!f") (match_operand:SI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,f,r"))] + "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,!f,!r"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && !TARGET_SOFT_FLOAT @@ -3869,9 +3869,9 @@ (define_insn "" [(set (match_operand:DF 0 "move_dest_operand" - "=f,*r,Q,?o,?Q,f,*r,*r,r,f") + "=f,*r,Q,?o,?Q,f,*r,*r,!r,!f") (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand" - "fG,*rG,f,*r,*r,RQ,o,RQ,f,r"))] + "fG,*rG,f,*r,*r,RQ,o,RQ,!f,!r"))] "(register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode)) && !(GET_CODE (operands[1]) == CONST_DOUBLE @@ -4043,9 +4043,9 @@ (define_insn "" [(set (match_operand:DF 0 "move_dest_operand" - "=r,?o,?Q,r,r,r,f") + "=r,?o,?Q,r,r,!r,!f") (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand" - "rG,r,r,o,RQ,f,r"))] + "rG,r,r,o,RQ,!f,!r"))] "(register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode)) && !TARGET_64BIT @@ -4185,9 +4185,9 @@ (define_insn "" [(set (match_operand:DI 0 "move_dest_operand" - "=r,o,Q,r,r,r,*f,*f,T,r,f") + "=r,o,Q,r,r,r,*f,*f,T,!r,!f") (match_operand:DI 1 "general_operand" - "rM,r,r,o*R,Q,i,*fM,RT,*f,f,r"))] + "rM,r,r,o*R,Q,i,*fM,RT,*f,!f,!r"))] "(register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode)) && !TARGET_64BIT @@ -4414,9 +4414,9 @@ (define_insn "" [(set (match_operand:SF 0 "move_dest_operand" - "=f,!*r,f,*r,Q,Q,r,f") + "=f,!*r,f,*r,Q,Q,!r,!f") (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand" - "fG,!*rG,RQ,RQ,f,*rG,f,r"))] + "fG,!*rG,RQ,RQ,f,*rG,!f,!r"))] "(register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode)) && !TARGET_SOFT_FLOAT |
