2003-10-22 David Daney <ddaney@avtrex.com)

	* include/mips-signal.h: New file.
	* sysdep/dwarf2-backtrace.cc: New file.
	* sysdep/mips: New directory.
	* sysdep/mips/locks.h: New file.
	* Makefile.am(extra_cc_files): New, to allow extra c++ files to be
	added to libgcj.
	(extra_cc_source_files): Ditto.
	* configure.host(disable_dladdr):  New shell variable passed to
	configure.
	(mips*-*-linux*): sysdeps_dir=mips,
	can_unwind_signal=yes, disable_dladdr=yes, use -mxgot.
	(mipsel*-linux* | mipsisa32el*-linux*): Enable hash synchronization.
	* configure.in:(mips*-*-linux*): Use sysdep/dwarf2-backtrace.cc to
	generate backtrace, and include/mips-signal.h as SIGNAL_HANDLER
	(HAVE_DLADDR): Make it depend on setting of disable_dladdr.
	(EXTRA_CC_FILES): New, to support conditional addition of
	sysdep/dwarf2-backtrace.cc.
	* configure: Regenerated.
	* Makefile.in: Regenerated.
	* gcj/Makefile.in: Regenerated.
	* include/config.h.in: Regenerated.
	* include/Makefile.in: Regenerated.
	* testsuite/Makefile.in: Regenerated.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@72808 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 109 insertions, 0 deletions

diff --git a/libjava/sysdep/mips/locks.h b/libjava/sysdep/mips/locks.h
new file mode 100644
index 00000000000..80509cadbbd
--- /dev/null
+++ b/libjava/sysdep/mips/locks.h
@@ -0,0 +1,109 @@
+// locks.h - Thread synchronization primitives. MIPS implementation.
+
+/* Copyright (C) 2003  Free Software Foundation
+
+   This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
+details.  */
+
+#ifndef __SYSDEP_LOCKS_H__
+#define __SYSDEP_LOCKS_H__
+
+/* Integer type big enough for object address.	*/
+typedef unsigned obj_addr_t __attribute__((__mode__(__pointer__)));
+
+
+// Atomically replace *addr by new_val if it was initially equal to old.
+// Return true if the comparison succeeded.
+// Assumed to have acquire semantics, i.e. later memory operations
+// cannot execute before the compare_and_swap finishes.
+inline static bool
+compare_and_swap(volatile obj_addr_t *addr,
+                 obj_addr_t old,
+                 obj_addr_t new_val) 
+{
+  long result;
+  __asm__ __volatile__(".set\tpush\n\t"
+                       ".set\tnoreorder\n\t"
+                       ".set\tnomacro\n\t"
+                       "1:\n\t"
+#if _MIPS_SIM == _ABIO32
+                       ".set\tmips2\n\t"
+#endif
+                       "ll\t%[result],0(%[addr])\n\t"
+                       "bne\t%[result],%[old],2f\n\t"
+                       "move\t%[result],$0\n\t"        // delay slot
+                       "move\t%[result],%[new_val]\n\t"
+                       "sc\t%[result],0(%[addr])\n\t"
+                       "beq\t%[result],$0,1b\n\t"
+                       "nop\n\t"                       // delay slot
+                       "2:\n\t"
+                       ".set\tpop"
+          : [result] "=&r" (result)
+          : [addr] "r" (addr), [new_val] "r" (new_val), [old] "r"(old)
+          : "memory");
+  return (bool) result;
+}
+
+// Set *addr to new_val with release semantics, i.e. making sure
+// that prior loads and stores complete before this
+// assignment.
+inline static void
+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
+{
+  __asm__ __volatile__(".set\tpush\n\t"
+#if _MIPS_SIM == _ABIO32
+                       ".set\tmips2\n\t"
+#endif
+                       "sync\n\t"
+                       ".set\tpop" : : : "memory");
+  *(addr) = new_val;
+}
+
+// Compare_and_swap with release semantics instead of acquire semantics.
+// On many architecture, the operation makes both guarantees, so the
+// implementation can be the same.
+inline static bool
+compare_and_swap_release(volatile obj_addr_t *addr,
+		  				     obj_addr_t old,
+						     obj_addr_t new_val)
+{
+  __asm__ __volatile__(".set\tpush\n\t"
+#if _MIPS_SIM == _ABIO32
+                       ".set\tmips2\n\t"
+#endif
+                       "sync\n\t"
+                       ".set\tpop" : : : "memory");
+  return compare_and_swap(addr, old, new_val);
+}
+
+// Ensure that subsequent instructions do not execute on stale
+// data that was loaded from memory before the barrier.
+// On X86, the hardware ensures that reads are properly ordered.
+inline static void
+read_barrier()
+{
+  __asm__ __volatile__(".set\tpush\n\t"
+#if _MIPS_SIM == _ABIO32
+                       ".set\tmips2\n\t"
+#endif
+                       "sync\n\t"
+                       ".set\tpop" : : : "memory");
+}
+
+// Ensure that prior stores to memory are completed with respect to other
+// processors.
+inline static void
+write_barrier()
+{
+  __asm__ __volatile__(".set\tpush\n\t"
+#if _MIPS_SIM == _ABIO32
+                       ".set\tmips2\n\t"
+#endif
+                       "sync\n\t"
+                       ".set\tpop" : : : "memory");
+}
+
+#endif   // __SYSDEP_LOCKS_H__