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| author | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-08-23 07:59:27 +0000 |
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| committer | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-08-23 07:59:27 +0000 |
| commit | e8c512e00ccaf5803d80ee1ca6152ddd9efb3ca4 (patch) | |
| tree | ba55effde3a479b22b09d5d780a402b43ce7c319 /libjava/java/sql/PreparedStatement.java | |
| parent | 760199f87c61d9c27a7a677867615623d93be436 (diff) | |
| download | ppe42-gcc-e8c512e00ccaf5803d80ee1ca6152ddd9efb3ca4.tar.gz ppe42-gcc-e8c512e00ccaf5803d80ee1ca6152ddd9efb3ca4.zip | |
* config/mips/mips.md (one_cmpl[sd]i2): Redefine using :GPR.
(and[sd]3, ior[sd]i3, xor[sd]i3): Likewise. Change 32-bit patterns
to use register_operand rather than uns_arith_operand as the predicate
for operand 1. Remove redundant MIPS16 force_reg() for operand 1.
(*and[sd]i3, *ior[sd]i3, *xor[sd]i3): Name formerly unnamed patterns.
Redefine using :GPR. Make same predicate change here. Extend the
commutativity of operands 1 and 2 from the SImode version to the
DImode one.
(*and[sd]i3_mips16, *ior[sd]i3_mips16, *xor[sd]i3_mips16): Likewise,
but with no predicate changes.
(*nor[sd]i3): Redefine using :GPR.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@86413 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libjava/java/sql/PreparedStatement.java')
0 files changed, 0 insertions, 0 deletions
