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authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>2008-10-11 17:57:20 +0000
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>2008-10-11 17:57:20 +0000
commit25010f2aeec81fd773ddee5f7886c86964bfc1a6 (patch)
tree82b88e121092e9168fd4b16c14c94fd32cfccb64 /libjava/classpath/lib/java/sql
parentf7bb6501b5f9d5397f8c2a6faa5472e594cb91f6 (diff)
downloadppe42-gcc-25010f2aeec81fd773ddee5f7886c86964bfc1a6.tar.gz
ppe42-gcc-25010f2aeec81fd773ddee5f7886c86964bfc1a6.zip
* config/i386/cpuid.h (__cpuid_count): New defines.
* config/i386/driver-i386.c (struct cache_desc): New structure. (describe_cache): Use struct cache_desc to pass cache descriptions. (detect_l2_cache): Ditto. Rename from decode_l2_cache. (detect_caches_amd): Use struct cache_desc to describe caches. (decode_caches_intel): Use struct cache_desc to pass cache descriptions. Update descriptions to match latest (rev -032, December 2007) CPUID documentation. Do not check valid bit here. Check for Xeon MP value 0x49 problems. (detect_caches_cpuid2): New function, split from detect_caches_intel. Check valid bit before calling decode_caches_intel. Detect number of times to repeat CPUID instruction. (detect_caches_cpuid4): New function. (detect_caches_intel): Depending on max_level, call detect_caches_cpuid2 or detect_caches_cpuid4. Call detect_l2_cache only when other methods fail to provide valid L2 cache description. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@141064 138bc75d-0d04-0410-961f-82ee72b054a4
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