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| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-05-15 17:48:26 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-05-15 17:48:26 +0000 |
| commit | c27c28571f5dcd06cf32f4f539ac5747cdafd33e (patch) | |
| tree | 942eeb0ad36c65c24effa819fc0b0ba444ddcdbc /libjava/classpath/java | |
| parent | e2be515af09e2aa25f43b973f737e93a06ebe27b (diff) | |
| download | ppe42-gcc-c27c28571f5dcd06cf32f4f539ac5747cdafd33e.tar.gz ppe42-gcc-c27c28571f5dcd06cf32f4f539ac5747cdafd33e.zip | |
* config/i386/i386.c (iy86_option_override_internal): Update
processor_alias_table for missing PTA_PRFCHW and PTA_FXSR flags. Add
PTA_POPCNT to corei7 entry and remove PTA_SSE from athlon-4 entry.
Do not enable SSE prefetch on non-SSE 3dNow! targets. Enable
TARGET_PRFCHW for TARGET_3DNOW targets.
* config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW instead
of TARGET_3DNOW.
(*prefetch_3dnow): Enable for TARGET_PRFCHW only.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198942 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libjava/classpath/java')
0 files changed, 0 insertions, 0 deletions
