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| author | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-09-27 19:33:52 +0000 |
|---|---|---|
| committer | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-09-27 19:33:52 +0000 |
| commit | 56189eab5c93f6c180b804f03a790c35aa8f9145 (patch) | |
| tree | 57bd4201f7f23a7459b159408dd7f0545ef4f526 /libjava/classpath/java/sql/SQLPermission.java | |
| parent | 6f65ddb59cbf7de3de9b14095f2f88f02fe2d2af (diff) | |
| download | ppe42-gcc-56189eab5c93f6c180b804f03a790c35aa8f9145.tar.gz ppe42-gcc-56189eab5c93f6c180b804f03a790c35aa8f9145.zip | |
[gcc]
2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
DFmode, DImode, and SFmode in the upper VSX registers based on the
-mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS
if -mpower8-vector. Combine -mvsx-timode handling with the rest
of the VSX register handling.
* config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters.
(f32_sv): Likewise.
(zero_extendsidi2_lfiwzx): Add support for loading into the
Altivec registers with -mpower8-vector. Use wu/wv constraints to
only do VSX memory options on Altivec registers.
(extendsidi2_lfiwax): Likewise.
(extendsfdf2_fpr): Likewise.
(mov<mode>_hardfloat, SF/SD modes): Likewise.
(mov<mode>_hardfloat32, DF/DD modes): Likewise.
(mov<mode>_hardfloat64, DF/DD modes): Likewise.
(movdi_internal64): Likewise.
[gcc/testsuite]
2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf
and -mupper-regs-df.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202984 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libjava/classpath/java/sql/SQLPermission.java')
0 files changed, 0 insertions, 0 deletions
