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| author | belagod <belagod@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-01-25 11:35:03 +0000 |
|---|---|---|
| committer | belagod <belagod@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-01-25 11:35:03 +0000 |
| commit | 431fc07976a47b77fa622c922c0ac2d41e019233 (patch) | |
| tree | 46cc3c9053ddcc8bc08ce8e8b61958dc8bee498f /libjava/classpath/java/sql/SQLInput.java | |
| parent | f329724595159071dd6ef0ea4a9f1f2060fd069e (diff) | |
| download | ppe42-gcc-431fc07976a47b77fa622c922c0ac2d41e019233.tar.gz ppe42-gcc-431fc07976a47b77fa622c922c0ac2d41e019233.zip | |
2013-01-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Separate sq<r>dmulh_lane
entries into lane and laneq entries.
* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_lane<mode>): Remove
AdvSIMD scalar modes.
(aarch64_sq<r>dmulh_laneq<mode>): New.
(aarch64_sq<r>dmulh_lane<mode>): New RTL pattern for Scalar AdvSIMD
modes.
* config/aarch64/arm_neon.h: Fix all the vq<r>dmulh_lane* intrinsics'
builtin implementations to relfect changes in RTL in aarch64-simd.md.
* config/aarch64/iterators.md (VCOND): New.
(VCONQ): New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@195467 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libjava/classpath/java/sql/SQLInput.java')
0 files changed, 0 insertions, 0 deletions
