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| author | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-09-06 11:02:52 +0000 |
|---|---|---|
| committer | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-09-06 11:02:52 +0000 |
| commit | 9d37257a98a0c50fb6757f8a74372714f4af74be (patch) | |
| tree | e4d27587879ef34d237340636fafbe6e7933a3c6 /libjava/classpath/java/sql/Driver.java | |
| parent | b8433293bd4832e64327db4c9bea6e1e3d28f939 (diff) | |
| download | ppe42-gcc-9d37257a98a0c50fb6757f8a74372714f4af74be.tar.gz ppe42-gcc-9d37257a98a0c50fb6757f8a74372714f4af74be.zip | |
[Patch AArch64] Fix register constraints for lane intrinsics.
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_sqdml<SBINQOPS:as>l_n<mode>_internal): Use
<vwx> iterator to ensure correct register choice.
(aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Likewise.
(aarch64_sqdmull_n<mode>): Likewise.
(aarch64_sqdmull2_n<mode>_internal): Likewise.
* config/aarch64/arm_neon.h
(vml<as><q>_lane<q>_<su>16): Use 'x' constraint for element vector.
(vml<as><q>_n_<su>16): Likewise.
(vml<as>l_high_lane<q>_<su>16): Likewise.
(vml<as>l_high_n_<su>16): Likewise.
(vml<as>l_lane<q>_<su>16): Likewise.
(vml<as>l_n_<su>16): Likewise.
(vmul<q>_lane<q>_<su>16): Likewise.
(vmul<q>_n_<su>16): Likewise.
(vmull_lane<q>_<su>16): Likewise.
(vmull_n_<su>16): Likewise.
(vmull_high_lane<q>_<su>16): Likewise.
(vmull_high_n_<su>16): Likewise.
(vqrdmulh<q>_n_s16): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202322 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libjava/classpath/java/sql/Driver.java')
0 files changed, 0 insertions, 0 deletions
